FN17: the 2017 final
The Fall 2017 final (250 points; the paper has no question 9). Work through it in order: each part gives its question in short and links to the page that solves it, and to its exam way where the page has one. Some point values are overwritten on the scan, so they read “about”. The exam ways of F1–F4 and M6 come with their rebuild in early December.
26 parts: all solved in the guide, 16 with an exam way.
FN17-1
FN17-1a (5 points)
How does DIBL change with channel length? Explain.
FN17-1b (5 points)
With 1 nF of clock load, what decoupling capacitance keeps the supply droop under 10%? Explain.
FN17-1c (5 points)
How does an NMOS transistor’s threshold vary with oxide thickness? Explain.
FN17-1d (5 points)
Why is low latency desirable in a clock distribution?
FN17-1e (5 points)
Name one mechanism of infant mortality, and how burn-in finds the chips it will kill early.
FN17-2
FN17-2a (10 points)
Two dynamic stages on and : how must the rising edge of sit against that of to avoid a race?
FN17-2b (10 points)
How must the falling edges sit to avoid collisions?
FN17-2c (5 points)
With those clocks, the logic function and the delay from A rising to Y falling.
FN17-3
FN17-3a (11 points)
A clock H-tree: the total delay from A to B, with Elmore delay for the wires.
FN17-3b (11 points)
With a buffer supply sensitivity of −0.1 at 1.2 V, the jitter from 10% supply noise.
FN17-3c
With 0.1 nH/mm of wire inductance, should inductance enter the delay analysis? Explain.
Its points are illegible on the scan.
FN17-4
FN17-4a (10 points)
Find a scan pattern that controls and observes a stuck-at-0 fault at node A: the values and their order.
FN17-4b (10 points)
After one clock, what scans out of the bad circuit, and what would the good one give?
FN17-5
FN17-5a (10 points)
Two flip-flops built from latches, the primed clocks 50 ps early, a 500 ps cycle: does it work with no logic?
FN17-5b (10 points)
The largest logic delay for which it works.
FN17-5c (10 points)
If (a) fails, how can and be changed so that it works?
FN17-5d (10 points)
The largest logic delay now.
FN17-6
FN17-6a (about 8 points)
A dynamic SRAM row decoder: sketch , , and data_out for the given inputs.
FN17-6b (8 points)
What does the decoder require of the non-overlap window of and ?
FN17-7
FN17-7a (about 8 points)
With and each input limited to 2 fF, size the path for minimum delay.
FN17-7b (12 points)
With a 500 fF branch , find a sizing close to the minimum delay.
FN17-8 (15 points)
Draw an 8-bit parallel-prefix adder from PG cells, radix-2 lookahead elements and sum cells, with its critical path.
FN17-10
FN17-10a (about 8 points)
Eight 10 µm/5 µm inverters, nA, 80 mV/decade: the on-current as a function of .
FN17-10b (about 8 points)
The chain’s delay as a function of .
FN17-10c (about 8 points)
The switching energy, leakage during the delay included, as a function of ; the that minimizes it.
FN17-11 (10 points)
A dynamic three-input OR: what must the waveforms at A, B and C satisfy, collisions included, and what does Y look like?