M5. Past midterms: pass transistors and layout

This page works every past-midterm problem on pass-transistor circuits and on stick layouts. A pass-transistor question has appeared on every midterm since 2021, and it is worth a quarter to a third of the exam: 55 of 150 points in 2021, 34 of 150 in 2023, 45 of 200 in 2024. A stick layout to read appeared on both recent midterms, for 10 and 15 points, and takes about five minutes once you know the rules.

Every answer below is re-solved here; none is copied from an answer key. Where a key disagrees, the folded note on the key at the end of the part explains why, and the table at the end lists them all.

After this page you can:

1. read a pass-transistor network node by node and name what it computes (a multiplexer, an XOR, a full adder’s sum and carry);
2. decide whether it is static, and tell a static circuit from a ratioed one by the lecture’s sizing test, including circuits with half latches;
3. find its worst output levels, counting one threshold per path and a second one where a degraded node drives a gate;
4. say what a half latch or a pair of cross-coupled PFETs restores, and what it costs;
5. draw a complementary static CMOS gate with the same function;
6. turn a stick layout into a schematic and a logic function.

Before you start

How to use this page. Each section restates one exam question with its source page (MT23-2c, p6 is Fall 2023, question 2c, physical PDF page 6) and its points, and shows the exam’s own figure. Each family opens with a short How to approach section: how to recognize the question, the moves in order, why the rules apply, and the traps. Then every part is worked the same way: what it asks, the idea behind the method, the solution in steps (each step gives its reason first), a check on the result, the answer, and one thing to remember. Try each part on your own first; open the Hint if you are stuck, and step through the solution before you press “Show all”. The answer key’s verdict is folded at the end of each part. The chapters teach each method in full, and every solution links the section.

Family	Questions (most recent first)	Points	Chapters
Pass-transistor logic	MT24-3, MT23-2, MT21-1, MT21-3	45 (of 200), 34, 30, 25 (of 150)	7, 10, 11
Stick layout to schematic	MT24-4, MT23-4	15 (of 200), 10 (of 150)	5, 9, 10

MT17 has neither family. The dynamic and domino circuits (MT17-3c, MT23-3, MT24-5) are on page M6.

Conventions the exams use

• Levels. The exams want levels relative to the supply, not numbers: $V_{DD} - V_{Tn}$VTn​, $V_{DD} - 2V_{Tn}$2VTn​, $|V_{Tp}|$∣VTp​∣, $2|V_{Tp}|$2∣VTp​∣. Where this page needs numbers, it uses Chapter 10’s $V_{DD} = 5\,\mathrm{V}$ and $V_{Tn} = |V_{Tp}| = 1\,\mathrm{V}$ (so 4 V, 3 V, 1 V, 2 V).
• The threshold rule (Chapter 10, Section 5). An NFET passes a 0 fully and a 1 only up to one $V_{Tn}$ below its own gate; a PFET passes a 1 fully and a 0 only down to one $|V_{Tp}|$ above its gate. So two NFETs in series with their gates at $V_{DD}$ lose one threshold, not two. A second threshold is lost only when a degraded node drives a gate.
• Static, ratioed, dynamic (Chapter 7, Section 4; Chapter 10, Section 9). Static: for every settled input, every node is connected to exactly one rail, and the right value is reached for any sizing. Ratioed: correct operation depends on the sizing (a node is connected to both rails, at least during a transition, and the stronger side wins). Dynamic: a node is connected to neither rail and holds its charge.
• Drivers. Data reaches a pass transistor from a real gate, usually an inverter, which the exam figures draw (Chapter 10, Section 8). Inputs and their complements ($A$A, $\bar A$Aˉ) are full-rail signals.
• Names. Internal node names on this page (P, Q, R, S, X, X̄ in MT24-3; the NFET names in MT23-2) are added; the exams’ own names (N9–N20, P3, P4, M_p,1, M_p,2, V_C, M1–M6) are kept.

How to approach a pass-transistor question

Recognize it by the picture: transistors whose source and drain carry signals (A, $\bar B$Bˉ, $C_{in}$Cin​) instead of the rails, inverters that make the complements, and sometimes a PFET from $V_{DD}$ whose gate sits on another node. The exams ask the same four things in the same words: “Is this a static CMOS circuit? Explain”, “What logic function does this circuit perform”, “the lowest logic high and largest logic low” (or “what function are transistors P3 and P4 performing”), and “Draw a complementary static CMOS circuit”. The family carries a quarter to a third of the exam: 45 of 200 points in 2024, 34 of 150 in 2023, and 30 + 25 of 150 in 2021.

The moves, in order.

1. Read it node by node. Each internal node is fed by two devices that never conduct together: two NFETs whose gates are complements, or an NFET and a PFET whose gates are tied. So each node is a two-way switch, “if the gate signal is 1, this input, else that one”. Write one line per node before answering anything; every part uses it.
2. Static, ratioed or dynamic? Settled states first: in every input state, is each node connected to exactly one rail (through a conducting path to a driver)? Then one transition: must a node that is changing overpower a device that is still on? If the answer depends on the sizes, the circuit is ratioed.
3. The function. Compose the switches into a Boolean expression and confirm it with a truth table. Then read which node feeds which labelled output.
4. The levels. Follow each 1 through NFETs and each 0 through PFETs, and apply the threshold rule (below) to every device on the path.
5. Restoring. A PFET from $V_{DD}$ whose gate is the complementary node is a half latch: say what it restores, and what it costs on a transition.
6. The static CMOS equivalent. One complementary gate computes an inverted function, so build the complement of the output as one gate and add an inverter.

Why these rules.

• Static, ratioed, dynamic (Chapter 7, Section 4). A static gate connects its output to exactly one rail for every settled input. Both rails at once is ratioed; neither is dynamic. The lecture’s test (Chapter 10, Section 9) adds the transitions: static CMOS reaches the right value for any sizing, however slowly; ratioed logic is correct only for some sizes. A half latch passes the settled-state check and fails the sizing test.
• The threshold rule (Chapter 10, Section 5). An NFET passing a 1 has its source on the rising side, so its $V_{GS}$ is (its gate voltage) − (the output). It cuts off when that falls to $V_{Tn}$VTn​: the output stops one $V_{Tn}$ below its own gate. It passes a 0 fully, because its source then stays at 0 V. A PFET is the mirror: a full 1, and a 0 only down to one $|V_{Tp}|$ above its gate. So the level depends on the gate voltage, not on how many devices are in series: two NFETs in series with full gates lose one threshold. A second threshold is lost only when a degraded node drives a gate.
• Duals (Chapter 7, Section 4). In a complementary gate the pull-up is the dual of the pull-down (series ↔ parallel), and the pull-down conducts when the output should be 0. So the gate computes the complement of whatever its pull-down network expresses.

Decisions to make on the way: which node feeds which labelled output (MT24-3 labels its inverters with the complements of the nodes that feed them); which input state gives the worst level (one where a degraded node is the gate of the device that passes the value); and whether “static” means the settled states or any sizing (write both).

Traps. Judging “static” from settled states alone. Counting one threshold per series device. Giving an input example that actually yields a full level (MT23-2c’s key). Reading an output node as the labelled output. “Only one select” when it must be exactly one.

1. MT24-3: a pass-transistor carry with half latches

MT24-3, p7 (source figure; the faint handwriting behind it shows through from the key’s next page).

MT24-3, p7 (Fall 2024, 45 points). Consider the pass transistor circuit shown above. (a) Is this a static CMOS circuit? Explain. (10 points) (b) What logic function does this circuit perform to each of the outputs $C_{out}$ and $\overline{C_{out}}$Cout​​? (15 points) (c) What function are transistors P3 and P4 performing? (10 points) (d) Draw a complementary static CMOS circuit implementation that has the same logic function as this pass-transistor circuit. (10 points)

Read the circuit once, node by node, before answering anything (Chapter 10, Section 4). Every internal node is fed by two NFETs whose gates are complements, so each node is a two-way switch: exactly one of its two inputs gets through.

Reading MT24-3 node by node

1. P, from N9 and N10. Their gates are A and $\bar A$Aˉ, so exactly one conducts. N9 passes B and N10 passes ground: for A = 1, P = B; for A = 0, P = 0. So $P = AB$AB.
2. Q, from N11 and N12. Again gates A and $\bar A$Aˉ. N11 passes $V_{DD}$ and N12 passes B: for A = 1, Q = 1; for A = 0, Q = B. So $Q = A + B$B.
3. X, from N13 and N14. Their gates are $\overline{C_{in}}$ and $C_{in}$Cin​, so this pair chooses between the two nodes just found: N13 passes P, N14 passes Q. $X = \overline{C_{in}}\,AB + C_{in}(A + B)$B). X drives the inverter labelled $\overline{C_{out}}$Cout​​.
4. R and S, the lower network. It is the same structure with every data input complemented, so expect complements: N15 (A) passes ground and N16 ($\bar A$Aˉ) passes $\bar B$Bˉ, so $R = \bar A\bar B = \overline{A + B}$A+B​; N17 (A) passes $\bar B$ and N18 ($\bar A$Aˉ) passes $V_{DD}$VDD​, so $S = \bar A + \bar B = \overline{AB}$AB.
5. X̄, from N19 and N20. N19 ($\overline{C_{in}}$Cin​​) passes S and N20 ($C_{in}$Cin​) passes R: $\overline{C_{in}}\,\overline{AB} + C_{in}\overline{(A + B)}$Cin​(A+B)​, the complement of X in every state. X̄ drives the inverter labelled $C_{out}$Cout​.
6. P3 and P4, the only PFETs. Each runs from $V_{DD}$ to one output node, with the other node on its gate: P3 to X with X̄ on its gate, P4 to X̄ with X on its gate. They are cross-coupled, so whichever node is low turns on the PFET that pulls the other one up.

MT24-3a: is it static?

MT24-3a, p7 (10 points). Is this a static CMOS circuit? Explain.

Hint

Every settled state looks fine. Pick an input change that makes X fall: what is P3 doing at that moment?

What it asks. Whether the circuit is static CMOS, with a reason. The word “static” decides the method: its definition has a half for the settled states and a half for the transitions.

The idea. Static means every node reaches exactly one rail in every settled state, and the right value is reached for any sizing (Chapter 10, Section 9). P3 and P4 are half latches (Chapter 10, Section 6): when a node they hold high must fall, its pull-down meets a PFET that is still on. The tempting answer is “yes, static: only ever one path”, which looks only at the settled states.

Static, or ratioed?

1. Settled states first. Without P3 and P4, every internal node is fed through exactly one conducting NFET (the two gates of each pair are complements), and every path ends at a rail or at an inverter that drives B or $\bar B$Bˉ. In every state each node is connected to exactly one rail: the pass networks alone are static, with weak highs.
2. Choose a transition that makes a held node fall. P3 holds X high, so take the inputs from A, B, $C_{in}$ = 1, 1, 0 (X = 1) to 0, 0, 0 (X = 0). Before: X = 1, held at $V_{DD}$ by P3, because its gate X̄ is 0.
3. Look at X just after the change. N10 and N13 now pull X toward ground, but P3 is still on, because its gate X̄ is still 0. X is connected to both rails at once: a fight.
4. Ask whether X̄ can free X by itself. N18 and N19 lift X̄, but through NFETs only, so to at most $V_{DD} - V_{Tn}$ (the threshold rule). P3 turns off only when its gate is within $|V_{Tp}|$ of $V_{DD}$VDD​. With equal thresholds, $V_{DD} - V_{Tn}$ leaves P3 exactly at its threshold ($V_{SG} = V_{Tn}$VSG​=VTn​); body effect (Chapter 5, Section 1) leaves the passed high a little lower still, so P3 stays partly on.
5. So the sizes decide the contest. X is pulled down against P3 until it falls past the inverter’s threshold and P4 takes X̄ to $V_{DD}$VDD​; where X sits meanwhile depends on the sizes. added Model every device as a resistor $R/W$ (Chapter 10’s switch model, a PFET counting $2R/W$2R/W). The pull-down is two 1 µm NFETs in series, $2R$2R; P3 of width $w$ is $2R/w$2R/w. X sits on the divider between them: $V_X = 5\,\mathrm{V} \cdot \dfrac{2R}{2R + 2R/w} = 5w/(w + 1)$ V. That is 1 V for $w = 0.25\,\mu\mathrm{m}$ (X switches), 2.5 V for $w = 1\,\mu\mathrm{m}$1μm, 4 V for $w = 4\,\mu\mathrm{m}$ (X still reads as 1).
6. Apply the lecture’s test. Correct operation depends on P3 and P4 being weak against the pass paths: by the lecture’s definition (Lecture 10, 50:43), that is ratioed logic.

Check. The divider’s limits behave as they must. As $w \to 0$0, $V_X \to 0$0: with no half latch there is no fight, and the pass network alone is static, as in step 1. As $w$ grows, $V_X \to 5$ V: a strong P3 always wins. The result swings with one width, so it is ratioed.

Answer: No. In every settled state each node has one path to one rail, but the cross-coupled half latches P3 and P4 make the circuit ratioed: on every transition the falling node must overpower a PFET that is still on, so the circuit works only if P3 and P4 are sized weak.

Remember. “Static?” is two checks: the settled states (one rail per node) and a transition (does anything fight?). A PFET held on by another node, a half latch, passes the first and fails the second. On the exam, write both.

The answer key differs

It says “Yes, this is static CMOS as there is only ever one path from the outputs to VDD/GND”. That is the settled-state view, and it ignores the transitions. The key’s own rubric gives “partial for understanding static criteria, full points for saying not static due to half latches”. Chapter 10 (Section 6) and Chapter 11 (Section 8) side with the rubric. The judgement rests on P3 being left at (or just above) its threshold in step 4.

MT24-3b: the function

MT24-3b, p7 (15 points). What logic function does this circuit perform to each of the outputs $C_{out}$ and $\overline{C_{out}}$Cout​​?

Hint

The reading already gives X as “if $C_{in}$ then one function, else another”. What are the two functions, and what single expression covers both?

What it asks. The Boolean function at each of the two labelled outputs. The words “to each of the outputs” decide the last step: after finding what each node computes, you still have to follow it through its inverter to the label.

The idea. A pass network is a tree of two-way switches, so its function is built by composing them: “if the gate is 1, this input, else that one” is $g\,x + \bar g\,y$ (Chapter 10, Section 4). The reading did that node by node. What is left is to simplify, recognize the function, and read the labels.

The function

1. Start from the reading. $X = \overline{C_{in}}\,AB + C_{in}(A + B)$B). For $C_{in} = 0$ that is $AB$AB; for $C_{in} = 1$ it is $A + B$B.
2. Find one expression for both cases. $AB + C_{in}(A + B)$ works: with $C_{in} = 0$ the second term vanishes, and with $C_{in} = 1$ it gives $A + B$B, which already contains $AB$AB.
3. Recognize it. $X = AB + AC_{in} + BC_{in}$ is 1 when at least two of the three inputs are 1. That is the majority function, the carry-out of a full adder.
4. Follow each node to its label, because the inverters sit between the nodes and the labels. X feeds the inverter labelled $\overline{C_{out}}$Cout​​, so that output is $\overline{X}$X, and X̄ feeds the inverter labelled $C_{out}$Cout​, so that output is X. Both labels are right.
5. Write the truth table, which the question’s 15 points expect (A B $C_{in}$ → $C_{out}$Cout​): 000 → 0, 001 → 0, 010 → 0, 011 → 1, 100 → 0, 101 → 1, 110 → 1, 111 → 1; $\overline{C_{out}}$ is the complement in every row.

Check. Trace one row straight through the switches, without the algebra. A, B, $C_{in}$ = 1, 0, 1: $C_{in} = 1$ selects Q through N14; A = 1 makes Q = $V_{DD}$ through N11. So X = 1 and $C_{out} = 1$1, matching row 101. The lower network gives R = 0 (N15 passes ground), so X̄ = 0: the two nodes are complements, as they must be.

Answer: $C_{out} = AB + C_{in}(A + B) = AB + AC_{in} + BC_{in}$BCin​, the carry (majority) of A, B and $C_{in}$Cin​; $\overline{C_{out}}$ is its complement.

Remember. Compose the switches into $g\,x + \bar g\,y$ terms, simplify, then follow each node through its inverter to its label. Here the upper network computes the carry itself, but its inverter is labelled $\overline{C_{out}}$Cout​​: reading the node as the output would invert your answer.

The answer key agrees

MT24-3c: what P3 and P4 do

MT24-3c, p8 (10 points). What function are transistors P3 and P4 performing?

Hint

Without P3 and P4, how high does a node get that is pulled up only through NFETs?

What it asks. The job of the two PFETs. “Function” here means their purpose in the circuit, not a Boolean function: what would be wrong without them, and how they fix it.

The idea. Every high in the pass networks arrives through NFETs, and an NFET passes a 1 only up to one $V_{Tn}$ below its gate (the threshold rule, Chapter 10, Section 5). A degraded high costs noise margin, and it leaves the next inverter’s PFET partly on. A half latch fixes it with feedback: a PFET from $V_{DD}$ whose gate is low exactly when its node should be high (Chapter 10, Section 6).

P3 and P4

1. Find the level without them. Highs reach X and X̄ only through NFETs (N11 and N18 pass $V_{DD}$VDD​; N9, N12, N16 and N17 pass B or $\bar B$Bˉ), and every one of those NFETs has a full-rail gate. So the high node stops at $V_{DD} - V_{Tn}$VTn​, one threshold (for A, B, $C_{in}$ = 1, 1, 0, X = $V_{DD} - V_{Tn}$VTn​).
2. Find the other node. Lows pass fully through NFETs, because the source stays at 0 V. So in every state the other node is a clean 0.
3. See what that clean 0 does. It sits on the gate of the PFET that feeds the high node (P3 for X, P4 for X̄). That PFET turns on and pulls the high node the rest of the way to $V_{DD}$VDD​.
4. Name it. This is the lecture’s half latch, with one difference: Lecture 10 wraps the PFET around an inverter on its own node, while here the complementary node already supplies the inverted signal, so the two PFETs are simply cross-coupled.
5. Say why it matters. The output inverters see a full $V_{DD}$VDD​, so their PFETs turn fully off and the high noise margin isn’t eaten (Chapter 10, Section 5).
6. Give the price. It is part (a): every transition starts with a fight against one of them, so they must be weak.

Check. Trace one row, A, B, $C_{in}$ = 1, 1, 0, with Chapter 10’s 5 V and 1 V. X: N13 passes P, and N9 passes B = 1 into P, so the pass network leaves X at $5 - 1 = 4$ V. X̄: N19 passes S, and N17 passes $\bar B = 0$ into S, so X̄ is a full 0 V. P3’s gate is X̄, so $V_{SG} = 5$ V and P3 is fully on: X goes to 5 V. P4’s gate is now X = 5 V, so P4 is fully off ($V_{SG} = 0$VSG​=0) and leaves X̄ at 0. The settled state is consistent and nothing fights: the fight of (a) happens only on a transition. The widget below (after MT23-2c) shows every row with and without the latches.

Answer: P3 and P4 are cross-coupled half latches. The pass networks give only $V_{DD} - V_{Tn}$ on the high node; the other node is a full 0, which turns on the PFET feeding the high node and restores it to $V_{DD}$VDD​. They must be weak, because the node that next falls has to overpower them.

Remember. A PFET from $V_{DD}$ whose gate is the complementary node is a half latch: it restores a high that NFETs degraded, and it makes the circuit ratioed. Expect the “static?” part and the “what do they do?” part to be two sides of the same device.

The answer key agrees

MT24-3d: a static CMOS equivalent

MT24-3d, p8 (10 points). Draw a complementary static CMOS circuit implementation that has the same logic function as this pass-transistor circuit.

Hint

A single complementary gate always inverts. Which of the two outputs is the complement of a simple expression?

What it asks. A complementary static CMOS circuit (a pull-up network of PFETs that is the dual of a pull-down network of NFETs) with the same two outputs as the pass-transistor circuit: $C_{out}$ and $\overline{C_{out}}$Cout​​.

The idea. The pull-down conducts when the output should be 0, so a single complementary gate computes the complement of its pull-down’s expression (Chapter 7, Section 4). So build $\overline{C_{out}}$ as one gate whose pull-down expresses $C_{out}$Cout​, draw the pull-up as its dual (series ↔ parallel), and add an inverter for $C_{out}$Cout​. Factoring the expression first saves transistors, as the lecture’s AOI gates do (Chapter 7, Section 5).

The static CMOS carry

1. Choose what the gate computes. $\overline{C_{out}} = \overline{AB + C_{in}(A + B)}$AB+Cin​(A+B)​, as one gate, then an inverter for $C_{out}$Cout​; the circuit then has both outputs, like the original.
2. Pull-down, from the expression. It must conduct when $C_{out} = 1$1. An AND is a series pair and an OR is a parallel pair, so: NFETs A and B in series, in parallel with (A ∥ B) in series with $C_{in}$Cin​. Five NFETs, stacks two high.
3. Pull-up, the dual. Swap every series for parallel and back: PFETs (A ∥ B) in series with (A–B in series, in parallel with $C_{in}$Cin​). Five PFETs; the A–B path is three high.
4. Count, because the factoring is what saves transistors. 10 transistors in the gate, 12 with the inverter. Writing the majority unfactored, $AB + AC_{in} + BC_{in}$BCin​, also works but needs 12 in the gate (14 in all).

MT24-3d: the gate's output is C̄out; an inverter after it gives Cout. Boxes are transistors (a bubble marks a PFET); the network is drawn from VDD (top) to ground (bottom).

Check. Two rows, one for each output value. A = B = 1: the pull-down’s A–B branch conducts and the pull-up’s (A ∥ B) is off, so $\overline{C_{out}} = 0$ and $C_{out} = 1$1. A = B = 0, $C_{in} = 1$1: no pull-down branch conducts (each needs A or B), while the pull-up’s (A ∥ B) is on and so is its A–B series pair, so $\overline{C_{out}} = 1$ and $C_{out} = 0$0. In both rows exactly one network conducts, as a static gate must.

Answer: the factored majority gate above, followed by an inverter.

Remember. For “draw a static CMOS equivalent”: build the complement of the output as one gate (pull-down = the expression, pull-up = its dual), then invert. Factor the expression first.

The answer key agrees

It draws the same circuit.

2. MT23-2: a pass-transistor full adder

MT23-2, p5 (source figure; the M_p,1, M_p,2 and V_C labels and the marks at A and B are handwritten on the key).

MT23-2, p5–6 (Fall 2023, 34 points). Consider the pass transistor circuit shown above. (a) Is this a static CMOS circuit? Explain. (8 points) (b) What logic function does this circuit perform to each of the outputs D and E? (16 points) (c) What is the lowest logic high and largest logic low values this circuit could produce at outputs D and E and under what static values for the input? (10 points)

This circuit is new in one way: its switches are an NFET and a PFET with their gates tied together, not two NFETs with complementary gates. For a full-rail gate signal, still exactly one of the pair conducts, so each node is again a two-way switch.

Reading MT23-2 node by node

1. The drivers first, because every pass path ends at one. Inverters make A and $\bar A$ (two in a row), B, and C and $\bar C$ (two in a row): all full-rail signals.
2. Node $V_C$VC​. Its pair shares the gate B: an NFET passes $\bar A$Aˉ, and M_p,1 (a PFET) passes A. A gate of 1 turns on the NFET, a gate of 0 the PFET: for B = 1, $V_C = \bar A$Aˉ; for B = 0, $V_C = A$A. So $V_C = A \oplus B$B.
3. Output D. Its pair shares the gate $V_C$VC​: an NFET passes C, and M_p,2 (a PFET) passes B. For $V_C = 1$1, D = C; for $V_C = 0$0, D = B.
4. Output E. Its pair also shares the gate $V_C$VC​: an NFET passes $\bar C$Cˉ, and a PFET passes C. For $V_C = 1$1, E = $\bar C$Cˉ; for $V_C = 0$0, E = C.
5. Note what drives the gates. $V_C$ is itself a pass-transistor output, and it steers four gates. A degraded $V_C$ would weaken every device it drives. That is what part (c) is about.

MT23-2a: is it static?

MT23-2a, p5 (8 points). Is this a static CMOS circuit? Explain.

Hint

Is there any device here that holds a node against the path that should switch it?

What it asks. The same question as MT24-3a, about a circuit without half latches. As there, “static” needs both checks: one rail per node in every settled state, and the right value for any sizing.

The idea. Same test as MT24-3a; what differs is that nothing here can fight. A fight needs two conducting paths to different rails on one node, and that needs either a half latch (a device held on by another node) or two switches of one pair on at once. With full-rail gates, neither happens. The one thing to check is the one input that is not full-rail: $V_C$ on the gates of the output pairs.

Static?

1. One path per node. $V_C$VC​, D and E are each fed by an NFET and a PFET with the same gate signal. For a gate at a full 0 or 1, exactly one of the two conducts.
2. Each path ends at one rail. Every conducting path leads back to an inverter output, which is connected to one rail.
3. Nothing fights. There is no half latch and no feedback, so no device has to overpower another. The sizes change the speed, never the logic value: Chapter 10’s test for static.
4. Check the one gate signal that isn’t full-rail. $V_C$ is degraded in two states ($V_{DD} - V_{Tn}$VDD​− or $|V_{Tp}|$∣VTp​∣, part c) and drives the D and E pairs. With $V_C = V_{DD} - V_{Tn}$ on its gate, M_p,2 has $V_{SG} = V_{Tn}$VTn​: with equal thresholds that is exactly its threshold, so it is still off. In the threshold model every node keeps exactly one path in every state (the widget below flags these devices “at the edge”).

Check. Compare with MT24-3a, where the answer was “ratioed”: there P3 stays on because another node holds its gate low while its own node must fall. Here every gate is an input or $V_C$VC​, and none of them depends on the node it steers, so no node can hold itself.

Answer: Yes, static. In every input state each of $V_C$VC​, D and E is connected to exactly one rail, through a complementary pair with a common gate, and nothing depends on sizing. It is not complementary static CMOS, and some levels are degraded, but it is neither ratioed nor dynamic.

added If you have time, add the caveat of step 4: the degraded $V_C$ leaves the “off” device of the next pair right at its threshold, so in a real circuit (body effect, or $|V_{Tp}| < V_{Tn}$VTn​) it would conduct slightly.

Remember. Static fails through a fight (a half latch, two drivers on a node) or a float (no path). With no feedback and full-rail gates, a pass circuit is static, even when its levels are degraded.

The answer key agrees

MT23-2b: the functions

MT23-2b, p5 (16 points). What logic function does this circuit perform to each of the outputs D and E?

Hint

$V_C$ tells you whether A and B differ. When they are equal, what is B?

What it asks. The Boolean functions at D and E, in terms of A, B and C. The 16 points go to an expression and a truth table for each.

The idea. Same method as MT24-3b: compose the two-way switches of the reading, then simplify. The new step is a substitution: when $V_C = 0$0, D passes B, and $V_C = 0$ means A = B, so B can be read as A or as B, whichever makes the expression recognizable.

D and E

1. The steering signal. $V_C = A \oplus B$ (reading, step 2): it is 1 exactly when A and B differ.
2. D, case by case. If A ≠ B ($V_C = 1$VC​=1), D = C. If A = B ($V_C = 0$VC​=0), D = B, and since A = B there, that is also $AB$AB. So $D = (A \oplus B)\,C + AB$AB.
3. Recognize D. Expand: $(A \oplus B)C + AB = A\bar BC + \bar ABC + AB = AB + AC + BC$BC. D is 1 when at least two inputs are 1: the majority, a full adder’s carry.
4. E, case by case. $V_C = 1$ gives $\bar C$ and $V_C = 0$ gives C, which is “C inverted when $V_C$ is 1”: $E = V_C \oplus C = A \oplus B \oplus C$C, a full adder’s sum.
5. Write the truth table, which the question’s 16 points expect for each output (A B C → D E): 000 → 0 0, 001 → 0 1, 010 → 0 1, 011 → 1 0, 100 → 0 1, 101 → 1 0, 110 → 1 0, 111 → 1 1.

Check. A full adder adds three bits, so D and E together must count the ones in each row as the binary number DE. Row 011: two ones, DE = 10 ✓. Row 111: three ones, DE = 11 ✓. Row 100: one, DE = 01 ✓.

Answer: $D = AB + AC + BC$ (the carry) and $E = A \oplus B \oplus C$ (the sum): the circuit is a full adder.

Remember. A switch steered by $A \oplus B$ is the sign of an adder: the carry passes C when A and B differ and A (= B) when they agree; the sum is C, inverted when A and B differ.

The answer key agrees

It writes $D = A(B + C) + BC$BC, the same function.

MT23-2c: the worst levels

MT23-2c, p6 (10 points). What is the lowest logic high and largest logic low values this circuit could produce at outputs D and E and under what static values for the input?

Hint

A high is worst when it passes through an NFET whose own gate is already degraded. In which input states is $V_C$ degraded?

What it asks. The lowest voltage that D or E can have while it is a logic 1, the highest while it is a logic 0, and the input states that produce them. “Under what static values for the input” means you must name a row that really gives the level.

The idea. Apply the threshold rule (Chapter 10, Section 5) along each path. An NFET passes a 1 only up to one $V_{Tn}$ below its own gate, and a PFET passes a 0 only down to one $|V_{Tp}|$ above its gate. So a level loses one threshold when a 1 goes through an NFET (or a 0 through a PFET) with a full-rail gate, and a second one only when that device’s gate is itself degraded. The tempting slip is to count devices in series: a 1 that crosses two NFETs with full gates loses one threshold, not two. Here the degraded gate is $V_C$VC​, so first find when $V_C$ is degraded, then which output passes a 1 (or a 0) through a device that $V_C$ steers.

Worst high and worst low

1. When is $V_C$ degraded? A = 0, B = 1: the NFET (gate B) passes $\bar A = 1$1, so $V_C = V_{DD} - V_{Tn}$VTn​. A = 0, B = 0: M_p,1 passes A = 0, so $V_C = |V_{Tp}|$∣VTp​∣. In the other two states $V_C$ is a full rail, because each device then passes the value it passes well (the NFET a 0, the PFET a 1).
2. Lowest high. We need a 1 that passes through an NFET whose gate is $V_C = V_{DD} - V_{Tn}$VTn​: it stops one $V_{Tn}$ below that gate, at $V_{DD} - 2V_{Tn}$2VTn​. $V_C$ is high, so the NFETs conduct: D = C, E = $\bar C$Cˉ. At D this gives a 1 for A, B, C = 0, 1, 1; at E for 0, 1, 0. The figure below marks the path for D.
3. Highest low. The mirror: a 0 that passes through a PFET whose gate is $V_C = |V_{Tp}|$ stops one $|V_{Tp}|$ above that gate, at $2|V_{Tp}|$2∣VTp​∣. $V_C$ is low, so the PFETs conduct: D = B, E = C. D is 0 for A = B = 0 with C either (through M_p,2); E for 0, 0, 0 (through E’s PFET).
4. Single drops elsewhere, for comparison. A, B = 1, 0 makes $V_C = V_{DD}$VDD​, so D (for C = 1) and E (for C = 0) reach $V_{DD} - V_{Tn}$ through their NFETs; A, B = 1, 1 makes $V_C = 0$0, so E (for C = 0) only falls to $|V_{Tp}|$∣VTp​∣.
5. Put in numbers. With Chapter 10’s $V_{DD} = 5\,\mathrm{V}$ and $V_T = 1\,\mathrm{V}$1V: the worst high is 3 V and the worst low is 2 V. The two outputs can be only 1 V apart.

MT23-2c at A, B, C = 0, 1, 1: the two threshold drops on the way to D (marked up by the study guide; the original is above).

Check. Every worst row has A = 0, and that is no accident. $V_C$VC​’s NFET passes $\bar A$Aˉ, which is a 1 (the value an NFET degrades) only when A = 0; its PFET passes A, which is a 0 (the value a PFET degrades) also only when A = 0. With A = 1, $V_C$ is a full rail and no output can lose more than one threshold. The widget below shows every row.

Answer: Lowest high $V_{DD} - 2V_{Tn}$2VTn​: at D for A, B, C = 0, 1, 1 and at E for 0, 1, 0. Highest low $2|V_{Tp}|$2∣VTp​∣: at D for 0, 0, 0 and 0, 0, 1, and at E for 0, 0, 0. Both come from the degraded $V_C$ driving the gate of the next pass device (Chapter 10, Section 5, its last check).

Remember. One threshold per path, plus one more where a degraded node drives a gate. To find the worst row, first find when the steering node is degraded, then pick the output value that passes through the device it steers.

The answer key differs

It gives the lowest high for “A = 1, B = 1, C = 1”. It doesn’t occur there: $\bar A = 0$ passes through the NFET as a strong 0, so $V_C = 0$0, M_p,2 is on and passes B = 1 to D at the full $V_{DD}$VDD​. The worst high needs A = 0, B = 1, so that $V_C$ is the degraded $V_{DD} - V_{Tn}$VTn​. The key’s levels themselves, and its low example (A = B = 0), are right.

Run both adders here. Every node shows its logic value and its level; the table runs all eight rows.

MT23-2 (sum and carry)MT24-3 with P3, P4MT24-3 without P3, P4

A = 0B = 1C = 1

V_C

1: V_DD − V_Tn (4 V)

D

1: V_DD − 2V_Tn (3 V)

E

0: 0 (0 V)

output D

1

output E

0

At the edge of conduction (|V_GS| = |V_T| exactly, so just off): Mp,2, Mp,3. Numbers at V_DD = 5 V, V_Tn = |V_Tp| = 1 V.

A	B	C	VC	D	E	D	E
0	0	0	|VTp|	2|VTp|	2|VTp|	0	0
0	0	1	|VTp|	2|VTp|	VDD	0	1
0	1	0	VDD − VTn	0	VDD − 2VTn	0	1
0	1	1	VDD − VTn	VDD − 2VTn	0	1	0
1	0	0	VDD	0	VDD − VTn	0	1
1	0	1	VDD	VDD − VTn	0	1	0
1	1	0	0	VDD	|VTp|	1	0
1	1	1	0	VDD	VDD	1	1

Orange: a degraded level, one or two thresholds short of the rail. A pass device stops one threshold short of its own gate, so two NFETs in series with their gates at V_DD lose one V_Tn, but a node at V_DD − V_Tn that drives a gate costs a second one. Settled levels only: transitions, and any fight they start, are in the text.

What to notice.

• MT23-2, A, B, C = 0, 1, 1: $V_C$ is $V_{DD} - V_{Tn}$ and D is $V_{DD} - 2V_{Tn}$2VTn​; M_p,2 and the PFET of E are flagged at the edge of conduction. Now set A = 1: $V_C$ becomes a full 0 and D a full $V_{DD}$ (the key’s example).
• MT24-3 without P3 and P4: every high node is $V_{DD} - V_{Tn}$VTn​, never worse, because every NFET’s gate is a full-rail input. With them, every high node is restored to $V_{DD}$VDD​.
• The widget shows settled states only. The fight that makes MT24-3 ratioed happens during a transition (MT24-3a); the switch-level widget of Chapter 10, Section 4 replays transitions for the lecture’s circuits.

Check yourself MT24-3's pass networks lose at most one threshold, while MT23-2's lose two. What is the structural difference?

In MT24-3 every pass NFET’s gate is a full-rail input ($A$A, $\bar A$Aˉ, $C_{in}$Cin​, $\overline{C_{in}}$Cin​​), and series NFETs with full gates lose only one $V_{Tn}$ in total. In MT23-2 the gates of the output pairs are driven by $V_C$VC​, which is itself a pass-transistor output and can be degraded; a device whose gate is one threshold short stops one threshold below that, two in all.

3. MT21-1: a pass-transistor multiplexer

MT21-1, p2 (source figure).

MT21-1, p2–3 (Fall 2021, 30 points). Consider the pass transistor multiplexer shown above. (a) What logic constraint on S1, S2, S3, and S4 ensures that this is a static CMOS circuit? (10 points) (b) In normal operation, what output high voltage will be achieved relative to the supply voltage $V_{DD}$VDD​? Explain. (10 points) (c) Draw a complementary static CMOS circuit that achieves the same logic functionality of the pass transistor design. (10 points)

MT21-1a: the constraint on the selects

Hint

Count Y’s paths to a rail for no select on, one on, and two on.

What it asks. A rule on the four selects under which the multiplexer is static. Here the circuit is static or not depending on the inputs, so the answer is a condition, not a yes or no.

The idea. Static means exactly one path from Y to one rail (Chapter 7, Section 4). Unlike MT24-3 and MT23-2, these selects are four independent signals, not complements, so the circuit itself no longer guarantees one path: the selects must. Count Y’s paths for each number of selects that are on (Chapter 10, Section 7).

When is the multiplexer static?

1. List the paths. Y has four possible paths, one per NFET, each to an inverter output and through it to one rail.
2. No select on. Y is connected to nothing and floats. That is dynamic, not static.
3. Two selects on, with different data. One inverter pulls Y up while another pulls it down, a fight decided by strength: ratioed.
4. Exactly one select on. Exactly one path, to exactly one rail. Static.

Check. The condition must exclude both failures, and “exactly one” does: “at most one” still allows the float, and “at least one” still allows the fight. A decoder’s outputs satisfy it by construction, which is why the lecture drives the selects from one.

Answer: exactly one of S1–S4 must be 1 at any time (the selects are one-hot, for example from a decoder).

Remember. When the gate signals are independent, being static is a condition on the inputs: no fight (at most one path) and no float (at least one). For a multiplexer, that is one-hot selects.

The answer key differs

It says “only one of the inputs can be logic 1 at any given time”, which reads as at most one. All four at 0 is also not static (Y floats), so say exactly one.

MT21-1b: the output high

Hint

When the NFET passes a 1, which of its terminals is the source, and what happens to $V_{GS}$ as Y rises?

What it asks. The voltage Y reaches when the multiplexer outputs a 1, relative to $V_{DD}$VDD​, with the reason. “In normal operation” means one-hot selects: a single NFET with its gate at $V_{DD}$ connects Y to one inverter.

The idea. This is the threshold rule itself, the single-drop case of MT23-2c (Chapter 10, Section 5). An NFET’s source is whichever of its two terminals is lower. Passing a 1, that is the output, so the output’s own rise eats into $V_{GS}$ until the device cuts off. The gate is a full-rail select, so there is no second drop.

The high level

1. Set up a 1 on the path. Say S3 = 1 and D3 = 0: the third inverter’s output is $V_{DD}$VDD​, and the third NFET has its gate at $V_{DD}$VDD​.
2. Find the source. Passing a 1, the NFET’s lower terminal is Y, so Y is its source and $V_{GS} = V_{DD} - V_Y$VY​.
3. Follow Y up. As Y charges, $V_{GS}$ shrinks; the NFET cuts off when $V_{GS} = V_{Tn}$VTn​, at $V_Y = V_{DD} - V_{Tn}$VTn​.
4. Add what the model leaves out. Body effect raises $V_{Tn}$ as the source rises, so a real NFET stops a little lower still.
5. Put in numbers, for example. The exam gives no values, so the answer stays symbolic. With illustrative values, $V_{DD} = 2.5\,\mathrm{V}$ and $V_{Tn} = 0.5\,\mathrm{V}$ (Chapter 10’s exam-style check; not the exam’s numbers, and not this page’s 5 V / 1 V), it is 2.0 V.

Check. The low side, by the same reasoning: passing a 0, the source is the inverter’s side, at 0 V, so $V_{GS}$ stays at $V_{DD}$ the whole way and Y reaches ground. An NFET-only multiplexer is asymmetric, a full 0 and a weak 1, which is what the rule predicts.

Answer: $V_{OH} = V_{DD} - V_{Tn}$VTn​, because the pass NFET turns itself off once its gate is only $V_{Tn}$ above the output.

Remember. An NFET passing a 1 stops one $V_{Tn}$ below its gate, because the output is its source. One drop, however many NFETs with full gates are in series.

The answer key agrees

Its answer is the same, but it writes $V_{GS} = V_{DD} - V_{tn}$ (“high $R_{DS}$RDS​”). At cut-off it is $V_{GS} = V_{Tn}$VTn​; it is the output that sits at $V_{DD} - V_{Tn}$VTn​.

MT21-1c: a static CMOS equivalent

Hint

The inverters already invert each data input. Can you write Y as the complement of an AND-OR expression of $S_i$ and $D_i$Di​?

What it asks. A complementary static CMOS circuit with the same function as the multiplexer, inverters included. Only the function has to match, not the structure.

The idea. Same move as MT24-3d: a single complementary gate computes the complement of its pull-down’s expression (Chapter 7, Section 4). What is new is that the multiplexer already inverts (it passes $\bar D_i$Dˉi​), so with one-hot selects Y is itself the complement of an AND-OR expression, and one AND-OR-invert gate does it with no inverter at all (Chapter 7, Section 5).

An AND-OR-invert gate

1. Write the function. With the inverters, the multiplexer passes $\bar D$Dˉ: $Y = S_1\bar D_1 + S_2\bar D_2 + S_3\bar D_3 + S_4\bar D_4$S4​Dˉ4​, assuming one-hot selects.
2. Rewrite it as a complement, because that is what one gate computes. With one-hot selects, if $S_k$ is the select that is on, $Y = \bar D_k = \overline{S_1D_1 + S_2D_2 + S_3D_3 + S_4D_4}$S1​D1​+S2​D2​+S3​D3​+S4​D4​​: only the $k$-th term can be 1.
3. Draw the gate. That is an AND-OR-invert gate: the pull-down has four series pairs ($S_i$Si​, $D_i$Di​) in parallel; the pull-up, its dual, has four parallel pairs ($S_i$Si​ ∥ $D_i$Di​) in series. 16 transistors, and no inverters: $D_i$ goes straight in.
4. Note its cost. Its PFET stack is four high, which Chapter 7 would avoid in practice. The question asks only for a circuit with the same function.
5. Compare the key’s form. It uses the complements $\bar S_i$ instead: pull-down $(D_1 \parallel \bar S_1)$ in series with the other three such pairs, pull-up four series branches ($\bar S_i$Sˉi​, $D_i$Di​) in parallel. It computes $\sum S_i\bar D_i$ exactly, for any selects, but needs four inverters for $\bar S_i$Sˉi​, and its NFET stack is four high.

MT21-1c with one-hot selects: Y = NOT(S1·D1 + S2·D2 + S3·D3 + S4·D4).

Check. One row each way. S3 = 1, D3 = 0: in the pull-down the S3–D3 pair is off, and every other pair has its select off, so the pull-down is off; in the pull-up, pairs 1, 2 and 4 conduct through their select PFETs (selects at 0) and pair 3 through its $D_3$ PFET, so Y = 1 = $\bar D_3$ ✓. With D3 = 1 the S3–D3 pair conducts and Y = 0 ✓.

Answer: the AOI gate above (or the key’s equivalent form with $\bar S_i$Sˉi​).

Remember. A pass-transistor multiplexer with one-hot selects is an AND-OR(-invert) of selects and data. Write the function as a complement first, then draw one gate.

The answer key agrees

It writes $Y = S_1\bar D_1 + S_2\bar D_2 + S_2\bar D_3 + S_4\bar D_4$S4​Dˉ4​: the third term should be $S_3\bar D_3$S3​Dˉ3​. Its circuit is otherwise correct.

4. MT21-3: the six-transistor XOR

MT21-3, p5 (source figure; the blue arrow is the key’s handwritten path).

MT21-3, p5 (Fall 2021, 25 points). Consider the six-transistor XOR gate shown above. As discussed in class, this is not a static CMOS circuit. Describe how one could size the circuit such that it produces a logically incorrect result.

Hint

Every row of the truth table is right, so look at a transition. When B rises with A = 1, which node must fall, and what still holds it up?

What it asks. A sizing that makes the gate give a wrong answer. The question already tells you the gate is not static, so the job is to find the transition where two paths fight, and say which device must lose for the wrong side to win.

The idea. Why the 6T XOR is ratioed (Chapter 10, Section 9): a settled-state check passes, because each row of the truth table has one path from Y to one rail. But on one transition a node is pulled both ways, and that node, $\bar B$Bˉ, is also the gate of a pass device (M5). So whichever side wins the fight decides whether M5 turns off, and with it the final state. A fight whose winner decides the answer is what makes a gate ratioed; a brief overlap that always ends the same way does not. Include the gates that drive A and B, as the lecture does (Lecture 10, 46:05): the fight runs through A’s driver.

The failing transition

1. Name the devices. M1 and M2 make $\bar B$ from B; M3 (PFET, gate A) joins B to Y; M4 (NFET, gate A) joins $\bar B$ to Y; M5 (NFET, gate $\bar B$Bˉ) and M6 (PFET, gate B) join A to Y. Every row of the truth table gives XOR.
2. Add the drivers, because the fight’s path runs through one: every node is driven by a real gate.
3. Start at A = 1, B = 0. $\bar B = 1$1, so M5 and M6 pass A = 1 to Y; M4 (gate A = 1) also joins Y to $\bar B$Bˉ, which is 1 too. Y = 1, and nothing fights.
4. Switch B to 1, and say what should happen. Y should fall: M2 pulls $\bar B$ down, M5 turns off, and M4 pulls Y down to $\bar B = 0$0.
5. Find the path that resists. While $\bar B$ is still high there is a path from $V_{DD}$ through the PFET of A’s driver, M5 (gate $\bar B$Bˉ, still on), Y and M4 (gate A = 1) to $\bar B$Bˉ. It holds $\bar B$ up against M2.
6. Choose the sizes that let it win. Size M2 very weak, and M5, M4 and A’s driver strong. Then $\bar B$ never falls far enough, M5 stays on, and Y stays at 1 for A = B = 1: the wrong answer, with current flowing from $V_{DD}$ to ground.
7. Put numbers on it added. With every device as $R/W$ (A’s driver PFET 2 µm, M5 and M4 1 µm, so the path is $3R$ per µm), $\bar B$ sits on a divider between that path and M2’s $R/W_2$R/W2​: $V_{\bar B} = 5\,\mathrm{V}/(1 + 3W_2)$ for an M2 of width $W_2$ in µm. $W_2 = 1\,\mu\mathrm{m}$ gives 1.25 V (it switches); $W_2 = 0.2\,\mu\mathrm{m}$ gives 3.125 V, with Y at 3.75 V (it fails). The switch-over is at $W_2 = 1/3\,\mu\mathrm{m}$1/3μm.

Check. At the switch-over, $W_2 = 1/3\,\mu\mathrm{m}$1/3μm, M2’s resistance is $R/W_2 = 3R$3R, equal to the path’s $3R$3R, and $V_{\bar B} = 5/(1 + 1) = 2.5\,\mathrm{V}$2.5V, half the supply. A ratioed contest should flip exactly where the two sides are equally strong, and it does.

Answer: make M2, the NFET of the inverter that produces $\bar B$Bˉ, much weaker than the series path through A’s driver, M5 and M4. Then on the transition A = 1, B: 0 → 1, $\bar B$ can’t be pulled low, M5 stays on and Y stays at 1. Because correct operation depends on sizing, the gate is ratioed.

Remember. To show a gate is ratioed, give a transition, the two paths that fight on one node, and the device whose weakness lets the wrong side win. The truth table alone can never show it.

The answer key agrees

It names the M5–M4 path; the PFET of A’s driver belongs to that path too.

Check yourself Does the 6T XOR fail on any other transition? Consider A = 0, B: 0 → 1.

It fights only briefly. When B rises, $\bar B$ falls on its own (M2 pulls it down and nothing holds it up, since M4 is off with A = 0). M5 turns off, M3 connects Y to B = 1, and the gate settles correctly whatever the sizes. A transient overlap is not what makes a gate ratioed; a fight whose winner decides the final state is. Only 10 → 11 has one (Chapter 10, Section 9).

How to approach a stick-layout question

Recognize it by the picture: two rails ($V_{DD}$VDD​ at the top, ground at the bottom), two horizontal diffusion lines (p near $V_{DD}$VDD​, n near ground), vertical poly lines labelled with the inputs, metal lines, and square contacts. The question always says “Draw the schematic corresponding to this layout. What logic function does this gate perform?” It is short: 15 of 200 points in 2024 and 10 of 150 in 2023, about five minutes, with most of the points for the schematic.

The moves, in order.

1. Find the transistors. Every place a poly line crosses a diffusion line is one transistor, with that poly’s signal on its gate: a PFET on the p line, an NFET on the n line.
2. Name the nodes. The pieces of diffusion between polys are the transistors’ sources and drains. A contact joins a piece to the metal over it; follow that metal to name the net ($V_{DD}$VDD​, ground, the output, or an internal net). A poly with no input label gets its signal through a contact from metal, so it is driven by an internal net.
3. Series or parallel. An uncontacted piece joins only its two neighbours, so they are in series. Two transistors whose ends reach the same two nets are in parallel, wherever they sit on the line.
4. Find the stages. A net that ends on a poly is a gate’s output driving another gate: the layout has two stages.
5. Then the function. Write each stage’s pull-down, check that its pull-up is the dual, and compose the stages.

Why these rules (Chapter 9, Section 10). A stick diagram draws one line per layer, so a transistor is exactly where gate poly crosses active diffusion, and only a contact joins two layers: metal that merely crosses a poly or a diffusion line touches nothing. Neighbouring transistors on one line share the diffusion between them (Chapter 5, Section 6): uncontacted, that shared piece is an internal node of a series stack; contacted, it is a net that other devices may also reach. The duality check comes from complementary static CMOS (Chapter 7, Section 4): if your pull-up is not the dual of your pull-down, you have misread a contact.

Traps. Metal crossing a poly or a diffusion line without a contact (both exam figures have one). A poly with no input label, which means a second stage (without MT24-4’s inverter you would answer NOR, not OR). Calling two transistors in series because they sit side by side, when their outer ends reach the same nets.

5. MT24-4: a stick layout with two stages

MT24-4, p9 (source figure: yellow p diffusion, green n diffusion, red poly, blue metal, black contacts).

MT24-4, p9 (Fall 2024, 15 points). Consider the stick layout above with a row of pFET devices and a row of nFET devices. Draw the schematic corresponding to this layout? What logic function does this gate perform? (Schematic 10 points, output 5 points.)

Hint

The fourth poly has no input label. Where does its signal come from?

What it asks. The schematic of the eight transistors (10 points) and the logic function at “Output” (5 points). The unlabelled fourth poly is the detail that decides the function.

The idea. Read it with the rules of the section above (Chapter 9, Section 10): transistors where poly crosses diffusion, nets named by following contacts and metal, series through uncontacted pieces, parallel where two devices reach the same two nets. The new idea here is a second stage: one metal net both collects the first gate’s output and ends in a contact on the fourth poly, so the first gate drives the second.

MT24-4: the net X and where it does and doesn’t connect (marked up by the study guide; the original is above).

Reading the layout (Chapter 9's rules)

1. Count the transistors. Four poly lines cross both diffusion lines: eight transistors. A, B and C enter from the bottom; the fourth poly has no input label and gets its signal through the contact on it.
2. Name the metal, because the nets decide every connection. The left vertical line joins the left ends of both rows and runs along the horizontal line to the contact on the fourth poly: call it X. The right vertical line joins the right ends of both rows: the output. The horizontal line crosses polys A, B and C with no contact, so it does not touch them.
3. PFET row, left to right: X, poly A, an uncontacted piece, poly B, an uncontacted piece, poly C, a contact to $V_{DD}$VDD​, the fourth poly, the output. The uncontacted pieces join only their neighbours, so A, B and C are in series from $V_{DD}$ to X (C nearest $V_{DD}$VDD​), and the fourth PFET runs from $V_{DD}$ to the output.
4. NFET row: X, poly A, ground, poly B, X (the contact wired up to the horizontal line), poly C, ground, the fourth poly, the output. A runs from X to ground, B from ground to X, C from X to ground: every one reaches the same two nets, so all three are in parallel between X and ground (Chapter 5, Section 6). The fourth NFET runs from ground to the output.
5. Find the stages. First stage: series PFETs over parallel NFETs, $X = \overline{A + B + C}$A+B+C​, a three-input NOR. Second stage: one PFET and one NFET, both gated by X, between the rails and the output: an inverter.
6. Compose them. $\mathrm{OUT} = \overline{X} = A + B + C$C.

MT24-4, first stage: X = NOT(A + B + C), with the PFETs in the layout's order (C nearest VDD).

MT24-4, second stage: an inverter, OUT = NOT X.

Check. Duality: the first stage’s pull-up (A, B, C in series) is the dual of its pull-down (A, B, C in parallel), as a complementary gate’s must be. And every transistor is used once: six in the NOR, two in the inverter, eight in all, matching the eight crossings.

Answer: a three-input NOR whose output X drives an inverter: $\mathrm{OUT} = A + B + C$C, an OR gate.

Remember. A poly with no input label is driven by an internal net, so look for a second stage before you write the function. Chapter 9’s exam-style practice is the two-input version of this layout.

The answer key agrees

6. MT23-4: a stick layout with four inputs

MT23-4, p10 (source figure).

MT23-4, p10 (Fall 2023, 10 points). Consider the stick layout above with a row of pFET devices and a row of nFET devices. Draw the schematic corresponding to this layout? What logic function does this gate perform?

Hint

Name the net of every contacted piece on the n line first. How many different nets are there?

What it asks. The schematic and the logic function of a single gate with four inputs. Every poly is labelled, so there is one stage; the work is in the nets.

The idea. Same rules as MT24-4. What is different: one stage, and an internal net (P) that is contacted and joined by metal, so devices that are not neighbours on the line still meet at it. That is how a parallel group and a series device share one row.

Reading the layout

1. Count the transistors. Four polys, A to D, each cross both rows: eight transistors.
2. PFET row: $V_{DD}$VDD​, A, an uncontacted piece, B, an uncontacted piece, C, a contact wired to Y, D, $V_{DD}$VDD​. The uncontacted pieces make A, B and C in series from $V_{DD}$ to Y; D runs from Y to $V_{DD}$VDD​, the same two nets, so it is in parallel with that stack.
3. NFET row: ground, A, a contact (call its net P), B, ground, C, a contact wired to the first one by the metal line (P again), D, Y. A runs from ground to P, B from P to ground, C from ground to P: all reach the same two nets, so they are in parallel between ground and P. D runs from P to Y.
4. Write both networks. Pull-down: D in series with (A ∥ B ∥ C); it conducts when $D(A + B + C)$C). Pull-up: (A–B–C in series) ∥ D, which is its dual, as it must be.
5. The function. The output is low when the pull-down conducts: $Y = \overline{D\,(A + B + C)} = \bar D + \bar A\bar B\bar C$AˉBˉCˉ, an OR-AND-invert gate.

MT23-4: Y = NOT(D·(A + B + C)).

Two traps in this figure. The Y metal crosses poly D on its way down, and the P metal crosses polys B and C; neither has a contact there, so neither connects.

Check. One row through the transistors themselves. A = B = C = 0, D = 1: on the n line the D NFET is on but A, B and C are all off, so P has no path to ground and the pull-down is off; on the p line A, B and C are all on, so the series stack pulls Y to $V_{DD}$VDD​. Y = 1, and the formula gives $\overline{1 \cdot 0} = 1$ ✓.

Answer: $Y = \overline{D\,(A + B + C)} = \bar D + \bar A\,\bar B\,\bar C$AˉBˉCˉ.

Remember. Name every contacted piece by its net before deciding series or parallel: devices far apart on a line are in parallel if they reach the same two nets.

The answer key agrees

Check yourself Is the order A, B, C, D in MT23-4 an Euler path of both networks? How can you tell from the layout alone?

Yes. Both diffusion rows run unbroken from end to end, with every pair of neighbouring transistors sharing a piece of diffusion. That is exactly what an Euler path common to both networks buys (Chapter 10, Section 1): straight polys and no breaks in either row.

Patterns

Pass-transistor circuits (every midterm since 2021: 23–37% of the points).

• Moves (the approach): read node by node; static (settled states, then a transition); the function; the levels by the threshold rule; what the half latch restores; one complementary gate plus an inverter.
• The answers that keep coming back: one-hot selects; $V_{DD} - V_{Tn}$VTn​; $V_{DD} - 2V_{Tn}$ and $2|V_{Tp}|$ when a pass output drives a gate; half latches restore the rail but make the circuit ratioed; the carry $AB + C(A + B)$ and the sum $A \oplus B \oplus C$C.
• Traps: “static” from settled states only; one threshold per series device; a worst-level example that gives a full level; an output label that is the complement of its node; “only one select” for exactly one.
• Time: 15–17 minutes for the whole question (about 30 seconds a point on a 150-point exam, 22.5 on a 200-point one).

Stick layout to schematic (MT23-4, MT24-4: 7–8% of the points).

• Moves (the approach): a transistor at every poly–diffusion crossing; name the nets by contacts and metal; series through uncontacted pieces, parallel to the same two nets; find the stages; then the function, with the duality check.
• Traps: metal crossing without a contact; an unlabelled poly, which means a second stage (NOR, not OR, if you miss MT24-4’s inverter).
• Time: about 5 minutes.

What the keys get wrong

Re-solving every part found these disagreements; all are recorded in this page’s review/decisions.md.

Part	The key	Here
MT24-3a	“Yes, this is static CMOS”	Not static: ratioed because of the half latches (the key’s own rubric gives full points for this)
MT23-2c	lowest high $V_{DD} - 2V_{Tn}$ “Ex: A = 1, B = 1, C = 1”	at 1, 1, 1 D is a full $V_{DD}$VDD​; the lowest high is at 0, 1, 1 (D) and 0, 1, 0 (E)
MT21-1a	“Only one of the inputs can be logic 1”	exactly one: with none on, Y floats
MT21-1b	$V_{GS} = V_{DD} - V_{tn}$	at cut-off $V_{GS} = V_{Tn}$VTn​; the output is $V_{DD} - V_{Tn}$ (the key’s answer is right)
MT21-1c	third term $S_2\bar D_3$	$S_3\bar D_3$S3​Dˉ3​; the circuit is otherwise right

Every other part (MT24-3b–d, MT24-4, MT23-2a–b, MT23-4, MT21-3) agrees with its key after re-solving.