19. SRAM: the 6T cell, its read and write circuits and the decoder

An SRAM is the memory a processor reaches every cycle: its level-one caches and register files. Chapter 18 showed the array: word lines across, bit-line pairs down, a cell at every crossing, a row decoder at the side and the read and write circuits at the bottom. This chapter opens the cell and builds the circuits around it. The cell is the 6T cell, Chapter 13’s loop of two inverters with two access transistors that connect it to the bitlines. It must be small, because the whole array multiplies it, and two requirements pull its three device sizes in opposite directions: a read must not upset it, and a write must succeed. The lecture then builds the column’s periphery on two clock phases: precharge, a word line qualified by the clock, a single-ended read, the write drivers, the column multiplexer and the sense amplifier. It ends with the decoder that raises one word line, built as a dynamic gate pair with a deliberate race. The cell is introduced at the end of Lecture 17 (58:00–64:30) and repeated at the start of Lecture 18; this chapter takes both.

After this chapter you can:

1. draw the 6T cell and give its read and write sequences;
2. say which devices fight during a write and during a read, and derive the two sizing ratios;
3. estimate the node voltage in each fight with a resistor divider;
4. read hold, read and write on the butterfly diagram, and say what the largest square measures;
5. explain why tiny cell devices fail at random, and name the remedies;
6. trace a column’s read and write through the two clock phases;
7. size the write path’s stack and say why fewer series devices help;
8. draw a column multiplexer, say what it buys and what it costs the write path;
9. explain how a clocked sense amplifier reads a small swing, and what its offset costs;
10. build a decoder from ANDs, predecode it as NAND–NOR, and qualify it with the clock;
11. explain the race in the race-based NOR and state the non-overlap condition;
12. estimate a decode path’s and a bitline’s delay, and the access time in FO4.

Boxes and equations marked board were written in the lecture. Parts marked added are explanations or examples this guide adds. The example cell added, used for numbers throughout: a cell PFET of 0.2 µm, access NFETs of 0.3 µm and pull-down NFETs of 0.6 µm (the board’s ratios), a bitline of 120 fF and $V_{DD} = 1.0$ V. These are this guide’s numbers, not the course’s; each use says “for example”.

Symbols

Symbol	Meaning	Unit	First appears
bit, $\overline{\text{bit}}$	a column’s pair of bitlines (board; FN17 writes B, $\bar B$Bˉ)	—	§1
WL	a word line (board “wordline”)	—	§1
$V_1$V1​, $V_2$	the cell’s two inner nodes, on the bit side and the $\overline{\text{bit}}$ side (L17 board)	V	§1
$V_{DD}$	the supply	V	§1
$W_p$Wp​, $W_a$Wa​, $W_{pd}$	widths of the cell’s PFET, access NFET and pull-down NFET added	µm	§1
$R$	the resistance of a 1 µm NFET pulling down (Chapter 7’s constant of proportionality); a device of width $W$ is $R/W$	kΩ·µm	§2
$V_X$	the written node’s voltage during a write fight (Chapter 13)	V	§2
$V_M$	an inverter’s switching threshold (Chapter 6)	V	§2
$\beta$	the cell ratio $W_{pd}/W_a$ added	—	§3
$V_{read}$	the voltage the 0 node rises to during a read added	V	§3
$V_L$VL​, $V_H$	the lifted low and the capped high in the butterfly sketches added	V	§4
SNM	static noise margin: the side of the largest square in a lobe of the butterfly added	V	§4
$\phi_1$ϕ1​, $\phi_2$ϕ2​; $\bar\phi_1$ϕˉ​1​, $\bar\phi_2$	the two clock phases and their complements (board)	—	§6
$t_{NO}$	non-overlap time, from $\phi_2$ falling to $\phi_1$ rising (Chapter 14)	ps	§6
$C_{BL}$CBL​, $C_{WL}$	a bitline’s and a word line’s capacitance added	fF	§7
$C_g$	gate capacitance per µm of width, 2 fF/µm in the examples	fF/µm	§7
$\tau_{inv}$	the fan-out-of-one delay (Chapter 7; FN10 writes $\tau_1$τ1​)	ps	§7
$W_{eq}$	the equivalent width of devices in series, $1/\sum(1/W_i)$	µm	§7
$t_{BL}$	the bitline’s delay from $V_{DD}$ to $V_{DD}/2$ added	$\tau_{inv}$	§7
$\Delta V$	the bitline swing when the read is detected added	V	§7
data, write	the column’s write data and write enable (board)	—	§8
col 1, col 2	the column-select lines of a multiplexer (board)	—	§9
$R$R, $C$C, $W$W, $N_w$	rows, columns, bits per word and words of a memory (Chapter 18’s names; this $R$ and $W$ are counts)	—	§9
$s$s, $\bar s$	the sense amplifier’s two sense nodes added	—	§10
$V_{os}$	a sense amplifier’s input offset voltage (board “input offset voltage”)	mV	§10
$a_0 \dots a_{n-1}$	address bits (board)	—	§11
$X$X, $Y$	the race-based NOR’s first- and second-stage nodes added	—	§12
$t_{eval}$	a dynamic stage’s evaluation delay	$\tau_{inv}$	§12
FO4	the fan-out-of-four delay; FN10 takes FO4 ≈ 3 $\tau_{inv}$	$\tau_{inv}$	§13

1. The 6T cell: storing a bit, reading and writing it

You need

Static storage (Chapter 13 §4–§5). Two inverters in a ring hold each other’s outputs: if $V_1$ is high, the inverter it drives makes $V_2$ low, and that inverter’s partner makes $V_1$ high again. The ring has two stable states, $(V_1, V_2) = (1, 0)$ and $(0, 1)$(0,1), and keeps either as long as the supply is on. On the butterfly diagram the two transfer curves, one mirrored, cross three times: the two outer crossings are the stable states and the middle one is metastable.

The butterfly diagram (Chapter 13): two stable crossings and a metastable one between them. Original figure ↗

The array (Chapter 18 §10). One row per word line, one column per pair of bitlines. The row decoder raises one word line; the columns end in the read and write circuits.

The question. How do you store one bit in as few transistors as possible, and still read it and write it through wires shared with every other cell in its column?

Six transistors

Building the cell (board, L17 59:32–60:24 and 64:30; L18 01:33)

1. Start from the loop. Two inverters, each driving the other’s input, store the bit (Chapter 13). Name the nodes as the board does: $V_1$ on the left, $V_2$ on the right.
2. Add two doors. An NFET connects $V_1$ to a vertical wire, bit, and a second NFET connects $V_2$ to its own wire, $\overline{\text{bit}}$bit. Their gates sit on a horizontal wire, the word line. These two NFETs are the access transistors (board, L17 64:30): with the word line low they are off and the loop is sealed; with it high, both nodes are connected to their bitlines.
3. Count. Each inverter is a PFET and an NFET, so the cell is $4 + 2 = 6$ transistors. Every cell in a column shares the same bit and $\overline{\text{bit}}$bit; every cell in a row shares the same word line.
4. Symmetric halves. “These two inverters are sized identically. … completely symmetric” (L17 60:24). The left half and the right half are mirror images. §2 and §3 will size the three devices within one half against each other; that does not break the symmetry between the halves.

The 6T cell, redrawn from the boards (Lecture17 @ 64:30, Lecture18 @ 01:33). (a) As the boards draw it: bit on the left and $\overline{\text{bit}}$ on the right, the word line WL across the top, the two access NFETs (gates on WL) from the bitlines to the inner nodes $V_1$ and $V_2$V2​, and two cross-coupled inverters between the nodes. (b) The same cell with each inverter drawn as its PFET over its NFET: six transistors. One device of each kind is labelled with its width: $W_p$ (the cell’s PFET), $W_{pd}$ (the pull-down NFET) and $W_a$ (the access NFET); the other half is the mirror image.

The board (Lecture17 @ 64:30)

Lecture17 @ 64:30The end of Lecture 17: the SRAM array, the 6T cell with its access transistors, the butterfly, and the read and write sequences.

Fair copy of the board above (Lecture17 @ 64:30), mark for mark in its own layout. All black: one cyan pen wrote the whole board. The board draws each transistor as a gate bar over a channel bump and each inverter as a small D shape with a bubble. “address bits” is written in three pieces beside the decoder. The lower-left corner (the bus marked 2 with its slash, and the left end of the column-multiplexer box), under the lecturer’s hands here, is read on 60:47; the array is unchanged since then. “⇒ either bit/”, which the hand squeezed in against “memory”, is set a little to its right.

Reading and writing

The board at L17 64:30 writes both sequences board. Follow a cell that holds $V_1 = 0$0, $V_2 = 1$1.

A read, then a write (board, L17 64:30; speech 61:25–63:56)

1. Read: precharge. Before the access, both bitlines are pulled up to $V_{DD}$ and left there.
2. Read: select. The decoder raises the cell’s word line, which turns both access transistors on.
3. Read: one bitline falls. On the $\overline{\text{bit}}$ side, $V_2 = 1$ meets a bitline that is also high: no voltage across the access device, no current. On the bit side, $V_1 = 0$ is held at ground by its pull-down NFET, so current flows from bit through the access NFET and the pull-down into ground, and bit sags. “One of these will pull down. Not both of them” (L17 62:06). The cell is tiny and the bitline is long, so the sag is slow.
4. Read: detect. A circuit at the bottom of the column sees which bitline fell (§7, §10). Bit fell, so $V_1 = 0$0.
5. Write: precharge and select, as for a read.
6. Write: pull one bitline low. To write $V_1 = 1$1, a driver at the bottom pulls $\overline{\text{bit}}$ actively to ground; bit is “kept at its precharge value” (L17 63:31). The low $\overline{\text{bit}}$ drags $V_2$ down through its access device. Once $V_2$ falls far enough, the inverter it drives raises $V_1$V1​, and the loop flips. Had the cell already held $V_1 = 1$1, the same write would store the same value again.

The read and the write as waveforms added (the sequences are the board’s, Lecture17 @ 64:30; a sketch without values). The cell starts with $V_1 = 0$0, $V_2 = 1$1. Left, a read: WL rises; bit sags slowly by a small amount $\Delta V$ while $\overline{\text{bit}}$ stays high; $V_1$ bumps up a little and stays low; WL falls. Right, a write of $V_1 = 1$1: WL rises, and on the same clock edge (§8) $\overline{\text{bit}}$ is driven quickly to 0; $V_2$ falls and $V_1$ rises until they cross; bit stays high; WL falls and the cell holds the new state.

Why only six, and the two requirements

“Density, of course, is paramount” (L17 59:02). An array has millions of cells, so one more transistor per cell costs millions of transistors. Cells with eight or ten transistors exist, but they have not caught on (L18 17:25; §5). The cell stays at six, and “people have figured out ways of using the peripheral circuits to compensate” (L17 59:32): that is the rest of this chapter.

Six minimum-area devices leave two requirements board (L18 02:18):

• Read stability. Reading must not flip the cell. During a read the access device pushes current into the 0 node; the node must stay low (§3).
• Writability. Writing must flip the cell. During a write the access device must pull the 1 node down against the cell’s own PFET (§2).

Both are fights between the access transistor and a device inside the cell, and they ask opposite things of it: strong enough to win the write, weak enough to lose the read.

A worked example (the board’s sequences, with this guide’s labels). The cell holds $V_1 = 0$0, $V_2 = 1$1. In a read, which access device carries current? Only bit’s: its bitline is at $V_{DD}$ and its node at 0, while $\overline{\text{bit}}$‘s device has $V_{DD}$ on both sides. Bit falls, $\overline{\text{bit}}$ stays high. To write $V_1 = 1$1, pull $\overline{\text{bit}}$ low: now $\overline{\text{bit}}$‘s access device carries the current, from $V_2$ into the bitline, and bit’s device carries almost none until the cell flips.

Traps.

• “The word line selects a column.” It selects a row: every cell on it connects to its bitlines at once. The bitlines are the columns.
• “In a read both bitlines move.” Only the bitline on the side holding 0 falls.
• Reading the state from the wrong side. A 0 on $V_1$ shows as bit falling; a 0 on $V_2$ as $\overline{\text{bit}}$ falling.

Check yourself Why are both bitlines precharged high before a read, rather than low?

A low bitline would write the cell: on the side holding 1, the access device would pull that node down, exactly as a write does. A high bitline is harmless on the side holding 1 (no voltage across the access device) and only slightly disturbs the side holding 0, where the pull-down holds the node (§3). And a 0 node can pull a high bitline down, which is the read signal; it could not pull a low one any lower.

Check yourself (Two steps.) An array has 256 rows and 256 columns. How many access transistors connect to each bitline, and how many access-transistor gates load each word line?

Each bitline runs down one column and meets one cell per row, with one access device on its side: 256 drains per bitline. Each word line runs across a row and meets 256 cells, and each cell has two access devices with their gates on it: $2 \times 256 =$ 512 gates per word line. §12 uses this count for the word line’s load.

Check yourself A cell holds V₁ = 1. A write pulls bit low. What happens, and which device carries the current at first?

Bit’s access device conducts from $V_1$ into the low bitline, fighting the cell’s PFET that holds $V_1$ up. If the access path wins (§2), $V_1$ falls below the other inverter’s threshold, $V_2$ rises, and the cell flips to $V_1 = 0$0.

2. Writability: the access NFET must beat the cell’s PFET

You need

The write fight and its divider (Chapter 13 §7). When two on paths fight over one node, one from $V_{DD}$ and one to ground, treat each as a resistor and the node sits at the divider’s voltage:

$$V_X = V_{DD}\,\frac{R_{down}}{R_{up} + R_{down}} .$$

An NFET of width $W$ pulling down is $R/W$R/W; a PFET of width $W$ pulling up is $2R/W$2R/W, because holes are about half as mobile as electrons, so a PFET must be twice as wide to be as strong (Chapter 7). Devices in series add. The write succeeds when $V_X$ falls below the switching threshold $V_M$ of the inverter the node drives. The model compares strengths; it does not predict exact voltages.

Chapter 13’s write fight as a divider. Original figure ↗

The cell (§1): two access NFETs ($W_a$Wa​) from bit and $\overline{\text{bit}}$ to $V_1$ and $V_2$V2​, and two inverters (PFET $W_p$Wp​, pull-down NFET $W_{pd}$Wpd​).

The 6T cell (§1). Original figure ↑

The question. A write pulls one bitline to ground. The node on that side holds 1, and the cell’s own PFET is holding it there. Who must win, and by how much?

The fight

The writability fight (board, 02:12–04:30)

1. The scene. Write a 0 into the node that holds 1, say $V_2$V2​. The driver at the bottom of the column pulls $\overline{\text{bit}}$ to ground through “a couple of transistors” (02:34; §8 builds them). The word line is high, so the access NFET connects $\overline{\text{bit}}$ to $V_2$V2​.
2. Who holds the node up. $V_2$ is the output of the inverter whose input is $V_1 = 0$0. Its NFET is off, and its PFET is on: the board marks it “ON”. The PFET pulls $V_2$ toward $V_{DD}$VDD​.
3. Who pulls it down. The access NFET, in series with the driver, pulls $V_2$ toward ground. “This path beats this one” (03:09): the access path must be the stronger, assuming the driver is strong.
4. When it has won. $V_2$ need not reach 0. It must fall below the switching threshold of the inverter it drives; then $V_1$ rises, the PFET that was holding $V_2$ up turns off, and the loop finishes the flip by itself.

The writability fight, redrawn from the board (Lecture18 @ 04:20). (a) $\overline{\text{bit}}$ is pulled to ground by the two series NFETs of the write driver (gates at 1). The access NFET (gate WL = 1, width $W_a$Wa​) connects it to $V_2$V2​, which holds 1 and is being pulled down. The inverter driving $V_2$ is drawn as its devices: its PFET ($W_p$Wp​) is on and pulls $V_2$ up; its NFET is off (dashed); both gates are at $V_1 = 0$0. (b) The same fight as a divider added: $2R/W_p$ from $V_{DD}$ to $V_X$VX​, then $R/W_a$ and the driver’s resistance in series to ground.

The ratio: three times as strong, one and a half times as wide

The board’s rule board (04:20): “access nFET ~3X strength [of] the pFET, 1.5x size”. The lecturer first says “3x the size”, then corrects himself: “3x the strength, sorry, which means 1.5x the size difference, right? Because the PFET is going to be a weaker device” (04:06).

Why 3× strength is 1.5× width (derive)

1. Strength per width. An NFET of width $W$ has resistance $R/W$R/W: strength $\propto W$W. A PFET of width $W$ has $2R/W$2R/W: strength $\propto W/2$W/2.
2. Set the ratio. Access strength over PFET strength $= W_a / (W_p/2) = 2W_a/W_p$2Wa​/Wp​. The board wants 3.
3. Solve. $2W_a/W_p = 3$3, so $W_a = 1.5\,W_p$1.5Wp​. A strength ratio and a width ratio differ by the mobility factor of 2.

Writability: the access NFET against the cell's PFETboard

$$\frac{2W_a}{W_p} \approx 3 \quad\Longrightarrow\quad W_a \approx 1.5\,W_p$$

Holds when: the cell's PFET half as strong as an NFET of the same width (μn ≈ 2μp, Chapter 7); the write driver strong; 3× is a design rule, not a hard limit

Memorize the rule and its reason: access about 3× the PFET’s strength, 1.5× its width, because a PFET of the same width is half as strong.

How far down the node goes

The divider added (Chapter 13’s model) says where the node settles while the fight lasts. With an ideal driver (bitline at 0), $R_{up} = 2R/W_p$ and $R_{down} = R/W_a$R/Wa​. At 3× strength, $R_{up} = 3R_{down}$3Rdown​:

$$V_X = V_{DD}\,\frac{R_{down}}{3R_{down} + R_{down}} = \frac{V_{DD}}{4} .$$

That is far below the switching threshold $V_M$ of the cell inverter the node drives, which sits below $V_{DD}/2$ because the cell’s pull-down is far stronger than its PFET (§3): the write wins with margin. The margin matters because every device in series with the access NFET (the driver’s stack in §8, the column multiplexer in §9) adds to $R_{down}$Rdown​, and because the devices vary from cell to cell (§5).

The written node during the fightadded

$$\begin{gathered} V_X \approx V_{DD}\,\frac{R_{down}}{R_{down} + R_{up}} \\ R_{down} = \frac{R}{W_a} + \sum_i \frac{R}{W_i}, \qquad R_{up} = \frac{2R}{W_p} \end{gathered}$$

Holds when: Chapter 13's divider: NFETs pulling down R/W, the cell's PFET pulling up 2R/W; W_i are the widths of the write path's devices in series below the access NFET (none for an ideal driver); rough, it compares strengths

Derive it on the exam in three lines: the PFET’s resistance, the pull-down path’s resistance (access plus every series device), the divider.

A worked example added (the example cell, for example: $W_p = 0.2$ µm, $W_a = 0.3$ µm).

The example cell's write

1. Pull-up. The PFET: $R_{up} = 2R/0.2 = 10R$10R.
2. Pull-down, ideal driver. The access NFET alone: $R_{down} = R/0.3 = 3.33R$3.33R.
3. Divider. $V_X = 3.33/(3.33 + 10)\,V_{DD} = 0.25\,V_{DD}$0.25VDD​: the board’s ratio gives a quarter of the supply.
4. Without the ratio. Make the access NFET as wide as the PFET, $W_a = 0.2$ µm: $R_{down} = 5R$ and $V_X = 5/15 = 0.33\,V_{DD}$0.33VDD​. Still below $V_{DD}/2$ in this crude model, but closer to that lowered threshold $V_M$VM​, with less room for the driver, the multiplexer and the device spread.

The board (Lecture18 @ 04:20)

Lecture18 @ 04:20Writability: the access NFET against the cell's PFET, and the rule: about 3× the strength, 1.5× the size.

Fair copy of the board above (Lecture18 @ 04:20), mark for mark in its own layout. All black: a violet pen wrote the title, “SRAM”, “6T SRAM” and the cell; a pale cream pen wrote everything from “read stability” on. The cream writes the next topic beside the cell rather than a layer over it, so it takes no accent. The board draws each transistor as a gate bar beside a channel bump, a supply as a short T bar and ground as a small triangle. In the sketch, the access NFET and the cell’s PFET (marked ON) are ringed separately, and the two-NFET stack at the foot of the bitline is ringed too. “wordline”, washed out by the lecturer’s face here, is read on 01:33; the “access” label and the lower edge of its ring, under his hand, on 06:40.

Traps.

• Reading “3X” as a width ratio. 3× is the strength; the width ratio is 1.5×.
• A stronger PFET “to hold the data better.” The cell’s PFET is exactly the device the write must overpower; strengthening it makes the cell unwritable.
• The access NFET alone. It does not fight alone: the driver’s devices are in series with it, and each one raises $V_X$VX​.

Check yourself If a PFET were a third as strong as an NFET of the same width, what width ratio W_a/W_p would make the access NFET 3× as strong as the PFET?

Access strength over PFET strength $= W_a / (W_p/3) = 3W_a/W_p = 3$3, so $W_a/W_p =$ 1.0.

Check yourself (Two steps.) For example: the example cell (W_p = 0.2 µm, W_a = 0.3 µm) is written through two series 0.6 µm NFETs below the access device. Where does the node settle?

Pull-down: $R_{down} = R/0.3 + 2R/0.6 = 3.33R + 3.33R = 6.67R$6.67R. Pull-up: $R_{up} = 2R/0.2 = 10R$10R. Divider: $V_X = 6.67/16.67\,V_{DD} =$ 0.40 $V_{DD}$VDD​, up from 0.25 with an ideal driver: the series devices ate more than half the margin to $V_M$VM​, which is smaller than the 0.25 to $V_{DD}/2$VDD​/2.

3. Read stability: the access NFET must lose to the pull-down

You need

The divider (§2; Chapter 13’s model). Two on paths fighting over a node leave it at $V_{DD}\,R_{down}/(R_{up} + R_{down})$Rdown​), with $R/W$ for an NFET pulling down. Rough: it compares strengths.

An NFET pulling up is weak (Chapter 13 §7). Its source is the node it is raising, so its gate-to-source voltage shrinks as the node rises, and it cannot pull higher than $V_{DD} - V_T$VT​. The course’s estimate treats it as $2R/W$2R/W, like a PFET.

The switching threshold (Chapter 6). An inverter’s output flips when its input crosses $V_M$VM​: near $V_{DD}/2$ for a balanced inverter, lower when its NFET is the stronger device.

The 6T cell (§1). Original figure ↑

The question. During a read the bitline sits at $V_{DD}$ and the access device connects it to the node that holds 0. That node’s pull-down holds it at ground. How high does the node rise, and what keeps it from flipping the cell?

The fight

The read-stability fight (board, 04:40–06:40)

1. The scene. The bitline was precharged to $V_{DD}$ (the board draws its precharge device at the top). The word line is high (“1”). The node holds 0 (“0”), and the inverter driving it has its pull-down NFET on (the board marks it “ON”), because that inverter’s input is the other node, at 1.
2. The fight. Current flows from the bitline, through the access NFET, into the node, and through the pull-down to ground. The node is the middle of a divider: the access NFET pulls it up, the pull-down pulls it down.
3. The danger. The node rises a little. If it rises past the threshold of the inverter it drives, that inverter’s output (the other node, at 1) starts to fall, which turns the pull-down off, and the read flips the cell.
4. The rule. “Weaken this path relative to this one” (05:56): the access NFET must be the weaker, “1.5 to 2x smaller … than the NFET” (06:23). Both are NFETs, so the width ratio is the strength ratio.

The read-stability fight, redrawn from the board (Lecture18 @ 06:40). (a) bit is precharged to $V_{DD}$VDD​. The access NFET (gate WL = 1, width $W_a$Wa​) connects it to $V_1$V1​, which holds 0 and is pushed up. The inverter driving $V_1$ is drawn as its devices: the pull-down NFET ($W_{pd}$Wpd​) is on and holds $V_1$ low; the PFET is off (dashed); both gates are at $V_2 = 1$1. (b) The divider added: $2R/W_a$ from $V_{DD}$ to $V_{read}$Vread​, then $R/W_{pd}$ to ground.

How high the node rises

The read bump as a divider (derive)

1. Pull-down. The pull-down NFET pulls down: $R_{down} = R/W_{pd}$R/Wpd​.
2. Pull-up. The access NFET pulls up, so it is weak: $R_{up} \approx 2R/W_a$2R/Wa​.
3. Divider. $V_{read} = V_{DD}\,\dfrac{R/W_{pd}}{R/W_{pd} + 2R/W_a}$VDD​R/Wpd​+2R/Wa​R/Wpd​​. Divide top and bottom by $R/W_{pd}$ and write $\beta = W_{pd}/W_a$Wpd​/Wa​: $V_{read} = V_{DD}/(1 + 2\beta)$2β).

The read bumpadded

$$V_{read} \approx \frac{V_{DD}}{1 + 2\beta}, \qquad \beta = \frac{W_{pd}}{W_a}$$

Holds when: Chapter 13's divider with the access NFET pulling up at about 2R/W_a and the pull-down at R/W_pd; β = W_pd/W_a; the bitline still near V_DD; rough, it compares strengths

The board’s range: $\beta = 1.5$ gives $0.25\,V_{DD}$0.25VDD​, $\beta = 2$ gives $0.20\,V_{DD}$0.20VDD​. With equal widths, $\beta = 1$1, the node would reach $0.33\,V_{DD}$0.33VDD​.

Why the margin matters more than the bare number. The cell’s inverters are skewed: their pull-down NFET is the strongest device in the cell and their PFET the weakest, so their threshold $V_M$ sits well below $V_{DD}/2$ (the skew argument of Chapter 11 §7, in reverse). The bump must stay below that lowered threshold, and random variation (§5) moves the threshold further from cell to cell.

Read stability: the pull-down against the access NFETboard

$$W_{pd} \approx (1.5\text{–}2)\,W_a$$

Holds when: both NFETs; the width ratio is the strength ratio

Memorize the rule; derive the bump in three lines (above).

Both rules together

§2 says the access NFET must be about 3× as strong as the PFET; this section says the pull-down must be 1.5–2× as strong as the access NFET. Together they order the cell’s three devices:

$$\begin{gathered} \text{pull-down} \;>\; \text{access} \;>\; \text{PFET} \\ \text{strengths } (1.5\text{–}2) : 1 : \tfrac{1}{3}, \qquad \text{widths } (1.5\text{–}2) : 1 : 0.67 . \end{gathered}$$

The two rules constrain different pairs (access against PFET, access against pull-down), so they never conflict. With such tiny devices, reaching the ratios can take “non-minimum length” on some of them (15:33): a longer channel makes a device weaker without making it narrower than the rules allow.

Memorize the order: pull-down strongest, access in the middle, PFET weakest.

The example cell’s sizes added (for example; the ratios are the board’s, Lecture18 @ 04:20 and 06:40): the six-transistor cell with PFETs of 0.2 µm, access NFETs of 0.3 µm and pull-down NFETs of 0.6 µm. One bracket joins an access NFET and the PFET on the same node, $W_a/W_p = 1.5$ (the write fight); the other joins the same access NFET and the pull-down, $W_{pd}/W_a = 2$ (the read fight).

A worked example added (the example cell, for example). $\beta = 0.6/0.3 = 2$2, so $V_{read} = V_{DD}/(1 + 4) = 0.20\,V_{DD}$0.20VDD​, which is 0.20 V at $V_{DD} = 1.0$ V. On a past final (FN10-5b) the cell’s NFETs are both 1 µm, so $\beta = 1$ and the bump would be $0.33\,V_{DD}$0.33VDD​: that cell ignores the read rule. The question asks only for the bitline’s delay, which depends on the series path of the two NFETs, not on where the node settles, so the estimate does not care.

The board (Lecture18 @ 06:40)

Lecture18 @ 06:40Read stability: the access NFET against the pull-down, which must be 1.5–2× larger; the writability sketch is still at the right.

Fair copy of the board above (Lecture18 @ 06:40), mark for mark in its own layout, on the coordinates of the 04:20 copy: the right half is that board’s, unchanged. All black: only “Lecture 18” is in the violet pen; the pale cream pen wrote the rest. The cell, “SRAM” and “6T SRAM” have been erased, and the read-stability sketch stands in their place. The quoted “0” at the node, with the short stroke and dot beside it, is copied as drawn.

Traps.

• A stronger access NFET to speed the read. It discharges the bitline faster and lifts the 0 node higher: the read gets faster and less stable.
• $R/W$ for the access NFET pulling up. It pulls up weakly, about $2R/W_a$2R/Wa​. With $R/W_a$ the estimate for $\beta = 1$ would be $V_{DD}/2$VDD​/2, past the cell’s lowered threshold; with $2R/W_a$ it is $0.33\,V_{DD}$0.33VDD​.
• “The two rules conflict.” They constrain different pairs and are met together by the order pull-down > access > PFET.

Check yourself What cell ratio β keeps the read bump below 0.15 V_DD?

$1/(1 + 2\beta) < 0.15$ means $1 + 2\beta > 6.67$6.67, so $\beta >$ 2.83: beyond the board’s 1.5–2.

Check yourself (Two steps.) For example: a designer widens the example cell's access NFETs from 0.3 to 0.45 µm to speed reads (W_pd = 0.6 µm, W_p = 0.2 µm). What happens to the read bump, and to §2's V_X with an ideal driver?

Read: $\beta = 0.6/0.45 = 1.33$1.33, $V_{read} = 1/(1 + 2.67) =$ 0.27 $V_{DD}$VDD​, up from 0.20. Write: $R_{down} = R/0.45 = 2.22R$2.22R, $R_{up} = 2R/0.2 = 10R$10R, $V_X = 2.22/12.22 =$ 0.18 $V_{DD}$VDD​, down from 0.25. The wider access device writes more easily and reads less safely: the two requirements pull it in opposite directions.

4. The butterfly: hold, read and write

You need

The butterfly diagram (Chapter 13 §5). Plot one inverter’s transfer curve, $V_1$ against $V_2$V2​, and on the same axes the other inverter’s, mirrored ($V_2$V2​ against $V_1$V1​). Where the two curves cross, each inverter’s output is the other’s input: the loop’s equilibria. A storage loop has three crossings: two stable states at the corners and a metastable one in the middle. The curves enclose two eye-shaped lobes, the “wings”.

The butterfly diagram (Chapter 13). Original figure ↗

A write on the butterfly (Chapter 13 §7). A writer fighting one inverter squashes that inverter’s curve; when the squashed curve no longer reaches the old state’s corner, only one crossing is left and the loop must go there.

The write on the butterfly (Chapter 13). Original figure ↗

The two dividers (§2, §3). During a read each 0 node rises to $V_{read} = V_{DD}/(1 + 2\beta)$2β); during a write the node being pulled down settles at $V_X$VX​, $0.25\,V_{DD}$ for the example cell with an ideal driver.

The question. §2 and §3 looked at one node in one fight. What do the two fights do to the whole loop, and how can one number say how safe a read is?

Hold, then read

The sketches here use Chapter 13’s drawing aid added, an S-curve $f(v) = V_{DD}/(1 + e^{12(v/V_{DD} - 0.5)})$ for each inverter. It is a picture, not a device model; only the lifted lows and capped highs come from the dividers.

From hold to read (board, 07:41–10:11)

1. Hold. The word line is low, both access devices are off, and the cell is Chapter 13’s loop: “a bistable … a metastable state here … two stable states” (07:41–08:27). The thin curves in the figure: two lobes, three crossings.
2. Read. Both access devices turn on, with both bitlines at $V_{DD}$VDD​. Whichever node is low is now pushed up by its access device: that inverter’s low output is lifted to $V_{read}$Vread​, $0.20\,V_{DD}$ for $\beta = 2$2. Both inverters are affected (either node can be the low one), so both curves’ low ends rise. The thick curves: “the wings … are going to get smaller” (08:28–09:41).
3. Measure the wings. “The largest square that I can fit inside of these butterfly wings is … quantitatively a way that people look at the noise margins of SRAM cells” (09:41). The side of that square is the static noise margin (SNM) added (the name is the textbooks’): a noise voltage smaller than the side cannot push the loop out of its lobe. In the sketch, the hold square is $0.217\,V_{DD}$ and the read square, for $\beta = 2$2, $0.127\,V_{DD}$0.127VDD​.
4. Squeeze to nothing. A weaker pull-down lifts the lows further. For $\beta = 1.5$ the read square is $0.103\,V_{DD}$0.103VDD​; for $\beta = 1$1, $0.062\,V_{DD}$0.062VDD​. If a lobe closes, the read has only one stable crossing left: reading the cell writes it.

Hold and read on the butterfly added, computed from Chapter 13’s drawing aid with the read low lifted to $V_L = 0.20\,V_{DD}$ (§3’s divider, $\beta = 2$2); a sketch, not a device model. Axes $V_2$ across and $V_1$ up, to $V_{DD}$VDD​. Thin: the hold curves. Thick: the read curves, whose low ends sit at $V_L$VL​. The largest square in each lobe: dashed for hold (side $0.217\,V_{DD}$0.217VDD​), solid for read (side $0.127\,V_{DD}$0.127VDD​). Dots mark the read curves’ crossings: two stable (filled), one metastable (hollow).

The board (Lecture18 @ 19:23)

Lecture18 @ 19:23The butterfly for hold and read (left), the write butterfly (right), and the variability notes of Section 5 (middle).

Fair copy of the board above (Lecture18 @ 19:23), mark for mark in its own layout. Black is the violet pen: both cells, the hold butterfly and both pairs of axes. It also stands for the blue pen of the variability notes in the middle, which writes the next topic beside the drawings rather than a layer over them. Magenta is the pink pen, the read layer: the precharge T’s on the read cell’s bitlines, the two read curves and the hatching of their lobes. Orange is the pale cream pen, the write layer: the T on the write cell’s bit, the write butterfly and the ring on its single crossing. The write butterfly was drawn, wiped and redrawn, and its smeared strokes are copied as strokes. The ringed numbers are dopant counts (Section 5).

Write

The write on the butterfly (board, 10:47–13:30)

1. The scene. To write $V_1 = 0$ into a cell that holds $V_1 = 1$1, pull bit low and keep $\overline{\text{bit}}$ at its precharge (the mirror of §2’s scene, which wrote through $\overline{\text{bit}}$bit).
2. The $\overline{\text{bit}}$ side behaves as in a read. Its access device sees a high bitline, so the curve of the inverter driving $V_2$ has its low end lifted, as in step 2 above.
3. The bit side is capped. The inverter driving $V_1$ is fighting the low bitline: its output can rise only to the divider’s level, it “is only going to be able to make it up to this” (12:31). Its curve is squashed down to $V_H = V_X$VX​, $0.25\,V_{DD}$ for the example cell.
4. One crossing. The capped curve no longer reaches the upper-left corner, so the old state’s lobe has vanished. One crossing remains, near $V_1 = 0$0, $V_2 = V_{DD}$VDD​: the new state. The cell is written.
5. A failed write. “If for some reason … I still have these two states, then … that cell is not writable” (13:00–13:30). In the sketch, a cap of $V_H = 0.9\,V_{DD}$ (a far too weak access path) leaves three crossings, and the old state at $V_1 = 0.873\,V_{DD}$ survives. The change from one crossing to three happens between $V_H = 0.71$ and $0.72\,V_{DD}$ in this sketch: an illustration, not a design number.

The write on the butterfly added, computed from the drawing aid (a sketch, not a device model). In both panels the curve of the inverter driving $V_2$ is read-lifted ($V_L = 0.20\,V_{DD}$VL​=0.20VDD​, thin); the curve of the inverter driving $V_1$ is shown undisturbed (dashed grey) and capped at $V_H$ (thick). Left, $V_H = 0.25\,V_{DD}$ (§2’s divider): one crossing, the new state $V_1 \approx 0$0, $V_2 \approx V_{DD}$VDD​. Right, $V_H = 0.9\,V_{DD}$0.9VDD​: three crossings, and the old state ($V_2 = 0.209$V2​=0.209, $V_1 = 0.873\,V_{DD}$0.873VDD​) survives: not writable.

“In read stability, I don’t want the butterfly diagram to pull apart. In writability, I do” (13:30). A read must leave both lobes open; a write must close one.

Memorize the definition: the static noise margin is the side of the largest square that fits in the smaller lobe of the read butterfly. Remember that the numbers in these sketches are not device numbers.

Try it added. The widget sets the three widths of the cell. The read lift $V_L = V_{DD}/(1 + 2\beta)$ and the write cap $V_H = V_X$ come from §2’s and §3’s dividers, and the curves are the drawing aid. Widen the access NFET and watch the read square shrink while the write gets easier. The PFET alone cannot break the write from these widths: at the slider’s end, 0.60 µm, $V_H = 0.50\,V_{DD}$0.50VDD​, and the sketch still writes. Narrow the access NFET to 0.10 µm first; then a PFET of 0.40 µm gives $V_H = 0.67\,V_{DD}$0.67VDD​, and the write fails.

cell PFET width W_p

0.20 µm

access NFET width W_a

0.30 µm

pull-down NFET width W_pd

0.60 µm

β = W_pd/W_a

2.00

read: low lifted to V_L

0.200 V_DD

read square (SNM)

0.127 V_DD (hold 0.217)

access ÷ PFET strength

3.00

write: high capped at V_H

0.250 V_DD

write crossings

1

Both work: the read leaves two lobes with a square of 0.127 V_DD, and the write leaves one crossing, the new state.

Axes as Chapter 13's butterfly: V₂ across, V₁ up, in units of V_DD. Left: the hold curves (thin) and the read curves (thick), each low end lifted to V_L by the access NFET fighting the pull-down; the squares are the largest in each lobe. Right: a write of 0 into V₁: the curve of the inverter driving V₁ (dashed when undisturbed) is capped at V_H by the bitline pulling through the access NFET against the PFET; the other curve is read-lifted; dots mark the crossings. Added: Chapter 13's divider (R/W for an NFET pulling down, 2R/W for a PFET or an NFET pulling up, an ideal write driver) and its drawing aid f(v) = 1/(1 + e^{12(v − 0.5)}). The squares and crossings are sketch numbers, not device numbers.

Traps.

• The hold square as the margin. The read is the worst case: its lobes are smaller. The SNM that matters is the read SNM.
• “In a write one curve moves.” Both change: one is read-lifted, the other collapses.
• The sketch’s threshold as a design limit. The 0.71–0.72 $V_{DD}$ comes from the drawing aid’s steepness; real curves move it.

Check yourself During a read, only bit̄ is precharged (bit is left floating at 0 V by mistake). Which part of the read butterfly would still change as in §4, and why is the cell in danger anyway?

Only the inverter whose 0 node sits on the $\overline{\text{bit}}$ side gets its low lifted by a high bitline, so only the curve of the inverter driving $V_2$ is lifted. But the bit side now has a low bitline on an open access device: if $V_1$ holds 1, that is a write. The precharge of both lines is what makes a read a read.

Check yourself (Two steps.) With β = 1.5, where is the read's lifted low V_L, and does the read square rise or fall against β = 2?

$V_L = V_{DD}/(1 + 3) =$ 0.25 $V_{DD}$VDD​, higher than 0.20. The lows rise further, the lobes shrink, and the read square falls: 0.103 against 0.127 $V_{DD}$ in the sketch.

5. Variability, push rules and the remedies

You need

The threshold depends on the dopants under the gate (Chapter 6 §8). A transistor’s threshold voltage is set by the charge of the dopant atoms in its channel region. Devices drawn alike are not quite alike: their thresholds scatter, and so do their strengths.

The read square (§4). The static noise margin is the side of the largest square in the smaller lobe of the read butterfly; it shrinks as the read lifts the lows.

Hold and read on the butterfly (§4). Original figure ↑

The question. §2–§4 set the cell’s ratios on nominal devices. Why does a cell drawn with the right ratios still fail, at random, one in a million?

Push rules and tiny devices

SRAM cells are drawn with push rules board (14:28–15:33): design rules the foundry tunes for the SRAM cell alone, tighter than the rules for “normal logic”. The cell’s devices are the smallest on the chip, sometimes with non-minimum lengths to reach the ratios.

Countable dopants

Random dopant fluctuation (board, 15:53–16:43)

1. Count them. In a tiny device the dopant atoms under the gate are few enough to count. “Say I have … 30 … dopants … Some device might have 28, some … 32, some … 27, some … 33” (16:11; the board rings 28, 27, 30, 32, 33).
2. How big the spread is added. For atoms placed at random, the count scatters by about the square root of its mean (Poisson statistics, background): $\sqrt{30} = 5.5$5.5, an 18 % spread. So 27 and 33 are ordinary, not rare.
3. Each count gives its own threshold. The two inverters of one cell no longer match, and the access device no longer has its nominal strength against its neighbours.
4. Margins rest on ratios. §2–§4’s margins are ratios of strengths. A random mismatch can close the read lobe or keep the write’s old crossing in a single cell, and in an array of millions some cell is that unlucky one.

A mismatched cell during a read added, computed from Chapter 13’s drawing aid (a sketch, not a device model). Both curves are read-lifted to $V_L = 0.20\,V_{DD}$0.20VDD​, but the inverter driving $V_1$ has its threshold moved from $0.5$ to $0.4\,V_{DD}$0.4VDD​; its undisturbed symmetric read curve is dashed grey. The lobes are no longer equal: the upper-left square has side $0.064\,V_{DD}$0.064VDD​, the lower-right $0.164\,V_{DD}$0.164VDD​. The cell’s margin is the smaller.

A worked example added. Shift one inverter’s threshold by $0.1\,V_{DD}$ in the read sketch with $\beta = 2$2. The symmetric cell had two squares of $0.127\,V_{DD}$0.127VDD​; the mismatched one has $0.064$ and $0.164\,V_{DD}$0.164VDD​. Its noise margin is the smaller, $0.064\,V_{DD}$0.064VDD​: half the nominal, from one shift.

The remedies

In the lecturer’s order (speech, 17:25–19:45):

• More transistors per cell. Eight- and ten-transistor cells separate the read path from the cell’s nodes. “None of them have really caught on” (the density cost).
• Bigger devices. Fewer dopants matter less in a bigger device, but the cell grows: “highly undesirable”.
• Redundancy. Build spare cells; a self-check after manufacture finds the cells that fail and swaps in the spares (18:11).
• Supply tricks. Raise the cell’s supply during an access, which strengthens it for the read; lower it while the cell only retains data, so “the leakage power … is more controlled” (18:37).

“Six transistor cells continue to be used, and these other tricks are employed” (19:12). This term’s class makes the same point about few dopants in small devices (Fall 2026 Lecture 2), and about SRAM’s sensitivity to relative strengths at skewed corners (Lecture 5).

Traps.

• “A cell that meets the ratios always works.” The ratios are nominal; mismatch is random and per cell.
• “Bigger is free.” Every remedy that grows the cell is multiplied by the whole array; that is why the periphery does most of the work.

Check yourself Why does raising the cell's supply only during an access help, without costing much leakage?

Leakage is paid all the time, by every cell. The boost lasts only for the access, and only the accessed row needs it; the rest of the time the supply can even be lowered to save leakage while the cells retain their data.

Check yourself (Two steps.) In the mismatched read sketch, which stored state is the vulnerable one, and in which operation?

The vulnerable state is the one whose lobe is smaller: the upper-left lobe, $V_1$ high and $V_2$ low, with a square of $0.064\,V_{DD}$0.064VDD​. It is vulnerable during a read, when the lows are lifted; in hold the lobes are larger.

6. Two phases for the periphery: precharge and access

You need

Two-phase clocks (Chapter 14 §3). Two clocks, $\phi_1$ and $\phi_2$ϕ2​, are high in turn and never together. Between $\phi_2$ falling and $\phi_1$ rising, and between $\phi_1$ falling and $\phi_2$ rising, both are low: the non-overlap gaps. A generator can widen them on purpose.

Two-phase clocks and their non-overlap (Chapter 14). Original figure ↗

The question. The cell needs its bitlines precharged before every access, and the access must not start until the precharge has stopped. How does one clock cycle organize the two?

Precharge and access (board, 20:09–22:16)

1. Two phases. The read and write circuits, “the data path for the SRAM”, run on two clocks “nominally 180 degrees out of phase” (20:09). While $\phi_2$ is high the bitlines precharge; while $\phi_1$ is high the cell is accessed: its word line is up, and it is read or written.
2. Precharge on $\bar\phi_2$ϕˉ​2​. The precharge PFETs pull the bitlines to $V_{DD}$VDD​. Their gates are driven by $\bar\phi_2$ϕˉ​2​, so they are on exactly while $\phi_2$ is high.
3. Why not $\phi_1$ϕ1​. With ideal complementary clocks, $\bar\phi_2$ and $\phi_1$ are the same signal. Driving the precharge from $\bar\phi_2$ gives “the ability, should I choose to, to create non-overlap windows between φ1 and φ2” (21:48–22:16).
4. The gap. added With a gap, precharge ends when $\phi_2$ falls, and the word line can rise only when $\phi_1$ rises; between them sits $t_{NO}$tNO​, when neither is on. §12 spends that gap.

The two phases of the periphery, redrawn from the board (Lecture18 @ 21:42) with non-overlap gaps added (the board draws the clocks complementary). Rows $\phi_1$ϕ1​, $\phi_2$ and $\bar\phi_2$ over two cycles. Brackets mark each $\phi_1$ high (the access phase) and each $\phi_2$ high (the precharge phase). $t_{NO}$ marks the gap from $\phi_2$ falling to $\phi_1$ rising.

A worked example added (§12’s example decoder). Its stages I–III must finish between $\phi_2$ falling and $\phi_1$ rising, and they take $6.65\,\tau_{inv}$6.65τinv​: the gap must be $t_{NO} \ge 6.65\,\tau_{inv}$6.65τinv​. The precharge on $\bar\phi_2$ has stopped by then, so the whole gap is the decoder’s (Check 1). The other numbers come with the circuits, §7–§12.

Traps.

• Precharging on $\phi_1$ “because it is the same”. Only while the clocks are exactly complementary; with a gap, the choice decides what the gap can be used for.
• Precharge PFETs with $\phi_2$ on the gate. A PFET is on when its gate is low; to be on during $\phi_2$ it needs $\bar\phi_2$ϕˉ​2​.

Check yourself (Two steps.) Suppose the precharge PFETs were driven by φ₁ (on while φ₁ is low) and the word line by φ₁. Does this work with complementary clocks, and what changes when a gap is added?

With complementary clocks, “$\phi_1$ϕ1​ low” is exactly “$\phi_2$ϕ2​ high”, so the precharge stops as the access starts: it works. With a gap, the precharge (on whenever $\phi_1$ is low) now also runs through both gaps; it still stops when the word line rises, but the gap can no longer separate the end of precharge from the start of the access. The precharge-on-$\bar\phi_2$ version ends the precharge at $\phi_2$ falling, a whole $t_{NO}$ before the access, and that time is free for the decoder (§12).

Check yourself What would happen if the precharge PFETs were still on when the word line rose?

They would hold the bitlines at $V_{DD}$ while the cell tried to pull one down: the read signal would fight the precharge and never develop, and a write driver would fight it too, burning current.

7. Reading a column: the clock-qualified word line and the skewed inverter

You need

A stage’s delay from its gain (Chapter 8 §1). A stage’s delay, in units of the fan-out-of-one delay $\tau_{inv}$τinv​, is its gain: the capacitance it drives divided by the input capacitance of the normalized inverter, the inverter with the same pull-down strength (NFET $W_{eq}$Weq​, PFET $2W_{eq}$2Weq​, input $3W_{eq}$3Weq​). Devices in series combine like resistors: $W_{eq} = 1/\sum (1/W_i)$1/∑(1/Wi​). Capacitances can be counted in µm of gate width, with $C_g = 2$ fF/µm. The delay is to the 50 % point.

Skewed inverters (Chapter 11 §7). Making one device much stronger than the other moves the switching threshold toward that device’s rail: a strong PFET moves it up toward $V_{DD}$VDD​.

The two phases (§6): precharge while $\phi_2$ is high, access while $\phi_1$ is high.

The two phases (§6). Original figure ↑

The question. How does a column read its cell: what turns the word line on at the right time, what detects the falling bitline, and how long does the bitline take?

The read column

The read circuit (board, 22:16–24:31)

1. Precharge. Two PFETs, gates on $\bar\phi_2$ϕˉ​2​, pull bit and $\overline{\text{bit}}$ to $V_{DD}$ during $\phi_2$ϕ2​.
2. A clock-qualified word line. The row decoder’s output for this row is ANDed with $\phi_1$ before it drives the word line. “Clock qualification … basically it’s a glorified term for AND” (22:44). The decoder’s output may be valid (or still changing) during precharge; the AND keeps the word line down until the access phase.
3. A single-ended detector. An inverter hangs from $\overline{\text{bit}}$bit. It is skewed: its PFET “much stronger than the NFET … to move the switch point toward VDD” (23:44–24:31). A small sag on $\overline{\text{bit}}$ already flips it.
4. Its polarity. “The bit bar is actually flipped here”: the inverter on $\overline{\text{bit}}$ outputs the sense of the bit side. If $V_2$ holds 0, $\overline{\text{bit}}$ falls and the output goes to 1; if $V_2$ holds 1, $\overline{\text{bit}}$ stays high and the output stays 0.

The read column, redrawn from the board (Lecture18 @ 23:56). Precharge PFETs on $\bar\phi_2$ at the tops of bit and $\overline{\text{bit}}$bit; the word line driven by an AND of $\phi_1$ and the decoder’s row select $s_{row}$ (the clock qualification; $s_{row}$ is this guide’s label); one cell and “⋮” for the others; at the foot of $\overline{\text{bit}}$ a skewed inverter, $W_P \gg W_N$WN​, to the output.

The board (Lecture18 @ 23:56)

Lecture18 @ 23:56The two phases and the read column: precharge on φ̄2, the clock-qualified word line, and the skewed inverter on bit̄.

Fair copy of the board above (Lecture18 @ 23:56), mark for mark in its own layout, all in black: one violet pen wrote the board. “skewed inv” is copied as written so far; by 25:40 it reads “skewed inverter”, with “PFET” under it. The clocks’ last cycle, washed out by the lecturer’s face here, is read on 25:40. The board draws each precharge PFET as an S-shaped channel with a bubble on its gate bar, and the cell’s devices as bumps under T-shaped gates.

How long the bitline takes

The bitline is long and heavily loaded; the cell that discharges it is tiny. Treat the discharge as one gate stage added.

The bitline as a gate stage (derive)

1. The drive. The current flows through the access NFET and the pull-down NFET in series. Their equivalent width is $W_{eq} = W_aW_{pd}/(W_a + W_{pd})$Wpd​).
2. The normalized inverter. An inverter with this pull-down strength has input $3W_{eq}$3Weq​.
3. The load. The bitline’s capacitance, in µm of gate: $C_{BL}/C_g$CBL​/Cg​.
4. The delay. To $V_{DD}/2$VDD​/2: $t_{BL} = C_{BL}/(3W_{eq}C_g)$CBL​/(3Weq​Cg​), in $\tau_{inv}$τinv​.
5. A smaller swing. Near $V_{DD}$ the cell’s current is roughly constant, so the bitline falls roughly linearly, and the time is proportional to the swing: a detector that switches after $\Delta V$ needs $t_{BL}\,\Delta V/(V_{DD}/2)$tBL​ΔV/(VDD​/2).

The bitline's delayadded

$$\begin{gathered} t_{BL} \approx \frac{C_{BL}}{3\,W_{eq}\,C_g}\,\tau_{inv}, \qquad W_{eq} = \frac{W_aW_{pd}}{W_a + W_{pd}} \\ t(\Delta V) \approx t_{BL}\,\frac{\Delta V}{V_{DD}/2} \end{gathered}$$

Holds when: Chapter 8 §1's gain model; the access and pull-down NFETs in series discharge the bitline; delay to V_DD/2 in units of τ_inv; for a smaller swing ΔV, the cell's current taken as constant near V_DD

Derive both, from Chapter 8 §1 and the constant-current picture.

A worked example added (the example column, for example: $W_a = 0.3$ µm, $W_{pd} = 0.6$ µm, $C_{BL} = 120$ fF, $C_g = 2$ fF/µm).

The example column's read

1. Series width. $W_{eq} = 0.3 \times 0.6/0.9 = 0.2$ µm.
2. Normalized input. $3 \times 0.2 = 0.6$ µm.
3. Load. $120\ \text{fF} / (2\ \text{fF}/\mu\text{m}) = 60$ µm.
4. To $V_{DD}/2$VDD​/2. $t_{BL} = 60/0.6 = 100\,\tau_{inv}$100τinv​.
5. With the skewed inverter. If it switches at $0.8\,V_{DD}$0.8VDD​, the bitline needs to fall only $0.2\,V_{DD}$ instead of $0.5\,V_{DD}$0.5VDD​: $100 \times 0.2/0.5 = 40\,\tau_{inv}$40τinv​, 0.4 of the time.

A past final asks this estimate for its own cell and bitline (FN10-5b); the memory practice page (FM1) solves it.

Traps.

• The access device alone. The pull-down is in series with it; $W_{eq}$ is smaller than either width.
• The wrong swing. $t_{BL}$ is to $V_{DD}/2$VDD​/2; a detector that switches elsewhere needs the swing it actually waits for.
• The polarity. The detector sits on $\overline{\text{bit}}$bit; its output is the bit side’s value. Trace one stored value through before writing a waveform.

Check yourself Why does the AND of the word line with φ₁ matter even when the decoder's output is already correct?

The decoder’s output can be valid, or still changing, during precharge. Without the AND, the word line would rise while the precharge PFETs are still on: the cell would fight the precharge, and a changing address could open the wrong row. The AND confines the access to $\phi_1$ϕ1​.

Check yourself (Two steps.) For example: double the example column's rows, so the bitline is 240 fF. What are the bitline's time to V_DD/2 and the time with the skewed inverter at 0.8 V_DD?

Load: $240/2 = 120$ µm over the same $0.6$ µm normalized input: $t_{BL} =$ 200 $\tau_{inv}$τinv​. With the skewed inverter: $200 \times 0.4 =$ 80 $\tau_{inv}$τinv​. The delay grows linearly with the rows: the reason arrays are cut into banks (§13).

8. Writing a column: the stack, the one-device driver and φ₁-stable data

You need

The write fight (§2). The node that holds 1 is pulled down through the access NFET and every series device below it, against the cell’s PFET:

$$\begin{gathered} V_X \approx V_{DD}\,\frac{R_{down}}{R_{down} + R_{up}} \\ R_{down} = \frac{R}{W_a} + \sum_i \frac{R}{W_i}, \qquad R_{up} = \frac{2R}{W_p} . \end{gathered}$$

Each series device raises $V_X$ toward the threshold.

The write fight (§2). Original figure ↑

Latches (Chapter 13 §2). A latch clocked by $\phi_2$ is transparent while $\phi_2$ is high and holds while it is low, so its output cannot change during $\phi_1$ϕ1​.

The question. What pulls the bitline low for a write, gated so that it acts only during the access and only on the right side, and how many devices may it put in series with the access NFET?

The two-high stack

The write column (board, 25:03–27:40)

1. The column as for a read. Precharge PFETs on $\bar\phi_2$ϕˉ​2​; the word line from the AND of $\phi_1$ and the row’s decode; the read inverter on $\overline{\text{bit}}$bit.
2. A stack on each bitline. Two NFETs in series from the bitline to ground. The upper one’s gate comes from an AND of $\phi_1$ and write; the lower one’s gate is data on the bit side and $\overline{\text{data}}$ (data through an inverter) on the $\overline{\text{bit}}$ side.
3. Write = 0. Both upper NFETs are off: the column only reads.
4. Write = 1, during $\phi_1$ϕ1​. The upper NFETs are on, and data picks the side: data = 1 pulls bit low, data = 0 pulls $\overline{\text{bit}}$ low.

The polarity, traced board (the board’s wiring, as FN17-6 prints it). Data = 1 pulls bit low, so the cell’s bit-side node $V_1$ takes 0 and $V_2$ takes 1. A later read: $V_2 = 1$1, so $\overline{\text{bit}}$ stays high, and the read inverter on $\overline{\text{bit}}$ outputs 0. The column returns the complement of the data written. That is harmless (the next stage can invert, or the wiring can swap data and $\overline{\text{data}}$data, or the detector can sit on bit), but a waveform question built on this circuit expects it: data_in high, data_out low.

Fewer devices in series

The stack is two devices in series below the access NFET, and the column multiplexer (§9) adds a third. Each one raises $V_X$VX​. The lecture collapses each side to one NFET, and moves the logic into a gate that drives it board (27:41–29:45):

• bit’s NFET is driven by NOR($\bar\phi_1$ϕˉ​1​, $\overline{\text{write}}$write, $\overline{\text{data}}$data);
• $\overline{\text{bit}}$‘s NFET by NOR($\bar\phi_1$ϕˉ​1​, $\overline{\text{write}}$write, data).

The board draws each NOR as an AND with bubbled inputs. By De Morgan, a NOR of complements is the AND of the true signals:

The one-device driver's gateboard

$$\overline{\bar\phi_1 + \overline{\text{write}} + \overline{\text{data}}} = \phi_1 \cdot \text{write} \cdot \text{data}$$

Holds when: the board's NOR with inputs φ̄1, write-bar and data-bar (bit's driver); the bit-bar driver takes data in place of data-bar; De Morgan's law

Derive it in one line. The driver is on only when $\phi_1 = 1$1, write = 1 and data = 1: the stack’s function with one device in the bitline’s path. The NOR switches on $\phi_1$‘s rising edge, in parallel with the word line’s AND, as the stack’s AND($\phi_1$ϕ1​, write) did; it adds no gate to the clock path and removes a device from the bitline’s.

The write column, redrawn from the board (Lecture18 @ 27:40 and 31:37). (a) The stacks: precharge PFETs on $\bar\phi_2$ϕˉ​2​, the word line from an AND of $\phi_1$ and $s_{row}$srow​, one cell, and at the foot of each bitline two series NFETs to ground, the upper gates from an AND of $\phi_1$ and write, the lower gates data (bit side) and $\overline{\text{data}}$ ($\overline{\text{bit}}$bit side); the read inverter on $\overline{\text{bit}}$bit. (b) One device per side: bit’s NFET driven by NOR($\bar\phi_1$ϕˉ​1​, $\overline{\text{write}}$write, $\overline{\text{data}}$data), $\overline{\text{bit}}$‘s by NOR($\bar\phi_1$ϕˉ​1​, $\overline{\text{write}}$write, data) (the board’s bubbled-input ANDs, drawn as NORs). (c) The data comes from a latch clocked by $\phi_2$ϕ2​.

A worked example added (the example cell, for example: $W_p = 0.2$ µm, $W_a = 0.3$ µm, each write-path device 0.6 µm; $R_{up} = 2R/0.2 = 10R$10R, the access NFET $R/0.3 = 3.33R$3.33R, each 0.6 µm device $1.67R$1.67R).

The written node with each write path

1. Two-high stack. $R_{down} = 3.33R + 2 \times 1.67R = 6.67R$6.67R: $V_X = 6.67/16.67 = 0.40\,V_{DD}$0.40VDD​.
2. Stack plus a mux device (§9). $R_{down} = 3.33R + 3 \times 1.67R = 8.33R$8.33R: $V_X = 8.33/18.33 = 0.45\,V_{DD}$0.45VDD​: at or past the cell’s lowered threshold $V_M$VM​, so the write may fail.
3. One NOR-driven device. $R_{down} = 3.33R + 1.67R = 5R$5R: $V_X = 5/15 = 0.33\,V_{DD}$0.33VDD​.
4. One device plus a mux device. $R_{down} = 6.67R$6.67R: $V_X = 0.40\,V_{DD}$0.40VDD​, as good as the stack without a mux.

Removing one series device buys back exactly what the multiplexer costs.

φ₁-stable data

The data must not change while $\phi_1$ is high board (29:56–31:37: “data ⇒ $\phi_1$-stable”, boxed). If it changed during the access, the driver would switch sides halfway through a write, and the cell could be left with the wrong value or half-written. The board’s answer: take data from a latch clocked by $\phi_2$ (“D Q”, $\phi_2$ϕ2​). That latch changes only while $\phi_2$ is high, so its output is still throughout $\phi_1$ϕ1​: Chapter 13’s two-phase discipline.

The board (Lecture18 @ 31:37)

Lecture18 @ 31:37The write column with its stacks, the one-device drivers and their NORs, and data made φ1-stable by a φ2 latch.

Fair copy of the board above (Lecture18 @ 31:37), mark for mark in its own layout, all in black: one violet pen wrote the board, the ring on “data” and the loop round the write devices included. The one-device drivers and the boxed “$\phi_1$ϕ1​-stable”, behind the lecturer here, show through and need no restoring (the same on 31:02). The clocks keep their first cycle and a half from 23:56; the tails were wiped and redrawn short. The board draws the drivers’ NORs as ANDs with bubbled inputs (Section 8), and grounds as small triangles. The ring on “data” is drawn wider than the board’s, to hold the typeset word.

Traps.

• The polarity reversed. Data drives the bit side’s device in the board’s circuit; trace one value (data = 1 → bit low → $V_1 = 0$0) before drawing a waveform.
• Data from a $\phi_1$ latch. It changes during the access, exactly when it must be still.
• “The NOR slows the write.” It switches on $\phi_1$‘s rising edge, in parallel with the word line’s AND, as the stack’s AND($\phi_1$ϕ1​, write) did: it adds no gate to the clock path, and it takes a device out of the bitline’s.

Check yourself (Two steps.) Write = 1, data = 0, φ₁ = 1, with the board's one-device drivers. Which NFET conducts, which bitline falls, and what does the read inverter output on the next read of that cell?

bit’s NOR has inputs $\bar\phi_1 = 0$0, $\overline{\text{write}} = 0$0, $\overline{\text{data}} = 1$1: output 0, off. $\overline{\text{bit}}$bit’s NOR has inputs 0, 0, data = 0: output 1, so $\overline{\text{bit}}$‘s NFET conducts and $\overline{\text{bit}}$ falls. The cell takes $V_2 = 0$0, $V_1 = 1$1. On the next read, $V_2 = 0$ pulls $\overline{\text{bit}}$ down and the inverter on it outputs 1: the complement of data = 0.

Check yourself Why must the driver's NOR include φ̄₁, when the word line is already qualified by φ₁?

Without it the driver would pull its bitline low whenever write and data are set, including during the precharge phase: it would fight the precharge PFETs, burn current, and leave the bitline low when the next access began.

9. Column multiplexing: the circuit and its cost

You need

The address split (Chapter 18 §10 teaches it). A memory of $N_w$ words of $W$ bits built as $R$ rows by $C$ columns ($R\cdot C = N_w\cdot W$R⋅W) holds $C/W$ words on each row. Its address bits split as $\log_2 N_w = \log_2 R + \log_2 (C/W)$log2​(C/W): the row bits go to the row decoder, the column bits choose one of the $C/W$ words through a $C/W$C/W:1 column multiplexer. Chapter 18’s 1024 × 32 example built as 256 × 128 uses $8 + 2$ bits.

Pass transistors as a multiplexer (Chapter 10 §7). NFETs in series with each input, gated by one-hot select lines: exactly one select is high, and its input passes.

The write path’s divider (§8): every device in series with the access NFET raises $V_X$VX​.

The write column (§8). Original figure ↑

The question. Chapter 18 split the address and named the column multiplexer. What is it as a circuit, and what does it cost the column?

The column multiplexer (board, 31:55–37:18)

1. One bit of address. “One-bit of address → column multiplexers” (board). With 128 columns and one column bit, two columns share one set of read and write circuits, and the word is 64 bits (32:44–33:12). In Chapter 18’s terms, $C/W = 2$2.
2. The circuit. Two columns, each with its own precharge PFETs and cells. Below the cells, an NFET in series with each bitline: both of column 1’s are gated by col 1, both of column 2’s by col 2. Below them the two bit lines join into one node, and the two $\overline{\text{bit}}$ lines into another.
3. Shared circuits. One write device hangs from each joined node (§8’s one-device drivers), and the read inverter hangs from the joined $\overline{\text{bit}}$ node.
4. The selects. col 1 and col 2 are the decoded column address: a full decode (§11) of the column bits, so exactly one is high.
5. The second benefit (spoken, 49:56–51:24). The read and write circuits, and the sense amplifiers of §10, are much wider than a cell. With multiplexing they are shared among columns and need not fit in one column’s narrow pitch.
6. The cost. “It adds this another device … into the stack” (36:35): the mux NFET is in series with the access NFET and the write device.

A 2:1 column multiplexer, redrawn from the board (Lecture18 @ 37:18). Two columns (bit₁, $\overline{\text{bit}}_1$bit1​, bit₂, $\overline{\text{bit}}_2$bit2​), each with precharge PFETs on $\bar\phi_2$ and a cell. Below the cells, a series NFET on each bitline, gated col 1 (column 1) and col 2 (column 2). bit₁ and bit₂ join (bit₁’s wire hops over $\overline{\text{bit}}_1$bit1​, as on the board) and go to one write NFET, gate $w_{bit}$wbit​; $\overline{\text{bit}}_1$ and $\overline{\text{bit}}_2$ join and go to the other, gate $w_{\overline{bit}}$wbit​, with the read inverter on that shared node. The two write devices are §8’s one-device drivers.

The board (Lecture18 @ 37:18)

Lecture18 @ 37:18Column multiplexing: one address bit selects one of two columns for the shared read and write circuits.

Fair copy of the board above (Lecture18 @ 37:18), mark for mark in its own layout. Black is the violet pen: the write board at the left, as at 31:37 (the one-device drivers are wiped, and the left driver’s AND stays with its output cut short), the multiplexer’s four precharge PFETs with their $\bar\phi_2$ labels, and the rings round the four mux devices. Teal is the blue pen, the multiplexer itself: the bitlines and cells, the mux devices with col 1, col 1, col 2, col 2, the joined bitlines (column 1’s $\overline{\text{bit}}$ hops over the wire joining the two bits), the two write devices and the read inverter. The title, in the pale cream pen, is black. The write stacks’ middle, behind the papers in the lecturer’s hand here, is copied from 36:46. The right write device runs off the frame’s bottom edge.

What it costs added (§8’s divider, the example cell, for example: every write-path device 0.6 µm). With the two-high stack, the mux device takes $V_X$ from $0.40$ to $0.45\,V_{DD}$0.45VDD​. With the one-device driver, from $0.33$ to $0.40\,V_{DD}$0.40VDD​. That is why §8 removes a stack device before the multiplexer adds one.

A worked example. The board’s: 128 columns with one column bit give a 2:1 multiplexer and a 64-bit word. In Chapter 18’s terms, $\log_2(C/W) = \log_2(128/64) = 1$ column bit. The cost: one more series device in the write path, as above.

The split itself, with its worked examples and the past final’s FN10-10, is Chapter 18’s (§10); this section adds the circuit it selects.

Traps.

• “The mux’s cost is a bigger decoder.” It costs the write path a series device. A 4:1 mux is still one device per path, but its selects need a 2-to-4 decode.
• “The detector sees the full bitline through the mux.” Through an NFET the shared $\overline{\text{bit}}$ node charges only to $V_{DD} - V_T$ (an NFET pulling up, §3; the point of §10’s Check on the isolation devices), which can sit below §7’s switch point of $0.8\,V_{DD}$0.8VDD​: the skewed inverter would see every read as a fall. Behind an NFET mux the detector must switch below $V_{DD} - V_T$VT​, or the shared node needs its own precharge, or the read path goes through PFETs or transmission gates.
• col 1, col 2 as address bits. They are the decoded one-hot lines; $k$ column bits make $2^k$ of them.
• Column bits as $\log_2 C$log2​C. They are $\log_2 (C/W)$log2​(C/W): the multiplexer chooses words, not bits.

Check yourself 128 columns hold 16-bit words. What is the multiplexer's ratio, how many column bits are there, and how many select lines must the column decoder drive?

$C/W = 128/16 = 8$8: an 8:1 multiplexer, $\log_2 8 =$ 3 column bits, decoded into 8 one-hot select lines.

Check yourself (Two steps.) For example: the example cell with the one-device driver (0.6 µm). How much does V_X rise when a 0.6 µm mux device is added, and how wide must the mux device be to keep V_X at or below 0.35 V_DD?

Without the mux, $V_X = 0.33\,V_{DD}$0.33VDD​; with it, 0.40 $V_{DD}$VDD​. For $V_X \le 0.35$0.35: $R_{down} \le (0.35/0.65)\,R_{up} = 0.538 \times 10R = 5.385R$5.385R. The access and driver take $3.33R + 1.67R = 5R$5R, leaving $0.385R$ for the mux device: $R/W_m \le 0.385R$0.385R, so $W_m \ge$ 2.6 µm, more than four times the driver’s width, and larger than the whole cell: the price of a series device.

10. Sense amplifiers: differential, regenerative, and their offset

You need

The cross-coupled pair (Chapter 13 §5). Two inverters in a loop have two stable states and a metastable one between them. Started slightly off balance, the loop runs away to the nearer stable state, faster the farther off balance it starts.

The bitline’s delay (§7). The cell discharges the bitline as one stage: $t_{BL} = C_{BL}/(3W_{eq}C_g)$ to $V_{DD}/2$VDD​/2; for a swing $\Delta V$ΔV, $t(\Delta V) \approx t_{BL}\,\Delta V/(V_{DD}/2)$ (constant current near $V_{DD}$VDD​). The example column: $t_{BL} = 100\,\tau_{inv}$100τinv​.

Switching energy (Chapter 6 §6). Restoring a node of capacitance $C$ by $\Delta V$ draws charge $C\,\Delta V$ from the supply, so energy $C\,V_{DD}\,\Delta V$CVDD​ΔV.

The single-ended read column (§7). Original figure ↑

The question. The bitline falls slowly. Can the column decide which way the cell leans long before the bitline has fallen far, and what limits how early?

The clocked sense amplifier (board, 37:23–48:45)

1. Differential. A sense amplifier compares bit with $\overline{\text{bit}}$ instead of comparing one line with a threshold. Noise that moves both lines together (coupling, supply bounce) cancels in the difference (37:23–39:20).
2. The circuit. Below the cells, a PFET in series with each bitline, gates on $\bar\phi_1$ϕˉ​1​: the isolation devices (“isolate transistors”). Below them, two cross-coupled inverters with sense nodes $s$ and $\bar s$sˉ, whose NFETs share a source; a tail NFET from that source to ground, gate also on $\bar\phi_1$ (40:09–41:10).
3. Don’t wait. “Waiting for this to get pulled all the way to ground is going to take a long time” (42:05). The amplifier needs only a small difference.
4. During $\phi_1$ ($\bar\phi_1 = 0$ϕˉ​1​=0). The isolation PFETs are on and the tail is off: the sense nodes follow the bitlines, and the cell’s small difference $\Delta V$ appears between $s$ and $\bar s$sˉ.
5. At the end of $\phi_1$ ($\bar\phi_1 = 1$ϕˉ​1​=1). The isolation PFETs turn off, cutting the sense nodes from the bitlines (which precharge once $\phi_2$ rises), and the tail turns on. The pair, started off balance by $\Delta V$ΔV, regenerates to full rail: “that can happen very fast. It has nothing to do with gain bandwidth product” (46:30).
6. The payoff. The bitlines swing only $\Delta V$ΔV: a shorter access, and less charge to restore.
7. The catch: offset. Mismatch between the pair’s devices (§5) makes the amplifier lean one way by itself, an input offset voltage. “These offsets can be quite large. They can be 50 to 100 millivolts” (48:15). The swing must exceed it, which erodes the advantage, and many SRAMs read single-ended again (47:37–48:45).

The clocked sense amplifier, redrawn from the board (Lecture18 @ 44:13; labels from 46:37 and 48:37). A column with precharge PFETs on $\bar\phi_2$ϕˉ​2​, the word line and a cell. Below it, an isolation PFET in series with each bitline, gates on one $\bar\phi_1$ wire; the sense nodes $s$ and $\bar s$ (this guide’s names for the board’s x marks); two cross-coupled inverters between them, their NFETs meeting at a common node; a tail NFET from that node to ground, gate on $\bar\phi_1$ϕˉ​1​.

The sense amplifier’s sequence added (from the board’s description, 43:28–46:57; a sketch). Rows $\phi_1$ϕ1​, $\bar\phi_1$ϕˉ​1​, WL, the bitlines and the sense nodes. While $\phi_1$ is high, bit sags by $\Delta V$ and the sense nodes follow. When $\phi_1$ falls, the bitlines are cut off and precharge, and the sense nodes regenerate: $s$ falls to 0 while $\bar s$ holds $V_{DD}$VDD​. The dotted line at $V_{DD} - V_{os}$ marks the swing the sag must pass before the amplifier fires.

Bitline restore energyadded

$$E \approx C_{BL}\,V_{DD}\,\Delta V$$

Holds when: one bitline of capacitance C_BL restored from V_DD − ΔV to V_DD per access; Chapter 6's charge argument

Derive it from Chapter 6: the precharge draws $C_{BL}\,\Delta V$ of charge from $V_{DD}$VDD​.

A worked example added (the example column, for example: $t_{BL} = 100\,\tau_{inv}$100τinv​, $C_{BL} = 120$ fF, $V_{DD} = 1.0$ V).

Sensing 100 mV

1. Time. The swing must exceed the offset; take $\Delta V = 100$ mV, the board’s upper figure. $t = 100 \times 0.1/0.5 = 20\,\tau_{inv}$20τinv​, against 40 for the skewed inverter (§7) and 100 to $V_{DD}/2$VDD​/2. At 50 mV it would be $10\,\tau_{inv}$10τinv​.
2. Energy. $E = 120\ \text{fF} \times 1.0\ \text{V} \times 0.1\ \text{V} = 12$ fJ per bitline per access, against 60 fJ for a swing of $V_{DD}/2$VDD​/2.

The board (Lecture18 @ 48:37)

Lecture18 @ 48:37The clocked sense amplifier, its two clock states, and the input offset of 50–100 mV.

Fair copy of the board above (Lecture18 @ 48:37), mark for mark in its own layout. Black is the pale cream pen’s read column, drawn earlier: the $\bar\phi_2$ precharge PFETs, “wordline”, the cell and the bitlines; “Lecture 18” is violet. Teal is the cyan pen, which adds the sense amplifier under the column and the notes beside it: the $\bar\phi_1$ wire to the two isolation PFETs, the x marks on the sense nodes, the cross-coupled pair, the ringed tail NFET, the arrow on $\overline{\text{bit}}$bit, the two clock states, the $\phi_1$ and $\phi_2$ waveforms with long vertical marks at the edges of the $\phi_1$ pulse, “input offset voltage” and “50∼100 mV”. The board draws each transistor as a channel bump beside a gate bar, a PFET with a small bubble, and writes the second $\bar\phi_1$ with a capital $\Phi$Φ. Nothing is restored: the lecturer’s hand washes out the right isolation device and the start of “isolate transistors”, and 47:52 has the same strokes clear; only “50∼100 mV” is new since then.

Traps.

• Firing before $\Delta V$ exceeds the offset. The amplifier resolves its own bias, not the cell’s data: a wrong read.
• Isolation devices left on during regeneration. The pair would have to swing the whole bitline, slowly, and fight the precharge.
• “A sense amplifier is a linear amplifier.” Its speed comes from positive feedback (regeneration), not from gain and bandwidth.

Check yourself Why are the isolation devices PFETs rather than NFETs?

They must pass the bitlines’ levels near $V_{DD}$ to the sense nodes. A PFET passes a high level fully; an NFET would stop a threshold below $V_{DD}$ (Chapter 10’s degraded high), right where the small signal lives.

Check yourself (Two steps.) For example: with a 75 mV offset on the example column, what is the earliest the amplifier may fire, and what restore energy does each bitline then cost?

Time: $100 \times 0.075/0.5 =$ 15 $\tau_{inv}$ of bitline sag. Energy: $120\ \text{fF} \times 1.0\ \text{V} \times 0.075\ \text{V} =$ 9 fJ.

11. Decoders: AND gates, predecoding and clock qualification

You need

AND from NAND and NOR added (De Morgan, background). $\overline{\bar a + \bar b} = ab$ab: a NOR of complements is an AND. So a NOR of NAND outputs is the AND of all their inputs: $\overline{\overline{ab} + \overline{cd}} = abcd$abcd.

Pseudo-NMOS (Chapter 10 §10). An always-on PFET (gate grounded) pulls a line up; NFETs pull it down. The line is low whenever any NFET on it conducts: a NOR. Chapter 18’s PLA planes are built this way.

The question. How does the row decoder raise exactly one word line out of $2^n$2n, and how is it built so that it is not one huge, slow gate per row?

Decoders (board, 51:24–53:38)

1. One AND per row. “Decoders are nothing but a glorified set of AND gates” (51:24). For 3 bits, eight 3-input ANDs; each takes every address bit, true or complemented, so that exactly one AND is high for each address. The board bubbles the inputs in a binary count down the column.
2. Clock qualification. Each AND’s output is ANDed with $\phi_1$ before it becomes a word line (§7).
3. Two levels. A wide AND is slow, so split it. A predecoder ANDs small groups of address bits; the decoder ANDs one predecoded line from each group (53:04). In CMOS the natural form is NAND then NOR: the NOR of NAND outputs is the AND of everything (the board’s “precoder” and “decoder”).

A 3-bit decoder, redrawn from the board (Lecture18 @ 55:51). Eight 3-input ANDs, inputs $a_0$a0​, $a_1$a1​, $a_2$ with bubbles in a binary count; each output ANDed with $\phi_1$ (the board draws two of these; all eight are drawn here) into a word line labelled with its product, from $a_0a_1a_2$ to $\bar a_0\bar a_1\bar a_2$aˉ0​aˉ1​aˉ2​.

Two-level decoding, redrawn from the board (Lecture18 @ 55:51). (a) Two 2-input ANDs (the predecoder) into a 2-input AND (the decoder). (b) The CMOS form: two NANDs into a NOR. The vertical line separates the predecoder from the decoder.

Counting a predecoded decoder

An 8-bit decoder with 2-bit predecoding (added)

1. Groups. Split the 8 address bits into $8/2 = 4$ groups of 2.
2. Lines per group. Each group of 2 bits is fully decoded into $2^2 = 4$ one-hot lines: $4 \times 4 = 16$ predecoded lines in all.
3. Decoders. Each of the $2^8 = 256$ word lines needs one line from each group: a 4-input gate.
4. Fan-out. A given line of one group is used by every row whose bits in that group match it: $256/4 = 64$ decoders.

Predecoding n bits in groups of kadded

$$\begin{gathered} \text{lines} = \frac{n}{k}\,2^k, \qquad \text{decoder inputs} = \frac{n}{k} \\ \text{fan-out of a line} = \frac{2^n}{2^k} = 2^{n-k} \end{gathered}$$

Holds when: n address bits split into n/k groups of k bits, each group fully decoded; every word-line gate takes one line per group

Derive the counts each time from the picture: groups, lines per group, one line per group per decoder.

A decoder driving a ROM

The same full decoder, driving a grid of pull-down devices on pseudo-NMOS columns, is a ROM added (a bridge to a past final, FN12-10d). Each address raises one row; a device at a crossing pulls its column low when its row is selected; a column with no device on the selected row stays high. Read it row by row.

A small ROM added: a 2-to-4 decoder (four 2-input ANDs on $a_1$a1​, $a_0$a0​) drives four rows. Two pseudo-NMOS columns $y_1$y1​, $y_2$ each have a PFET with its gate grounded at the top. NFETs from a column to ground, gated by a row, sit at row $\bar a_1\bar a_0$–$y_1$y1​, row $a_1\bar a_0$–$y_1$y1​, row $a_1\bar a_0$–$y_2$ and row $a_1a_0$–$y_2$y2​; row $\bar a_1a_0$ has none.

Reading the ROM, row by row (added)

1. $a_1a_0 = 00$00. Row $\bar a_1\bar a_0$ is selected; it has a device on $y_1$ only: $y_1y_2 = 01$01.
2. $a_1a_0 = 01$01. Row $\bar a_1a_0$ has no device: $y_1y_2 = 11$11.
3. $a_1a_0 = 10$10. Row $a_1\bar a_0$ has devices on both: $y_1y_2 = 00$00.
4. $a_1a_0 = 11$11. Row $a_1a_0$ has a device on $y_2$y2​: $y_1y_2 = 10$10.

The board (Lecture18 @ 55:51)

Lecture18 @ 55:51Decoders: eight ANDs for 3 bits, clock-qualified by φ1, and two-level decoding as AND–AND and NAND–NOR.

Fair copy of the board above (Lecture18 @ 55:51), mark for mark in its own layout. Black is the violet pen: “Lecture 18”, “3 bit” with its ring, $a_0a_1a_2$a0​a1​a2​, and the decoders: eight three-input ANDs with bubbles on the complemented inputs, the first two ANDed with $\phi_1$ into long word lines, two NANDs into an AND with bubbled inputs, and two ANDs into an AND, each pair split by a line into “precoder” and “decoder”. Teal is the cyan pen: the titles “column”, “Decoder” and “row”, and at the left what remains of the sense-amplifier board as it is wiped, with “⇒ Column multiplexing”. The wipe has taken the read column, “isolate transistors” and the clock states; the copy keeps what remains, down to the letters left of “input offset voltage” and “50∼100 mV” and a few short pieces of the column. The right isolation device’s gate and the right PFET’s top bar show through the lecturer’s hand and are copied as they stand at 55:08. “precoder” is the board’s shortening of “predecoder”, the word the lecture uses. The tiny input labels the board writes beside the first two ANDs are left out: typeset, they would overlap.

Traps.

• The fan-out of a predecoded line as all $2^n$ decoders. Each decoder takes one line per group, so a line feeds only the rows that match it: $2^{n-k}$2n−k.
• Leaving out the clock qualification. While the address changes, two decoder outputs can be high for a moment; without $\phi_1$ two word lines could rise together.
• Reading a ROM device as a 1. A device pulls its column low.

Check yourself A 6-bit decoder uses 3-bit predecoding. How many predecoded lines are there, how many inputs does each word-line gate have, and how many gates does each line feed?

$6/3 = 2$ groups of $2^3 = 8$ lines: 16 lines. One line per group: 2 inputs. Fan-out $2^{6-3} =$ 8.

Check yourself (Two steps.) In the ROM figure, which address gives an all-ones output word, and why? Which gives all zeros?

Address 01: its row $\bar a_1a_0$ has no device, so nothing pulls either column low and both PFETs hold them high. All zeros: address 10, whose row has a device on both columns.

12. The race-based NOR

You need

Precharge and evaluate; the race (Chapter 11 §4–§5). A dynamic gate’s node is precharged high while its clock is low and can only fall while its clock is high (its foot NFET on). If its output drives an NFET of a second dynamic gate that evaluates at the same time, the second gate sees a high input at the start of every evaluation, even when the first node is about to fall: it can discharge by mistake. That is the race; domino logic puts an inverter between the stages to avoid it.

The race between two dynamic gates (Chapter 11, Lecture11 @ 30:38). Original figure ↗

The half latch (Chapter 11 §8). A weak PFET from $V_{DD}$ to a dynamic node, gated by the inverter after it, holds a high node high against leakage and noise.

The two phases with a gap (§6). Precharge while $\phi_2$ is high, access while $\phi_1$ is high, and a non-overlap time $t_{NO}$ from $\phi_2$ falling to $\phi_1$ rising.

The two phases with the gap $t_{NO}$ (§6). Original figure ↑

A dynamic stage’s gain (Chapter 12 §2). On its evaluation edge a footed stage pulls down through its input NFET and its foot in series: gain $= C_{out}/(3W_{eq})$ with $W_{eq} = 1/(1/W_{in} + 1/W_{foot})$1/Wfoot​). An inverter’s rising edge is driven by its PFET, $W_p$Wp​, as strong as an NFET of $W_p/2$Wp​/2: gain $= C_{out}/(1.5W_p)$Cout​/(1.5Wp​).

The question. The word line must rise for one row only, and only in the access phase. Can the decoder’s last gate and the clock qualification be one fast dynamic gate pair, and what does the clock have to do to make that safe?

The circuit

The race-based NOR (board, 56:10–57:02)

1. Stage 1: the decoder’s NOR. A dynamic NOR of the row’s predecoded lines (two on the board): a PFET from $V_{DD}$ to node $X$X, gate $\bar\phi_2$ϕˉ​2​, so $X$ precharges while $\phi_2$ is high; the input NFETs in parallel; a foot NFET, gate $\bar\phi_2$ϕˉ​2​, so the gate evaluates as soon as $\phi_2$ falls. (“This is phi one bar … excuse me, phi two bar”, 56:10.) $X$ stays high only on the selected row, the one whose inputs are all low; on every other row some input is high and $X$ falls.
2. Stage 2: the clock qualification. A second dynamic stage: a PFET from $V_{DD}$ to node $Y$Y, gate $\phi_1$ (precharge while $\phi_1$ is low); an NFET gated by $X$X; a foot NFET gated by $\phi_1$ϕ1​, which the board rings: “clock qualification”. $Y$ falls only if $X$ is high while $\phi_1$ is high.
3. The word line. $Y$ drives an inverter whose output is the word line, with a half latch (a PFET from $V_{DD}$ to $Y$Y, gate on the word line) to hold $Y$ high on the unselected rows.
4. The board’s stage-2 device. The board draws stage 2’s top device without a bubble. It must be a PFET: an NFET there would conduct together with the $\phi_1$ foot and short the supply to ground. The redraw draws the bubble.

The race-based NOR, redrawn from the board (Lecture18 @ 58:46; stage 1 as uncovered at 56:46). Stage 1: a dynamic NOR of the predecoded lines $\ell_1$ℓ1​, $\ell_2$ℓ2​, precharged and footed on $\bar\phi_2$ϕˉ​2​, node $X$X. Stage 2: precharged by a PFET on $\phi_1$ (bubble drawn; the board omits it), an NFET gated by $X$X, and the $\phi_1$ foot, the clock qualification; node $Y$Y. An inverter from $Y$ drives the word line WL, with a half-latch PFET back to $Y$Y. The labels $\ell_1$ℓ1​, $\ell_2$ℓ2​, $X$ and $Y$ are this guide’s.

The board (Lecture18 @ 58:46)

Lecture18 @ 58:46The race-based NOR: the decoder's dynamic NOR on φ̄2, and a second stage footed by φ1, the clock qualification.

Fair copy of the board above (Lecture18 @ 58:46), mark for mark in its own layout, on the 55:51 copy’s coordinates; its decoder half is that copy’s, unchanged. Teal is the cyan pen: “race-based NOR” and its circuit, and the titles “column”, “Decoder” and “row”. Black is the violet pen’s decoders and “Lecture 18”, and three short pieces of the wiped read column. Stage 1: a PFET on $\bar\phi_2$ (its bubble is the small o after the label), two input NFETs in parallel and a foot on $\bar\phi_2$ϕˉ​2​. Stage 2: the device on $\phi_1$ is drawn without a bubble, as on the board; it is a PFET, since an NFET there would conduct with the foot and short the rails. Its NFET takes stage 1’s node, and its foot on $\phi_1$ is ringed: “clock qualification”. The node drives an inverter to “wordline”, with a half-latch PFET whose gate is the inverter’s output. Nothing is restored: the lecturer stands in front of the half latch and the inverter, which show through, and 58:01 has the same strokes. The tiny input labels beside the first two ANDs are left out, as in the 55:51 copy.

The race, and the clock that removes it

Stage 1’s node drives stage 2’s NFET directly: a precharged-high node into a dynamic gate, Chapter 11’s race. “This is often called a race-based NOR because there’s an inherent race condition here” (57:49).

Edge by edge (board 57:19–57:49; the timing is added)

1. Precharge ($\phi_2$ϕ2​ high). $X$ is high on every row; $Y$ is high (its PFET is on while $\phi_1$ is low); every word line is low.
2. $\phi_2$ falls. Stage 1’s foot turns on. On the unselected rows $X$ starts to fall, taking a time $t_{eval}$teval​. On the selected row $X$ stays high.
3. $\phi_1$ rises, $t_{NO}$ later. Stage 2’s foot turns on. On the selected row $X$ is high, so $Y$ falls and the word line rises: the access begins.
4. The race. On an unselected row, if $X$ is still high when $\phi_1$ rises, stage 2 sees a high input and starts to discharge $Y$Y: a glitch on a word line that must stay low, and two rows accessed at once. The fix is the clock: “I can twiddle the phi one, phi two bar relative to the phi one to ensure that this guy evaluates before this guy evaluates … I get rid of the race condition” (57:19–57:49). Make $t_{NO}$ longer than stage 1’s evaluation.
5. $\phi_1$ falls. Stage 2’s PFET turns on, $Y$ precharges high and the word line falls (on the board’s circuit).

The race-based NOR’s timing added (a sketch, from the board’s spoken sequence, 57:19–57:49). $\phi_2$ falls at $t_1$ and $\phi_1$ rises $t_{NO}$ later. $X$ on an unselected row falls within $t_{eval}$teval​, shorter than $t_{NO}$tNO​; on the selected row (dashed) it stays high. $Y$ on the selected row falls just after $\phi_1$ rises and is restored when $\phi_1$ falls; the word line follows, inverted. On an unselected row $Y$ stays high; the dotted dip marked ✗ is what would happen if $X$ were still high when $\phi_1$ rose.

The race-based NOR's clock conditionadded

$$t_{NO} \;\ge\; \sum t_{eval}$$

Holds when: the sum runs over the stages that evaluate between φ2 falling and φ1 rising; in the board's circuit everything between the φ2 falling edge and stage 2 evaluates in the gap (stage 1, and any domino predecoder clocked on φ̄2 in front of it); the lecture states the condition in words (57:19–57:49)

Derive it from the edge-by-edge picture: an unselected row’s $X$ must be low before stage 2’s foot opens. Precharging stage 1 on $\bar\phi_2$ rather than $\phi_1$ (§6) is what makes the gap available.

Two remarks. First, a variant: if stage 2’s PFET is gated by the $\bar\phi_2$ line instead of $\phi_1$ (as on the 2017 final’s circuit, FN17-6), $Y$ is precharged only while $\phi_2$ is high, so the selected word line stays high from $\phi_1$ rising until $\phi_2$ rises, through the second gap. Both versions work; the board’s word line falls with $\phi_1$ϕ1​. Second, the clocked design is not the only one: SRAMs can be self-timed with a replica column that triggers the end of the access, “but they’re far more complex” (54:20–55:21; Chapter 18’s replica rows are the same idea).

The decode path’s delay

The critical edges run through the predecoder and the race NOR on the unselected rows (they must finish before $\phi_1$ϕ1​), and through stage 2 and the word-line driver on the selected row (after $\phi_1$ϕ1​). Add them as Chapter 8 does, one gain per stage.

A decode path for a 64-row array added (for example; the shape of the course’s design-project decoder with this guide’s sizes, in µm). I: a domino NOR2 predecoder (precharge PFET 4 on $\bar\phi_2$ϕˉ​2​, inputs and foot 8). II: its inverter (PFET 30, NFET 5), each output feeding 16 race NORs. III: the race NOR3 (precharge PFET 2 on $\bar\phi_2$ϕˉ​2​, inputs and foot 3). IV: stage 2 (PFET 6 on $\phi_1$ϕ1​, NFET 12, foot 12 on $\phi_1$ϕ1​). V: the word-line driver (PFET 40, NFET 6) into $C_{WL}$CWL​. Under each stage, its gain: 2.92, 1.07, 2.67, 2.56, 0.81. The dashed line marks the $\phi_1$ edge: stages I–III before it, IV–V after.

A worked example added (for example: the path in the figure, $C_g = 2$ fF/µm; the word line has 20 fF of wire and 64 cells with 0.3 µm access devices).

The example decode path, stage by stage

1. I, the predecoder falls. Drive: input 8 in series with foot 8, $W_{eq} = 4$4, normalized input 12. Load: the inverter, $30 + 5 = 35$35. Gain $35/12 = 2.92$2.92.
2. II, the predecoded line rises. Driven by its PFET of 30, normalized input $1.5 \times 30 = 45$45. Load: 16 race NOR inputs of 3, $48$48. Gain $48/45 = 1.07$1.07.
3. III, the unselected race NORs fall. Input 3 in series with foot 3, $W_{eq} = 1.5$1.5, normalized input 4.5. Load: stage 2’s NFET, 12. Gain $12/4.5 = 2.67$2.67.
4. IV, stage 2 falls on the selected row. 12 in series with 12, $W_{eq} = 6$6, normalized input 18. Load: the driver, $40 + 6 = 46$46. Gain $46/18 = 2.56$2.56.
5. V, the word line rises. The word line’s load: two access gates per cell, $C_{WL} = 20 + 64 \times 2 \times 0.3 \times 2 = 96.8$ fF, which is 48.4 µm. Driven by a PFET of 40, normalized input 60. Gain $48.4/60 = 0.81$0.81.
6. Add. $2.92 + 1.07 + 2.67 + 2.56 + 0.81 = 10.0\,\tau_{inv}$10.0τinv​. Before $\phi_1$ (stages I–III, the minimum $t_{NO}$tNO​): $6.65\,\tau_{inv}$6.65τinv​. After $\phi_1$ (IV–V): $3.36\,\tau_{inv}$3.36τinv​.

The word line's loadadded

$$C_{WL} = C_{wire} + N_{cols}\cdot 2\,W_a\,C_g$$

Holds when: a 6T cell puts both access NFETs' gates (width W_a each) on its word line; N_cols cells per row; C_g per µm

Derive it from the cell: two access gates per cell. Memorize the factor of 2.

On a past final (FN10-5a). The 2010 final asks for this kind of path, with its own sizes, for a word line of 256 cells with 1 µm access transistors and 100 fF of wire. Its answer key writes the word-line load as “100fF + 256(2fF)”, one access device per cell (612 fF). A 6T cell puts two access gates on the word line: $100 + 256 \times 2 \times 1 \times 2 = 1124$ fF. Driven by the paper’s 100 µm PFET, the last stage’s gain is $562/150 = 3.75$3.75, not the key’s 2.04, and the path comes to $21.57\,\tau_1$21.57τ1​, not $19.86\,\tau_1$19.86τ1​. The memory practice page (FM1) solves the question.

On a past final (FN17-6). The 2017 final prints a four-row version of this decoder with one column. Its scan hides the bars on $x_1$ in the W0 and W2 decoders, under their drain wires. Read W0 = NOR($\bar x_0$xˉ0​, $\bar x_1$xˉ1​), W1 = NOR($\bar x_0$xˉ0​, $x_1$x1​), W2 = NOR($x_0$x0​, $\bar x_1$xˉ1​) and W3 = NOR($x_0$x0​, $x_1$x1​). W1’s and W3’s labels are clear, and with them this is the only reading in which every address selects exactly one row. FM1 traces the waveforms.

Traps.

• One access device per cell on the word line. The example path would then see $20 + 64 \times 0.3 \times 2 = 58.4$ fF and a last-stage gain of 0.49 instead of 0.81: the 2010 key’s slip.
• Adding the stages of different rows as if they were one gate. The path mixes edges: the unselected rows’ race NORs before $\phi_1$ϕ1​, the selected row’s stage 2 and driver after it. Each stage’s critical edge is the one that must finish for the access to work.
• Stage 1 precharged on $\phi_1$ϕ1​. Then it could evaluate only from $\phi_1$ rising, together with stage 2: no gap to win the race.

Check yourself What goes wrong on an unselected row if t_NO = 0?

Stage 2’s foot opens while that row’s $X$ is still high, so $Y$ starts to discharge before $X$ falls: the unselected word line glitches up, and two rows may be accessed at once, which corrupts a read and can write the wrong cell.

Check yourself (Two steps.) For example: the array of the worked example grows to 128 columns (64 rows still). What are the new word-line load, the last stage's gain, the path's total, and the minimum t_NO?

Load: $20 + 128 \times 2 \times 0.3 \times 2 =$ 173.6 fF, 86.8 µm. Gain: $86.8/60 =$ 1.45. Total: $6.65 + 2.56 + 1.45 \approx$ 10.65 $\tau_{inv}$ (summed from the unrounded gains; the rounded terms add to 10.66). The minimum $t_{NO}$ is unchanged, 6.65 $\tau_{inv}$τinv​: stages I–III do not see the word line.

Check yourself In the variant whose stage-2 PFET is gated by φ̄₂, when does the selected word line fall?

When $\phi_2$ rises: only then does $\bar\phi_2$ fall and turn the PFET on, restoring $Y$ high. Through the gap after $\phi_1$ falls, $Y$ floats low and the word line stays high.

13. Putting it together: the access time

You need

The bitline (§7): $t_{BL} = C_{BL}/(3W_{eq}C_g)$ to $V_{DD}/2$VDD​/2, $W_{eq}$ the access and pull-down NFETs in series; a smaller swing $\Delta V$ takes $t_{BL}\,\Delta V/(V_{DD}/2)$tBL​ΔV/(VDD​/2). The example column: 100 $\tau_{inv}$ to $V_{DD}/2$VDD​/2, 40 with a skewed inverter at $0.8\,V_{DD}$0.8VDD​.

Sensing (§10): a sense amplifier fires once the swing exceeds its offset, 50–100 mV; 20 $\tau_{inv}$ at 100 mV on the example column.

The sense amplifier (§10). Original figure ↑

The decode path (§12): one gain per stage, added; the example path is 10.0 $\tau_{inv}$τinv​.

The race-based NOR (§12). Original figure ↑

The question added. How long is one read, from the address to the data, and does it fit in a processor’s cycle?

The access time of the example array (added)

1. Add the parts. A read is the decode path, then the bitline’s swing, then the detector. With the skewed inverter: $10.0 + 40.0 = 50.0\,\tau_{inv}$50.0τinv​. With a sense amplifier at 100 mV: $10.0 + 20.0 = 30.0\,\tau_{inv}$ (the amplifier’s own regeneration, a few $\tau_{inv}$τinv​, is left out).
2. Convert. The course’s finals take FO4 ≈ 3 $\tau_{inv}$ (FN10 states it). Single-ended: $50.0/3 = 16.7$ FO4. Sensed: $30.0/3 = 10.0$ FO4.
3. Against a cycle. A processor cycle of 12–15 FO4 is 36–45 $\tau_{inv}$τinv​. The single-ended array needs more than a cycle; the sensed one fits.
4. The bitline dominates. In both, the bitline is two to four times the decode: optimize it first.

The example array’s access time added, computed from §7, §10 and §12 (for example). Two bars on one axis in $\tau_{inv}$τinv​: SE, single-ended with the skewed inverter: decode 10.0 (hatched) and bitline 40.0, total 50.0; SA, with a sense amplifier at 100 mV: decode 10.0 and bitline 20.0, total 30.0. Dotted lines at 36 and 45 $\tau_{inv}$ mark cycles of 12 and 15 FO4 at 3 $\tau_{inv}$ per FO4.

The access timeadded

$$t_{access} \approx t_{decode} + t_{BL}(\Delta V) + t_{sense}, \qquad \text{FO4} \approx 3\,\tau_{inv}$$

Holds when: a read: decode path, then the bitline's swing to the detector, then the detector; FO4 ≈ 3 τ_inv is FN10's convention

Derive it by adding the parts; memorize that the bitline usually dominates.

The remedies, each from this chapter or the last:

• Sense a small swing (§10): the bitline term falls in proportion to $\Delta V$ΔV.
• Shorter bitlines: fewer rows per bank (Chapter 18’s organization); the bitline term falls in proportion to the rows.
• Self-timing (§12): end the access when a replica column says the data is ready, not at a fixed clock edge.
• Pipelining (Chapter 14): spread the access over two cycles, with the decode in one and the bitline in the next.

Traps.

• Optimizing the decoder first. In these numbers the bitline is the larger term.
• Mixing FO4 conventions. State the conversion you use; FN10 gives FO4 ≈ 3 $\tau_1$τ1​.

Check yourself (Two steps.) For example: halve the example column's rows, so its bitline is 60 fF. What is the new single-ended access time, in τ_inv and in FO4?

Bitline to $V_{DD}/2$VDD​/2: $(60/2)/0.6 = 50\,\tau_{inv}$50τinv​; with the skewed inverter, $50 \times 0.4 = 20\,\tau_{inv}$20τinv​. Access: $10.0 + 20.0 =$ 30.0 $\tau_{inv}$τinv​, $30.0/3 =$ 10.0 FO4: halving the rows does what the sense amplifier did. (The decode loses a predecode bit too, which this estimate ignores.)

Check yourself Which single change to the example array helps the access time most: halving the decode path's delay, or sensing 50 mV instead of 100 mV?

Halving the decode saves $5.0\,\tau_{inv}$5.0τinv​. Sensing 50 mV saves $20.0 - 10.0 = 10.0\,\tau_{inv}$ on the sensed array: the bitline term is the larger lever.

On the exam

Three past finals test this chapter, about 57 points in all. The memory practice page (FM1) solves them; the 2010 and 2017 decoders are the course’s design-project decoder of §12.

Part	Points	What it asks	Sections
FN10-5a	10	the decode path’s delay through a domino predecoder and a race-based NOR, in $\tau_1$ (the key undercounts the word line: §12)	§12, §11
FN10-5b	10	the bitline’s delay to $V_{DD}/2$ through the cell’s two NFETs	§7
FN10-5c	6	the access time in FO4, why it is a problem in a 12–15 FO4 cycle, and one remedy	§13, §10
FN10-10b	6	the column-multiplexing bits for a 4k × 16 memory built as 256 × 256	Chapter 18 §10; the multiplexer it selects, §9
FN17-6a	about 8	the decoder’s and the column’s waveforms over write and read cycles	§12, §8, §7
FN17-6b	8	the clock condition that removes the race	§12
FN12-10d	9	a ROM: a full decoder into pseudo-NMOS columns, read row by row	§11

At the finals’ pace of 0.7–0.9 minutes a point, FN10-5 is an 18–23 minute question.

Memorize.

• The cell’s strength order, pull-down > access > PFET, and both ratios with their reasons: access about 3× the PFET’s strength (1.5× its width, the PFET half as strong per width); pull-down 1.5–2× the access device.
• The read and write sequences: precharge both bitlines, raise the word line, then one bitline falls (read) or is pulled low (write).
• The butterfly: read lifts both lows and shrinks both lobes; a write caps one side and closes the old state’s lobe. The static noise margin is the side of the largest square in the smaller read lobe.
• Precharge on $\bar\phi_2$ϕˉ​2​, access on $\phi_1$ϕ1​; the word line is the AND of $\phi_1$ and the decode.
• The board’s write column: data on the bit side, so a read through the inverter on $\overline{\text{bit}}$ returns the complement of the data written.
• Two access gates per cell on the word line.
• A sense amplifier’s offset: 50–100 mV.
• The race in words: an unselected row’s first stage must fall before $\phi_1$ opens the second stage’s foot.

Derive (with the path).

• The two dividers (§2, §3): $V_X$ from $R/W_a + \sum R/W_i$ against $2R/W_p$2R/Wp​; $V_{read} = V_{DD}/(1 + 2\beta)$ from $R/W_{pd}$ against $2R/W_a$2R/Wa​.
• The bitline (§7): series width, normalized input $3W_{eq}$3Weq​, load $C_{BL}/C_g$CBL​/Cg​; a smaller swing in proportion.
• The address split (Chapter 18 §10): $\log_2 N_w = \log_2 R + \log_2 (C/W)$log2​(C/W).
• Predecode counts (§11): $n/k$ groups of $2^k$ lines; fan-out $2^{n-k}$2n−k.
• The race condition (§12): $t_{NO} \ge \sum t_{eval}$ of the stages between $\phi_2$ falling and $\phi_1$ rising.
• The decode path and the access time (§12, §13): one gain per stage, the word line with two gates per cell; add the bitline; FO4 ≈ 3 $\tau_1$ where the paper says so.

Method cards. The memory families (the decode path’s delay; the bitline and the access time; address bits; decoder and column waveforms; ROM tables) have their playbook cards: SRAM access path, memory addressing and ROM decoders and dynamic row decoders.

The lecture’s boards

The boards of Lectures 17 and 18 used in this chapter (24 frames)

Lecture17 @ 60:47 the 6T cell drawn, before the read and write lists

Lecture17 @ 64:30 the cell, the butterfly, read and write

Lecture18 @ 01:33 the cell redrawn; read stability being written

Lecture18 @ 02:57 the writability sketch begun

Lecture18 @ 04:20 writability: 3× strength, 1.5× size

Lecture18 @ 06:40 read stability: 1.5–2× smaller

Lecture18 @ 08:05 the read-stability board begun

Lecture18 @ 10:05 the read butterfly with its hatched lobes

Lecture18 @ 11:21 the write cell, before its butterfly

Lecture18 @ 13:42 the write butterfly finished

Lecture18 @ 19:23 both butterflies and the variability notes

Lecture18 @ 21:42 the two phases: precharge and access

Lecture18 @ 23:56 the read column and its skewed inverter

Lecture18 @ 27:40 the write column’s stacks beside the read column

Lecture18 @ 30:17 the one-device drivers being written

Lecture18 @ 31:37 the write column, the NOR drivers and φ1-stable data

Lecture18 @ 37:18 the column multiplexer

Lecture18 @ 39:11 the multiplexer uncovered; the sense amplifier begun

Lecture18 @ 44:13 the sense amplifier complete

Lecture18 @ 46:37 the sense amplifier’s two clock states

Lecture18 @ 48:37 the input offset voltage, 50–100 mV

Lecture18 @ 55:51 decoders: eight ANDs, predecoder and decoder

Lecture18 @ 56:46 the race-based NOR’s first stage

Lecture18 @ 58:46 the race-based NOR complete