Playbook

A card is the method for one family of exam questions, short enough to read in two minutes before you sit down to practise. It says how to recognize the question from its picture and its wording, the moves in the order you make them, the formulas you need (each marked Memorize or Derive, with the three-line derivation when it is Derive), the shortcuts that save time and when they hold, the traps the past papers and their keys fell into, and a link to every past part of the family.

How to use a card. Read it, then work one of its practice parts on paper against the clock. Check your lines against the part’s exam way page, which shows what to write; open the full solution when a step is unclear, because it explains why each formula applies. The final is closed book with no formula sheet, so the Memorize lines are the ones to know cold.

The playbook has fifteen cards so far: path sizing; the five families of sequential timing and clocking (flip-flop timing, latch loops, clock generation, pulsed latches, storage cells); the three families of datapath and control (parallel-prefix adders, logarithmic shifters, PLAs); the three families of memory (the SRAM access path, memory addressing and ROM decoders, dynamic row decoders); and the three families of wires and power (Elmore wires, clock-tree wires, power grids and decap). The others are added with the final-exam pages, one per family.

Path sizing

Recognize. The picture: a row of four static CMOS gates, every transistor labelled with a width ($W_1, \dots, W_4$W1​,…,W4​, or $W_1, \dots, W_8$ in pairs), and a large capacitor at the end, from 100 fF to 2 pF. Later parts add a capacitor, or a gate, hanging off one middle node. The phrases: “estimate the delay … the FO1 delay is $\tau_{inv}$τinv​”, “$W_1$W1​ is fixed … you are free to tune $W_2$W2​, $W_3$ and $W_4$W4​”, “minimize delay”, “the input capacitance … is limited to”, “the circuit is modified as shown”, “how might this new circuit be resized”. The strength convention is stated in the stem: “the nFET and pFET have the same drive strength”, or “the nFET has twice the on current of the pFET”. The finals also put a dynamic gate first, and some cap how far a gate may be skewed (a β limit).

The family’s picture: MT23-5’s four-gate path. Original figure ↗

Moves.

1. Read the strength convention. Equal strengths: a balanced inverter is W/W, input $2W$2W. $R_{pfet} = 2R_{nfet}$2Rnfet​: 2W/W, input $3W$3W.
2. Tabulate the stages. For each gate, its normalized inverter’s input (by the stack rule) and the capacitance of one of its inputs. Convert every load to microns of gate, $C/C_g$C/Cg​.
3. (a) The delay as drawn. Each gain is the next stage’s input (or the load) over this stage’s normalized input. The delay is $\tau_{inv}$ times their sum.
4. (b) Minimum delay, first gate fixed. $F = G \cdot H$ (or the product of the gains with the widths as unknowns); $f = F^{1/N}$F1/N; size back from the load, one stage at a time; the first stage’s gain checks the work; the delay is $N f\,\tau_{inv}$Nfτinv​.
5. An input limit instead of a fixed first gate. Use the whole limit, because $H = C_L/C_{in}$ is then smallest. Then as move 4.
6. (c) A side load at fixed sizes. Find its node. Add $C/C_g$ to the load of the one stage that drives that node, and recompute that gain only.
7. (d) Retuning. First rebalance the overloaded stage with the stage before it: only the gate between them moves, so their product is fixed and the equal split is best. Then split the path at the branch, balance each side, and tabulate the delay for a few sizes of the gate after the branch.
8. Give the delay in $\tau_{inv}$ and in ps or ns.

Formulas.

• Derive: gain $= \dfrac{\text{load}}{\text{normalized inverter's input}} = g \cdot h$h. Path: (1) a stage discharges everything on its output, $C_{out}$Cout​, through $R/W_{eq}$R/Weq​, where $W_{eq}$ is its normalized inverter’s NFET width, so $t \propto (R/W_{eq})\,C_{out}$(R/Weq​)Cout​; (2) the FO1 inverter gives $\tau_{inv} \propto (R/W)\,C_g\cdot 2W$ (equal strengths) or $\cdot\,3W$ ($R_{pfet} = 2R_{nfet}$Rpfet​=2Rnfet​); (3) divide: $t/\tau_{inv} = (C_{out}/C_g)/(2W_{eq})$(Cout​/Cg​)/(2Weq​), or $(C_{out}/C_g)/(3W_{eq})$ with $R_{pfet} = 2R_{nfet}$2Rnfet​: the load in microns of gate over the normalized input.
• Memorize: $n$ equal devices of width $W$ in series act like one of width $W/n$ (their resistances $R/W$ add).
• Memorize: $g_{inv} = 1$1; with $R_{pfet} = 2R_{nfet}$2Rnfet​, $g_{NAND2} = \tfrac43$ and $g_{NOR2} = \tfrac53$35​; with equal strengths, $g_{NAND2} = g_{NOR2} = \tfrac32$23​; AOI22 and OAI22, $g = 2$ either way.
• Memorize: $\text{Delay} = \tau_{inv}\sum f_i$τinv​∑fi​; $F = \prod f_i = G \cdot H$H, $G = \prod g_i$∏gi​, $H = C_L/C_{in}$CL​/Cin​, when nothing branches.
• Memorize: $f = F^{1/N}$ and $\text{Delay}_{min} = N\,F^{1/N}\,\tau_{inv}$NF1/Nτinv​, when $F$ is fixed.
• Derive: why equal gains are best, when a question asks. Path: (1) two stages, $\text{Delay}/\tau_{inv} = f_2 + F/f_2$F/f2​; (2) $1 - F/f_2^2 = 0$0, so $f_2 = \sqrt F = f_1$f1​; (3) resizing the gate between two stages keeps their product fixed, so every neighbouring pair is equal.
• Memorize: the branching effort $b = (C_{on} + C_{off})/C_{on}$Coff​)/Con​; with a branch, $F = GHB$ depends on the sizes.
• Derive: a balanced pair with a fixed product $P$ contributes $2\sqrt P$2P​. Path: $a + b - 2\sqrt{ab} = (\sqrt a - \sqrt b)^2 \ge 0$0, zero when $a = b = \sqrt P$P​.

Shortcuts.

• The product of part (a)‘s gains is $F$ when nothing branches, at any sizes. If (b) fixes the first gate at a different width, scale it: MT23-5’s (a) gains multiply to 150 with $W_1 = 10$10, and (b)‘s $F$ is $150 \times 10 = 1500$ with $W_1 = 1$1.
• A fourth root is two square roots: $1500^{1/4} = \sqrt{38.73} = 6.223$6.223.
• The first stage is a free check when you size back from the load: its gain must come out equal to $f$f.
• With equal strengths, a gate whose two networks are both stacks of two (AOI22, OAI22) has a normalized input equal to its per-device width.
• A side load at fixed sizes raises the delay by exactly the rise in one gain. It holds only while every size stays as it was.
• The bottom of the curve is flat. A pair split 3 and 5.33 instead of 4 and 4 costs about 4%, so round widths freely near the optimum; a split of 1 and 16 costs more than double.
• Rebalance first. It is never worse, and with a branch under about half the stage’s load (MT23-5, MT17-5, M7) it does most of the work. Enlarging the gate after the branch pays most when the branch dominates the load (MT21-5b: 99%).

Traps.

• Dividing by the gate’s own input capacitance: that is $h$h, not the gain.
• The wrong strength convention: W/W against 2W/W changes every normalized input.
• A side load on the wrong node (MT23-5c’s key).
• Picoseconds written as nanoseconds (MT23-5b–d’s key).
• Treating $F$ as fixed after a branch and re-taking $F^{1/N}$ (MT23-5d’s key): it can make the path slower.
• Resizing only the stage that drives the branch (MT17-5d’s key): the extra gain moves to the stage before it.
• Counting what a branch gate drives instead of its input (MT17-5c).
• Resizing the fixed first gate, or not using the whole input limit (MT21-5a).

Practice.

Paper	Parts (points)	Full solution	Exam way
MT23	5a–d (40)	M4 §1: a, b, c, d	a, b, c, d
MT21	5a–b (35)	M4 §2: a, b	with the retrofit
MT17	5a–d (40)	M4 §3: a, b, c, d	with the retrofit
FN17	7a–b (20 or 22)	F3 §1: a, b	with the retrofit
FN19	8a–c (35), a dynamic first stage	F3 §2: a, b, c	with the retrofit
FN10	9a–b (24), a dynamic first stage	F3 §4: a, b	with the retrofit
FN12	8a–b (30), a domino path	M6 §4	with the retrofit
M7 (practice)	Question 5a–d (40)	M7, Solution 5 (the questions)	with the retrofit
HW3	3a–b (homework)	H3 §3	—

The method itself is taught in Chapter 8: the gain from the normalized inverter (§1), path effort (§2), equal gains (§3), the number of stages (§4), branching and retuning (§8–9).

Flip-flop timing

Recognize. The picture: two clocked elements with logic between them, and something wrong with their clocks. The finals draw each flip-flop as its two latches, so four latches in a row on φ1, φ2, φ1′, φ2′ are two flip-flops. A box CG per pair means each pair’s phases are made locally, by a NOR generator with delays $\Delta_1$ and $\Delta_2$Δ2​. When the words (or FN17-3’s drawing) describe a clock tree on a noisy supply, it is jitter. The phrases: “skewed to arrive 50 psec earlier”, “CLK2 arrives 1.5nsec later than CLK1”, “will this circuit function correctly”, “what is the largest value of $t_{logic}$tlogic​”, “how must $\Delta_1$ and $\Delta_2$ … be adjusted (from zero)”, “what jitter can I expect”, “functional failure that could not be eliminated by slowing down the clock”. The data: $t_{setup}$tsetup​, $t_{clk-q}$tclk−q​, sometimes $t_{hold}$ (take 0 when none is given) and sometimes $t_{d-q}$ (the latch’s $t_{D\to Q}$tD→Q​), which a flip-flop-to-flip-flop path never uses.

The family’s picture: FN17-5’s four latches, read as two flip-flops. Original figure ↗

Moves.

1. Read the pairs. In each pair the first latch the data meets is the master. The pair captures when the master closes and launches when the slave opens. $t_{setup}$ and $t_{hold}$ are the master’s, $t_{clk\to Q}$ the slave’s.
2. Sign the skew. $\delta$ = capture edge − launch edge. “The capturing clocks arrive 50 ps earlier” is $\delta = -50$ ps; “CLK2 arrives 1.5 ns later”, at the capturer, is $\delta = +1.5$ ns. Write the edge times of one cycle.
3. Hold first. $t_{clk\to Q} + t_{logic,min} \ge \delta + t_{hold}$ (+ $t_{overlap}$ on the left if the pair has a window). It has no $T_{cycle}$Tcycle​, so a failure here is one no clock speed fixes.
4. Then the long path. $t_{clk\to Q} + t_{logic,max} + t_{setup} \le T_{cycle} + \delta - t_{overlap}$toverlap​; solve for $t_{logic}$ or for $T_{cycle}$Tcycle​.
5. Repair a hold failure. Pad the short path, or open a non-overlap window between the launching master’s closing and its slave’s opening, $t_{overlap} \ge \delta + t_{hold} - t_{clk\to Q} - t_{logic,min}$tlogic,min​. With the NOR generator, pick the delay that follows the master’s closing edge. The window costs every long path as much.
6. Jitter. $\Delta t \approx |S|\,(\Delta V_{DD}/V_{DD})\,t_{latency}$∣S∣(ΔVDD​/VDD​)tlatency​. Between flip-flops on different leaves it enters as $\delta = +\Delta t$ for hold and $\delta = -\Delta t$ for setup.
7. Conditional parts. “If the circuit is not functional in (a)”: test the condition. If it is false, say so, give the repair for the other sign in one line, and “now” means the earlier answer stands.

Formulas.

• Derive: the long path. Path: (1) the launch edge at 0; Q moves at $t_{clk\to Q}$tclk→Q​, and the data reaches the capturer at $t_{clk\to Q} + t_{logic}$tlogic​; (2) the capturer’s next edge is at $T_{cycle} + \delta$δ, and a window delays the launch, $- t_{overlap}$−toverlap​; (3) arrive $t_{setup}$ before it: $t_{clk\to Q} + t_{logic} + t_{setup} \le T_{cycle} + \delta - t_{overlap}$toverlap​.
• Derive: the short path. Path: (1) the same launch, delayed by any window, $t_{overlap}$toverlap​; (2) the capturer’s edge of the same cycle is at $\delta$δ, and it holds the old data until $\delta + t_{hold}$thold​; (3) the new data must not arrive sooner: $t_{overlap} + t_{clk\to Q} + t_{logic} \ge \delta + t_{hold}$thold​.
• Memorize: a master–slave pair captures when the master closes and launches when the slave opens; its $t_{D\to Q}$ plays no part between two pairs.
• Memorize: the NOR generator, $\phi_1 = \text{NOR}(\phi, \Delta_1(\phi_2))$NOR(ϕ,Δ1​(ϕ2​)), $\phi_2 = \text{NOR}(\overline\phi, \Delta_2(\phi_1))$NOR(ϕ​,Δ2​(ϕ1​)). φ falling drops φ2 at once and raises φ1 $\Delta_1$ later; φ rising drops φ1 at once and raises φ2 $\Delta_2$ later. Each delay must stay shorter than its half period.
• Derive: the supply sensitivity of a velocity-saturated inverter. Path: (1) $t \propto C V_{DD}/I$ with $I \propto V_{DD} - V_T$VT​, so $t \propto V_{DD}/(V_{DD} - V_T)$VT​); (2) $\ln t = \ln V_{DD} - \ln(V_{DD} - V_T) + \text{const}$const; (3) $S = \dfrac{d\ln t}{d\ln V_{DD}} = 1 - \dfrac{V_{DD}}{V_{DD} - V_T} = -\dfrac{V_T}{V_{DD} - V_T}$−VDD​−VT​VT​​. The square law gives $1 - 2V_{DD}/(V_{DD} - V_T)$VT​).
• Memorize: jitter $\Delta t \approx |S|\,(\Delta V_{DD}/V_{DD})\,t_{latency}$∣S∣(ΔVDD​/VDD​)tlatency​, to first order.

Shortcuts.

• An early capture clock needs no hold check when $t_{hold} \le t_{clk\to Q}$tclk→Q​: then even $t_{logic} = 0$ passes. FN17-5a has 60 ps of margin. It costs the long path $|\delta|$ instead.
• Skew moves time; it creates none. The stage after a skewed pair, launching from the skewed clock into an on-time one, gets $T_{cycle} - \delta$δ, so the two stages sum to $2(T_{cycle} - t_{clk\to Q} - t_{setup})$tsetup​): FN17-5’s 435 + 535 = 970 ps. It checks the sign. Condition: the stage after launches from the same skewed clock.
• Flip the skew’s sign and the two checks trade $2|\delta|$2∣δ∣. FN17-5 with the primes late: the long path gains 100 ps (to 535 ps) and hold loses 100 ps (from +60 to −40 ps).
• A hold repair needs the same amount from a window as from padding, $\delta + t_{hold} - t_{clk\to Q} - t_{logic}$tlogic​; with the overheads ignored, $\delta - t_{logic}$tlogic​. FN12-7b: $1.5 - 0.5 = 1.0$ ns either way. Condition: the hold check alone; the window also costs every long path.
• Jitter scales with latency. Halve the tree’s delay and the jitter halves; FN10-6c’s 5% of 2 ns is 100 ps. Condition: first order, every buffer on the same noisy supply.

Traps.

• Four latches read as four stages.
• Adding $t_{D\to Q}$ (the papers’ $t_{d-q}$td−q​) between flip-flops (FN17-5b: 425 instead of 435 ps), or taking $t_{clk\to Q}$ from the master.
• The wrong sign: $+50$ for an early capture clock (535 ps), or a hold failure claimed for one.
• Comparing hold with the next edge: that is setup.
• Believing a slower clock fixes hold (FN10-6d asks exactly this: it cannot).
• Raising $\Delta_2$ because Chapter 14’s board flip-flop has its master on φ1. FN12-7b’s master is on φ2, so the knob is $\Delta_1$Δ1​.
• Leaving out the generator’s ceiling: $\Delta_1 < T_{cycle}/2 = 5$ ns in FN12-7b. The key gives $\Delta_1 \ge 1.0$ ns and omits it.
• Jitter from one inverter instead of the whole 2 ns latency, or with part (b)‘s square-law $-1.5$ (600 ps instead of 100 ps).
• Dropping the sign of $\Delta V_{DD}$ΔVDD​, as the FN10-6c key does (its size is right): the delay grows as the supply falls.
• Repairing a circuit that works (FN17-5c), or subtracting in (d) a window that (c) never opened.

Practice.

Paper	Parts (points)	Full solution	Exam way
FN17	5a–d (40)	FS1, FN17-5: a, b, c, d	a, b, c, d
FN12	7b (15)	FS1, FN12-7b	b
FN10	6c–d (15), jitter	FS1, FN10-6: c, d	c, d
PS5	Q1c, a loop of two flip-flops	FS1, PS5-Q1c	c
Added	three harder variations: the primes late; supply droop; the master on φ1	FS1 V1, V2, V3	—
FN12	7a (15), the generator itself	FS2, FN12-7a (clock-generation card)	a
FN19	5a (10), hold with a pulsed latch	FS2, FN19-5a (pulsed-latch card)	a
FN17	3b (11), a clock tree’s jitter from supply noise	FW1, FN17-3b (clock-tree card)	b
FN17	1d, why a clock’s latency should be low	not yet in the guide	—

The method is taught in Chapter 13: the master–slave pair (§10) and the long path (§11); and in Chapter 14: skew and the long path (§1), short paths and hold (§2), and two-phase clocks with the non-overlap window (§3). Jitter is Lecture 22’s topic (Chapter 23, still to come); FS1’s FN10-6 teaches it in place.

Latch loops

Recognize. The picture: a row of latches on alternating phases, logic blocks between them, and a wire from the last latch back to the first; the clocks drawn as square waves with their high and low times; primed clocks marking a skewed group. The phrases: “indicate if the circuit is functional (i. e., it is a valid FSM)”, “how the circuit, delays, or clocks could be modified”, “try to explore more than one possibility”, “even if the circuit is functional, indicate any issues”, “you cannot change this skew time”. Setup, hold and the latches’ own delay are usually zero.

The family’s picture: PS5-Q1c’s loop of four latches. Original figure ↗

Moves.

1. Write the windows. Put φ1’s rising edge at 0 and write each latch’s open interval, the primes shifted by the skew. PS5: φ1 [0, 5), φ2 [5, 10), φ1′ [1.5, 6.5), φ2′ [6.5, 11.5) ns.
2. Count the cycles. Alternating latches hold half as many cycles as latches; a single latch fed back on itself holds one.
3. Rule 2 first. $\sum t_{logic} \le N_{cycles}\,T_{cycle}$Ncycles​Tcycle​. If it fails, only more time or less logic fixes the loop.
4. Race checks. From each latch’s opening edge, through the next block, against the next latch’s previous closing edge plus $t_{hold}$thold​. A φ1 latch feeding a φ2 latch directly is a flip-flop: use the flip-flop checks with $\delta$δ.
5. Walk from L1’s opening edge: wait at a closed latch, pass an open one, check every closing edge. If a lap ends later than the one before, walk more laps.
6. After a wait, restart the clock at that latch’s opening edge. The blocks that follow must reach each later latch before it closes; this chain, not rule 2, can set the period.
7. Repairs, more than one: a slower clock (rule 2 or a chain), faster logic, padding (a race), moving a latch into a block (retiming), a non-overlap window. The skew itself stays.

Formulas.

• Memorize: rule 1: the data reaches every latch before its closing edge (minus $t_{setup}$tsetup​).
• Memorize: rule 2: $\sum t_{logic} \le N_{cycles}\,T_{cycle}$Ncycles​Tcycle​.
• Derive: the race into latch $k$k. Path: (1) the data leaves latch $k-1$ no earlier than its opening edge, $t_{open,k-1}$topen,k−1​; (2) latch $k$‘s previous window closes at $t_{close,k} - T_{cycle}$ and must keep its data $t_{hold}$ longer; (3) $t_{open,k-1} + t_{logic} \ge t_{close,k} - T_{cycle} + t_{hold}$thold​.
• Derive: one latch fed back on itself. Path: (1) the data leaves as the latch opens and returns after $t_{loop}$tloop​; (2) it must not return while the latch is open: $t_{loop} \ge t_{high} + t_{hold}$thold​; (3) it passes once per cycle: $t_{loop} \le T_{cycle}$Tcycle​.
• Derive: the chain after a wait. Path: (1) data that waits at latch $j$ leaves at its opening edge, $t_{open,j}$topen,j​; (2) it reaches a later latch $k$ after the blocks between them; (3) $t_{open,j} + \sum_{i=j}^{k-1} t_{logic,i} \le t_{close,k} - t_{setup}$ for every $k$ up to the next wait.

Shortcuts.

• Rule 2 alone decides the loop when nothing waits after the first lap. PS5-Q1e: 21 ns in 20 ns fails (on lap 5), and at $T_{cycle} = 10.5$ ns it settles. Condition: no latch makes the data wait from lap 2 on.
• The margin shrinks by $\sum t_{logic} - N_{cycles}T_{cycle}$ a lap, so the failing lap follows from one margin. PS5-Q1e: 2.5 ns on lap 2, 1 ns a lap, negative on lap 5. Condition: the same.
• On 50% phases a race does not depend on the period: the closing edge moves with $T_{cycle}/2$Tcycle​/2. PS5-Q1c is 0.5 ns short at 10 ns and at 20 ns. Condition: the phases scale with the period.
• One block longer than the time from its starting latch’s opening to the next latch’s closing fails, whatever rule 2 says. PS5-Q1d: 11 ns against $21.5 - 11.5 = 10$ ns. Condition: the data waits at the starting latch.

Traps.

• Counting latches instead of cycles: four alternating latches are two cycles.
• Checking only the windows the data is meant to use: the race sits in the previous window.
• One good lap taken as proof (PS5-Q1e passes its first four laps).
• A slower clock offered for a race (PS5-Q1c). For a single latch at 50% duty it is worse: PS5-Q1a races above 14 ns.
• Meeting only the next closing edge after a wait. In PS5-Q1d a 10 ns block meets φ2′ exactly but reaches φ1 0.5 ns late; the block must be at most 9.5 ns. The agent-written PS5 solution (PS5 has no key) does not discuss this.
• Moving logic between the two latches of a one-cycle loop (PS5-Q1b): the loop still has one cycle.
• Calling a loop broken because the walk from the edge waits: walk the launch forward first (Chapter 14’s third example).

Practice.

Paper	Parts	Full solution	Exam way
PS5	Q1a–e (no points)	FS1, PS5-Q1: a, b, c, d, e	a, b, c, d, e
Added	two harder variations: six latches with a late corner; PS5-Q1c on non-overlapping phases	FS1 V4, V5	—
Lecture	three worked four-latch loops	Chapter 14 §9	—
FN19	5a (10), a pulsed latch: one latch’s open window against a short path	FS2, FN19-5a (pulsed-latch card)	a

No past final has a latch loop; PS5-Q1 is the family’s only graded source. The method is taught in Chapter 14: transparent latches and cycle stealing (§7), the two rules of the road (§8) and the worked loops (§9); the race check is §2’s short path, applied to latches.

Clock generation

Recognize. The picture: a box marked CG followed by “≡” and what it stands for: two NOR (or NAND) gates, an inverter, and one or two boxes marked Δ, which are delay blocks made of an even number of inverters. One clock goes in and two phases come out, and below the circuit the paper prints φ with empty rows for φ1 and φ2. The phrases: “local clock generator”, “generate two clock phases locally from a single-wire global clock”, “sketch the φ1 and φ2 waveforms”, “ignore the gate delays … but indicate the Δ1 and Δ2 delays on your sketch”, and, in a timing part that follows, “how must Δ1 and Δ2 be adjusted”. FN19-6b’s generators, inverters and a NAND around a box marked “replica AND row”, are move 8’s replica delay; the PLA card has their edges.

The family’s picture: FN12-7’s generator, each delay block taking the other phase. Original figure ↗

Moves.

1. Read every wire. Write each phase as a function of its inputs, naming each delayed input by the signal it comes from: $\phi_1 = \text{NOR}(\phi, \Delta_1(\phi_2))$NOR(ϕ,Δ1​(ϕ2​)). Which phase each delay block takes is the whole question.
2. Find the controlling value: 1 for a NOR (any 1 makes the output 0), 0 for a NAND.
3. Set the steady state before the first edge of φ.
4. Walk each edge of φ. A gate whose direct input takes the controlling value switches at once. A gate whose direct input leaves it waits for its last input, the delayed other phase: that wait is the Δ on the sketch.
5. Draw every row on φ’s time axis and label each gap (or overlap) with its Δ and the edge it follows.
6. Check: a NOR generator never has both phases high; with Δ → 0 the phases become a complementary pair.
7. If a timing part follows, find which phase clocks the master. The window between the master’s closing edge and the slave’s opening edge protects hold, so widen that window’s Δ, and pay for it on the long path.
8. A replica delay (FN19-6b): when one clock must wait for a block to finish, build the delay block as a copy of that block’s slowest path (a replica row), so the delay tracks it at every corner. Chapter 18 §9 builds a dynamic PLA’s two clocks this way; FN19-6b’s single replica row is solved in FD1 and drilled on the PLA card.

Formulas.

• Memorize: a NOR’s output is 1 only when every input is 0; a NAND’s is 0 only when every input is 1. A delay block’s output at time $t$ is its input at $t - \Delta$Δ.
• Derive: the NOR generator’s windows, for ideal gates and each Δ shorter than its half period. Path: (1) φ rises, a 1 reaches φ1’s NOR, and φ1 falls at once; (2) φ2’s NOR still sees $\Delta_2(\phi_1) = 1$ for $\Delta_2$Δ2​, so φ2 rises $\Delta_2$ after φ rises; (3) the same at φ’s falling edge with the roles swapped: φ2 falls at once, φ1 rises $\Delta_1$ later.
• Derive: with gate delays, each window is $\Delta + t_{NOR}$tNOR​. Path: (1) the phase that falls does so $t_{NOR}$ after its direct input switches; (2) its delayed copy falls $\Delta$ later; (3) the other NOR rises $t_{NOR}$ after that, so the gap is $\Delta + t_{NOR}$ (the inverter drops out while it is faster than that route).
• Memorize: the window hold needs, and its price: $t_{overlap} \ge t_{skew} + t_{hold} - t_{clk\to Q} - t_{logic}$tlogic​, and $t_{logic} \le T_{cycle} - (t_{clk\to Q} + t_{setup}) - t_{overlap}$toverlap​.

Shortcuts.

• A phase is not a delayed copy of φ or φ̄. Only its rising edge waits; it falls at once. Condition: a NOR generator (with NANDs it is the falling edge that waits).
• NORs make gaps, NANDs make overlaps. By De Morgan, the NAND generator is the NOR generator with its two outputs inverted and exchanged and its two delays swapped, so each of its overlaps is as long as one Δ. Condition: the same wiring.
• Real gates add one NOR to each window: FS2’s Variation 1 turns blocks of 60 and 100 ps into windows of 90 and 130 ps with $t_{NOR} = 30$ ps. Condition: the inverter is faster than a block plus a NOR.
• Only one window protects hold: the one after the master’s closing edge. With the master on φ1 that is the $\Delta_2$ window; with the master on φ2 (FN12-7b) it is the $\Delta_1$ window.

Traps.

• Swapping $\Delta_1$ and $\Delta_2$Δ2​: read which phase each block takes.
• Drawing each phase as a delayed copy of φ or φ̄, late at both edges.
• Drawing the two phases as mirror images: the gaps are $\Delta_2$ after one edge and $\Delta_1$ after the other.
• Widening the window after the slave’s closing edge to cure hold: it does nothing for that race.
• Clocking latches with a NAND generator: its overlap lengthens the race (FS2’s Variation 2: with a 30 ps overlap a shift register with $t_{clk\to Q} = 40$ ps and $t_{hold} = 15$ ps needs 5 ps of logic even on perfect clocks).
• No key error in this family so far: FN12-7a’s key agrees.

Practice.

Paper	Part (points)	Full solution	Exam way
FN12	7a (15): sketch φ1 and φ2	FS2 §1	7a
FN12	7b (15): set $\Delta_1$ and $\Delta_2$ against 1.5 ns of skew; a flip-flop timing part on the same generator	FS1	7b
FN19	6b (8): a replica AND row that times a PLA’s two clocks	FD1, FN19-6b (PLA card)	6b
FS2 (added)	Variation 1: the generator with gate delays; Variation 2: a NAND generator	V1, V2	—

The method itself is taught in Chapter 14 §3: two-phase clocks, the non-overlap window, the cross-coupled NOR generator and the window’s cost. Overlapping phases are Chapter 15 §8 and §10. Self-timed clocks from replica rows are Chapter 18 §8 and §9.

Pulsed latches

Recognize. The picture: a box marked CC (a clock chopper) followed by “≡” and an inverter, a delay block Δ and a NOR; then two latches, each clocked through its own CC box from CLK1 and CLK2, with combinational logic between them. A second part sends the chopped clock through an inverter into a load capacitance. The phrases: “clock-chopped flip-flops”, “the pulse width of the chopped clock”, “a hold time of … on their closed clock edge”, “CLK2 arrives 100 psec earlier”, “driven from an inverter with a load capacitance”, “what will be the ‘height’ of the pulse?”, “what problems might this present?”.

The family’s picture: FN19-5’s chopper and its two clock-chopped latches. Original figure ↗

Moves.

1. Read the chopper. NOR(clk, clk inverted and delayed) is high only just after each falling edge, for the chain’s delay; the papers call Δ the width and ignore the single inverter.
2. Place the pulses: the launching pulse opens at 0 and the receiving pulse at $\delta$δ, the signed skew, negative when the receiving clock is early.
3. Hold. The new data, at $t_{clk\to Q} + t_{logic,min}$tlogic,min​, must arrive after the receiving pulse closes plus the hold time: solve for the widest pulse. If no clock-to-Q delay is given, take 0 and say so.
4. The long path, if a period is given: so as to borrow nothing from the next stage, the data must reach the receiving latch by its pulse’s opening, with the early receiving clock.
5. Distribution. $C_{in}$ from the driver’s widths times $C_g$Cg​; $t_d = \tau_1 C_L/C_{in}$τ1​CL​/Cin​. A pulse shorter than $t_d$ arrives as a runt.
6. Height and consequence: $1 - 2^{-t_{pulse}/t_d}$ of $V_{DD}$VDD​; sketch the bump, say what it does to the latch, and cure it with the driver or a chopper beside the latch, never with a wider pulse.

Formulas.

• Derive: pulsed hold. Path: (1) the new data reaches the receiving D at $t_{clk\to Q} + t_{logic}$ after the launching pulse opens; (2) the receiving latch listens until its pulse closes, at $\delta + t_{pulse}$tpulse​, and for $t_{hold}$ more; (3) so $t_{pulse} \le t_{clk\to Q} + t_{logic,min} - t_{hold} - \delta$δ.
• Memorize: a driver’s delay, $t_d = \tau_1 C_L/C_{in}$τ1​CL​/Cin​, measured at the 50% point, with the driver’s own drain capacitance ignored.
• Derive: the runt’s height. Path: (1) a step into an RC moves $1 - e^{-t/\tau_{RC}}$ of the swing; (2) the 50% point at $t_d$ gives $\tau_{RC} = t_d/\ln 2$td​/ln2; (3) after $t_{pulse}$ the output has moved $1 - 2^{-t_{pulse}/t_d}$ of $V_{DD}$VDD​.
• Memorize: the pulsed long path without borrowing, $t_{clk\to Q} + t_{logic,max} \le T_{cycle} + \delta$δ, with setup met inside the pulse when $t_{pulse} \ge t_{setup}$tsetup​; a flip-flop needs $t_{clk\to Q} + t_{logic} + t_{setup} \le T_{cycle} + \delta$δ.

Shortcuts.

• Skew moves the pulse cap one for one. An early receiving clock adds its skew to the widest pulse, a late one takes it away: FN19-5a gives 150 ps with no skew, 250 ps with CLK2 100 ps early, 50 ps if it were late. Condition: identical choppers, so the pulses are offset by exactly the clocks’ skew.
• Runt landmarks: pulses of $0.5$0.5, $1$ and $2\,t_d$ reach $0.29$0.29, $0.5$ and $0.75$ of $V_{DD}$VDD​, so FN19-5b’s $0.6\,t_d$ must land between the first two (0.34). Condition: the 50%-point RC model.
• The driver a pulse needs: for half the swing, $C_{in} \ge \tau_1 C_L/t_{pulse}$ (FN19-5b: 20 fF); for 90%, $t_d \le t_{pulse}/\log_2 10 = t_{pulse}/3.32$ (66.4 fF). Condition: hold fixes the pulse width.
• Hold and setup take opposite skews: the late receiving clock caps the pulse, the early one sets the period.

Traps.

• Reading an early receiving clock as late: FN19-5a then gives 50 ps instead of 250 ps.
• Measuring hold from the pulse’s opening edge instead of its closing edge.
• Drawing the NOR chopper’s pulse at the rising edge, or giving a NOR an even chain: it makes no short pulse, only $\overline{\mathrm{clk}}$ shortened by the chain.
• Taking $t_d$ itself as the RC time constant: the unofficial 2019 solution boxes $0.451\,V_{DD}$ for FN19-5b that way. With the course’s 50%-point delay the height is $0.340\,V_{DD}$0.340VDD​, which it gives only as an alternative.
• Curing a runt by widening the pulse: hold capped the width.
• Counting the pulse as free time on the long path: what one stage borrows, the next loses (FS2’s Variation 3: 960 ps, not 916).

Practice.

Paper	Part (points)	Full solution	Exam way
FN19	5a (10): the widest pulse	FS2 §2	5a
FN19	5b (12): the runt through a loaded inverter	FS2 §2	5b
FS2 (added)	Variation 3: a pulsed design end to end; Variation 4: a double-edge chopper	V3, V4	—

The method itself is taught in Chapter 14: pulsed latches and their short path (§4), the clock chopper (§5) and runt pulses (§6); the driver’s delay is Chapter 7 §7.

Storage cells

Recognize. The picture: a latch drawn at transistor or gate level (a pass NFET or a transmission gate on clk, a forward inverter, a feedback inverter, sometimes clocked devices or a TSPC stack), or a small sequential design given only in words. The phrases: “he is unable to write the latch”, “Y is not affected by the value of A”, “what has gone wrong? How can this be fixed?”, “design a two-bit wrap-around counter”, “a synchronous input reset”, “design your circuit for the fastest clock frequency possible”. No past paper yet asks “which nodes are dynamic?” or for a half latch on a TSPC flip-flop, but the lecturer flags that question as an exam candidate (Lecture14 @ 27:02; FS2’s Variation 5).

The family’s picture: FN19-9’s pass-transistor latch, whose feedback inverter is always on. Original figure ↗

Moves.

1. Name every internal node (X for the storage node) and, for each clock phase, list the devices that conduct onto it. Something pulling both ways is a fight; nothing conducting is a dynamic node.
2. A write: the writer (the driver and the switch, in series) against the holder (the feedback device that is on in the old state). Estimate the divider and compare it with $V_M$VM​, in both directions.
3. The fix: weaken the holder, strengthen the writer, or, robustly, switch the feedback off while writing (gated feedback).
4. A design: state table, next-state equations, gates (the fewest levels, for speed), then the flip-flops (their edge, static or dynamic, Q and Q̄).
5. A synchronous input goes through D and acts at the next edge. One that arrives $t$ after the edge is a flip-flop output with $t_{clk\to Q} = t$t: it meets the next edge’s setup and this edge’s hold.
6. The fastest clock is set by the slowest path into any D, $t_{start} + t_{logic} + t_{setup}$tsetup​.
7. A dynamic cell: walk each phase and data sequence, find the state with two floating nodes, and hold the inner one with a half latch gated by the output.

Formulas.

• Memorize: device resistance in the course’s model: an NFET of width $W$ pulling down is $R/W$R/W; a PFET pulling up, $2R/W$2R/W; an NFET pulling up, about $2R/W$2R/W, and only to $V_{DD} - V_T$VT​. Devices in series add.
• Derive: the write as a divider. Path: (1) during the fight the same current flows through the pull-up and the pull-down side; (2) so $V_X = V_{DD}\,R_{down}/(R_{down} + R_{up})$Rup​); (3) the write succeeds if $V_X$ crosses $V_M$VM​; at $V_M = V_{DD}/2$VDD​/2, if the writer’s resistance is the smaller.
• Memorize: a flip-flop’s paths, $t_{clk\to Q} + t_{logic} + t_{setup} \le T_{cycle}$ and $t_{clk\to Q} + t_{logic,min} \ge t_{hold}$thold​.
• Memorize: a binary counter flips bit 0 every cycle and bit $k$ when all lower bits are 1 ($Q_1^+ = Q_1 \oplus Q_0$Q1+​=Q0​); a synchronous reset ANDs each next state with $\overline{\mathrm{reset}}$reset.
• Memorize: a half latch is about one tenth of the strength of the network that must overpower it.
• Derive: a dynamic node’s slowest clock. Path: (1) the leakage $I_{leak}$ drains $C_s$Cs​; (2) the node may droop $\Delta V_{max}$ΔVmax​, so it holds for $t_{hold,max} = C_s\,\Delta V_{max}/I_{leak}$Cs​ΔVmax​/Ileak​; (3) it must hold for half a period, so $f \ge 1/(2t_{hold,max})$1/(2thold,max​).

Shortcuts.

• Compare resistances, not voltages. At $V_M = V_{DD}/2$ the side with the smaller resistance wins. Condition: a balanced forward inverter.
• At normal sizes an ungated feedback inverter wins both ways. With every inverter 2/1 and a 1 µm pass NFET, X stalls at $\tfrac23 V_{DD}$ writing a 0 and at $\tfrac14 V_{DD}$ writing a 1. To lose both fights, the feedback PFET must be narrower than 1 µm and its NFET narrower than 1/3 µm, so it is made long instead. Condition: the course’s resistor model.
• Writing a 1 through an NFET is the worse direction: check it first.
• Gated feedback needs no sizes: nothing fights the write at any corner.
• One gate level for a counter bit: with Q and Q̄ both available, $\overline{\mathrm{reset}}\,(Q_1 \oplus Q_0) = \overline{\mathrm{reset} + Q_1Q_0 + \overline{Q_1}\,\overline{Q_0}}$ is a single complex gate. Condition: the flip-flops give both outputs.
• A late synchronous input is rarely critical. It leaves $t_{clk\to Q} - t$ before the flip-flops’ outputs do (PS5-Q2, with example delays: a 95 ps reset path against a 195 ps counter path). Condition: $t < t_{clk\to Q}$tclk→Q​.

Traps.

• Strengthening the forward inverter: its gate draws no current, so it does not fight.
• Widening only the pass NFET: the driver is in series with it.
• Checking only the write-0 direction.
• A transmission gate alone against a 2/1 feedback inverter: still a ratio, and it can still lose (FS2’s Variation 6).
• A synchronous reset wired to the stored nodes: that is an asynchronous reset.
• Letting a reset that arrives after an edge act at that edge: it acts at the next one.
• Reading an inverting flip-flop’s output (TSPC) as Q.
• No key error in this family so far: FN19’s unofficial solution and PS5’s agent-written work agree with FS2.

Practice.

Paper	Part (points)	Full solution	Exam way
FN19	9 (10): a latch that cannot be written	FS2 §3	9
PS5	Q2a (no points): the counter’s logic	FS2 §4	Q2a
PS5	Q2b (no points): the reset and the clock	FS2 §4	Q2b
PS5	Q3a (no points): a scan flip-flop’s schematic	not yet in the guide (the test page)	not yet in the guide
FS2 (added)	Variation 5: half latches on a TSPC toggle flip-flop (the lecturer’s flagged exam candidate); Variation 6: a transmission gate against its feedback	V5, V6	—

The method itself is taught in Chapter 13: the latch circuits (§6), the write fight (§7), gated feedback (§8), master–slave (§10) and the long path (§11); the dynamic cells in Chapter 15: the dynamic flip-flop (§1), the half latch (§5) and the TSPC flip-flop (§6).

Parallel-prefix adders

Recognize. No picture: FN17-8 prints its three blocks as equations and asks for the drawing. The phrases: “draw the block schematic diagram of an 8-bit parallel adder composed of an interconnection of three logic building blocks”, “a PG generator with the equations: $p = a\oplus b$b, $g = ab$ab”, “a radix-two lookahead element with the equations: $P = p_1p_0$p1​p0​, $G = g_1 + p_1g_0$p1​g0​”, “sum generator with the equation: $s = p\oplus c$c”, “draw the critical path through your network”. Nothing is computed; the marks are for the wiring and the path.

The family’s answer, since the paper prints no figure: FN17-8’s adder, each sum fed from the column to its right, with both critical paths. Original figure ↗

Moves.

1. Number the positions. The carry-in is position 0, entered as the pair $(c_{in}, 0)$(cin​,0); the bits are 1 to $N$N. Draw them as the key does: bit $N$ at the left, the carry-in entering at the right.
2. Bottom row: one PG generator per bit, $g_k = a_kb_k$ and $p_k = a_k\oplus b_k$bk​.
3. Read the element as groups. The paper’s $g_1, p_1$ is the higher span’s $(G, P)$(G,P), and $g_0, p_0$ the adjacent lower span’s. The higher span always enters on the left.
4. The network: Kogge–Stone unless the paper names another. In level $m$m, every row whose span does not yet reach position 0 merges with the row $2^{m-1}$ below it. For 8 bits: 8, 7, 5 and 1 elements, 21 in 4 levels (the board’s Brent–Kung: 13, also in 4).
5. Top row: $s_1 = p_1\oplus c_{in}$cin​, with the carry-in wired straight up; $s_k = p_k\oplus G_{k-1:0}$Gk−1:0​, its $p_k$ straight up from its own PG generator and its carry from the column one to its right (the bit below). $c_{out} = G_{N:0}$ feeds no sum.
6. The depths: $L$ for $C_{N-1}$CN−1​, the top sum’s carry, and $L'$ for $C_N$CN​, the carry-out. Kogge–Stone puts every $C_k$ at its bound, $\lceil\log_2(k + 1)\rceil$1)⌉.
7. Mark both critical paths, PG → $L$ elements → $s_N$ and PG → $L'$ elements → $c_{out}$cout​, and say which is longer and when. For a network whose carries are not all at their bounds (Brent–Kung), find the deepest $C_{k-1}$ over every $k$k: the last sum may sit in the middle.
8. Check with two additions through the drawing: $1 + 1$ with $c_{in} = 0$ must give 2, and $0 + 0$ with $c_{in} = 1$ must give 1 (the only test of the wire from $c_{in}$ to $s_1$s1​).

Formulas.

• Memorize: $g_k = a_kb_k$ and $p_k = a_k\oplus b_k$ (the XOR, because the sum reuses it); the element $(G_{hi}, P_{hi})\circ(G_{lo}, P_{lo}) = (G_{hi} + P_{hi}G_{lo},\ P_{hi}P_{lo})$Phi​Glo​, Phi​Plo​), associative but not commutative.
• Derive: the carries and the sums, $C_k = G_{k:0}$Gk:0​, $s_k = p_k\oplus C_{k-1}$Ck−1​, $c_{out} = C_N$CN​. Path: (1) a carry leaves bit $k$ if some position $j \le k$ generates and every bit from $j + 1$ to $k$ propagates: the group generate $G_{k:0}$Gk:0​; (2) position 0 generates when $c_{in} = 1$ and passes nothing on, so it enters as $(c_{in}, 0)$(cin​,0); (3) bit $k$‘s sum is $p_k$ XOR the carry into it, the carry out of bit $k - 1$1.
• Memorize: Kogge–Stone over $N + 1$ positions has $(N + 1) - 2^{m-1}$ elements in level $m$ and $\lceil\log_2(N + 1)\rceil$ levels. No network of two-input elements makes $C_k$ in fewer than $\lceil\log_2(k + 1)\rceil$ levels.
• Derive: the critical path, $t_{s_N} \approx t_{PG} + L\,t_e + t_{sum}$ and $t_{c_{out}} \approx t_{PG} + L'\,t_e$L′te​. Path: (1) the blocks on a path are in series, so their delays add; (2) $s_N$ needs $C_{N-1}$CN−1​, at depth $L$L, then one XOR; (3) $c_{out}$ is $C_N$ itself, at depth $L'$L′. Fan-out and wires ignored, as the lecture counts.
• Derive: the miswired sum’s error, $s'_k = p_k\oplus C_k = s_k\oplus C_{k-1}\oplus C_k$Ck​. Path: (1) insert $C_{k-1}\oplus C_{k-1} = 0$0; (2) regroup as $(p_k\oplus C_{k-1})\oplus(C_{k-1}\oplus C_k)$Ck​); (3) the first bracket is $s_k$sk​, so bit $k$ is wrong exactly where the carry changes across it.
• Memorize: $a - b = a + \bar b + 1$1. XOR each $b_k$ with the subtract line and feed the same line to $c_{in}$cin​; $c_{out} = 1$ means no borrow.

Shortcuts.

• Classify spans to evaluate fast: generate $(1, 0)$(1,0), kill $(0, 0)$(0,0), propagate $(0, 1)$(0,1). A generate or a kill on the left decides the element alone; a propagate passes the lower span through. Condition: $p = a\oplus b$b, so $(1, 1)$ never occurs (with an OR propagate it does).
• 16 bits: Kogge–Stone $16 + 15 + 13 + 9 + 1 = 54$ elements in 5 levels, strict Brent–Kung 27 in 6. Condition: the carry-in counted as position 0.
• FN17-8’s two paths tie. With the example delays $t_{PG} = 2$2, $t_e = 4$ and $t_{sum} = 4\,\tau_{inv}$4τinv​: $s_8$ at $2 + 3\cdot4 + 4 = 18$ and $c_{out}$ at $2 + 4\cdot4 = 18\,\tau_{inv}$18τinv​. Condition: $t_{sum} = t_e$te​; the sum path wins when the XOR is slower than an element, the carry-out path otherwise.
• The bound ends the argument. $C_7$ spans 8 positions and $C_8$ nine, so no network makes them in fewer than 3 and 4 levels. Kogge–Stone meets both, so only faster blocks can shorten FN17-8’s path. Condition: two-input elements.
• A miswired adder is right only when every carry equals $c_{in}$cin​: no bit generates (with $c_{in} = 0$0) or none kills (with $c_{in} = 1$1). That is $2\cdot3^8 = 13{,}122$ of the 131,072 additions, $(3/4)^8 = 10.0\,\%$10.0%, and its $c_{out}$ is always right. Condition: only the sum wiring is wrong.
• In Brent–Kung the last sum can sit in the middle. At 16 bits, in the strict pattern, $s_{15}$ waits for $C_{14}$ at level 6, $2 + 24 + 4 = 30\,\tau_{inv}$30τinv​, while the top sum $s_{16}$ is ready at 22, because its carry $C_{15}$ comes straight from the up-sweep. Condition: a network whose carries are not all at their bounds.

Traps.

• Wiring each sum to its own column, $s_k = p_k\oplus C_k$Ck​, as the FN17-8 key does: every sum one position too high, and $s_1$ fed from the 0–1 output the key labels “C₁”. It gives $1 + 1 = 1$ and $0 + 0 + 1 = 0$0, is wrong on 117,950 of the 131,072 additions (90.0 %), and moves the critical path: $s_8$ would wait for $C_8$C8​, $22\,\tau_{inv}$22τinv​.
• Swapping an element’s inputs (the lower span on the left): the element does not commute.
• Feeding the sums from the network’s $P$ outputs instead of each bit’s own $p_k$pk​; taking the propagate as $a + b$b.
• Forgetting the carry-in, or entering it with a propagate of 1.
• Calling Brent–Kung faster. It has fewer elements, never fewer levels: on the board’s 8-bit network $C_7$ is 4 deep against Kogge–Stone’s 3, so $s_8$ arrives at 22 instead of $18\,\tau_{inv}$18τinv​.
• In a subtraction, forgetting $c_{in} = 1$1, or reading $c_{out} = 0$ as “no borrow”: $56 - 108$108, computed as $56 + 147 + 1$1, gives 204 with $c_{out} = 0$0, a borrow, so the result is $-52$−52.

Practice.

Paper	Part (points)	Full solution	Exam way
FN17	8 (15): an 8-bit parallel-prefix adder and its critical path	FD1, FN17-8	8
FD1 (added)	Variation 1: debugging the miswired adder; Variation 2: a subtraction through all 21 elements; Variation 3: sixteen bits, and the sum that comes last	V1, V2, V3	—

FN17-8 is the family’s only past-final part. The method is taught in Chapter 16: subtraction (§3), generate and propagate (§9), the radix-2 element and the $(c_{in}, 0)$ entry (§12–§13); and in Chapter 17: the element and its order (§1), carries as prefixes (§2), Kogge–Stone (§3), Brent–Kung (§4), the two compared (§5) and the whole prefix adder (§6).

Logarithmic shifters

Recognize. The picture: one 2:1 multiplexer block with its equation beside it. FN12-6 draws a box marked MUX with data inputs $a$ and $b$ from the top, a control $c$ from the left and the output $y$ below, and prints $y = ac + b\bar c$bcˉ. The phrases: “draw the (block-level) schematic of an 8-bit arithmetic right shifter using the basic multiplexer building block shown below”, “the shift amount should be determined by a three-bit control signal”. Other words of the family: “logical”, “arithmetic”, “rotate”, “logarithmic”, “barrel”, “stack height”. The marks are for the rows, the wiring of each mux’s two inputs, and what fills the vacated end. An encoded amount ($\log_2 N$log2​N select bits) means the logarithmic shifter; one select line per amount, one-hot, means the barrel shifter.

The family’s answer, since the paper prints only the mux: FN12-6’s shifter, 24 muxes and seven $A_7$ pads. Original figure ↗

Moves.

1. Read the mux equation: which input passes when the control is 1. FN12-6’s $y = ac + b\bar c$ passes $a$a.
2. Write the amount in binary, $s = \sum_k 2^kS_k$ ($4S_2 + 2S_1 + S_0$4S2​+ for 8 bits): one row of $N$ muxes per select bit, row $k$ shifting by $2^k$2k. Any order of rows works; keep the key’s ($S_0$S0​ first).
3. Wire row $k$k, mux $i$i: the control is $S_k$Sk​; the input that passes on a 1 takes $w_{i+2^k}$wi+2k​, the bit $2^k$ places to the left in the word $w$ entering the row; the other input takes $w_i$wi​, straight above.
4. The pads: every passes-on-1 input whose index $i + 2^k$ runs past $N - 1$1. Tie it to 0 (logical), to $A_{N-1}$ from the input (arithmetic), or to the bit the same row pushes out at the bottom, $w_{i+2^k-N}$ (rotate).
5. Count: $\log_2 N$ rows of $N$ muxes and $N - 1$ pads.
6. Check one word: a negative number shifted by an amount with two 1 bits, so that two rows pad; compare with $\lfloor x/2^s\rfloor$⌊x/2s⌋.
7. Transistor detail, if asked: with pass-transistor muxes a path is its driver plus one device per row. Break long stacks with rows of inverters, and invert the pads of every row that carries inverted data.
8. More than one kind of shift: keep the rows, and put a mux on each pad that chooses between the wrapped bit and one common fill, $A_{N-1}\cdot arith$arith.

Formulas.

• Memorize: a right shift by $s$ gives $Y_i = A_{i+s}$Ai+s​. The top $s$ places fill with 0 (logical), with the MSB (arithmetic, so a two’s-complement $x$ becomes $\lfloor x/2^s\rfloor$⌊x/2s⌋), or with the bits that fell off the bottom (rotate, $Y_i = A_{(i+s) \bmod N}$A(i+s)modN​).
• Derive: the logarithmic shifter. Path: (1) write $s = \sum_k 2^kS_k$∑k​2kSk​; (2) a shift by $2^j$ followed by one by $2^k$ is a shift by $2^j + 2^k$2k, so one row per bit, each shifting by $2^k$ or passing, gives every amount; (3) in row $k$k, mux $i$ takes $w_{i+2^k}$ on the input that passes when $S_k = 1$ and $w_i$ on the other: $\log_2 N$ rows of $N$ muxes.
• Derive: the pads. Path: (1) row $k$ has $2^k$ muxes whose shifted input would come from beyond the MSB; (2) $1 + 2 + \dots + N/2 = N - 1$ pads; (3) an arithmetic right shift never changes the MSB, so every row’s MSB is still $A_{N-1}$ and every pad can come straight from the input.
• Derive: the stack height. Path: (1) a pass-transistor mux puts one device in series for each row a bit crosses; (2) with its driver, $\log_2 N + 1$1; (3) an inverter after a row is a new driver, so a stack is 1 plus the rows since the last driver, and the data stay inverted until the next inverter.
• Memorize: the barrel shifter has one NFET per (output, amount) pair, $N^2$ in all, with one-hot selects: two lines on would fight, none on would float.

Shortcuts.

• The sizes: 8 bits, 3 rows, 24 muxes, 7 pads; 32 bits, 5 rows, 160 muxes, 31 pads. Condition: $N$ a power of 2.
• Check by value. FN12-6: $1001\,0111 = -105$ with $S = 110$ passes row $S_0$ unchanged, then becomes $1110\,0101$ and $1111\,1110 = -2 = \lfloor -105/64\rfloor$⌊−105/64⌋. With 0 pads the same rows give $0000\,0010 = 2$2: the pads alone make the shift arithmetic. Condition: two’s complement.
• The kind of shift lives in the pads. Three modes on FN12-6’s shifter cost one pad mux per pad and one fill mux, $24 + 7 + 1 = 32$ muxes, and lengthen a pad path from 4 to 5 devices in series (6 if the fill is a pass mux too). Condition: pass-transistor muxes, the fill from a restoring gate.
• Buffer every two rows to keep stacks at 3. At 32 bits the unbuffered stack is 6; inverter rows after $S_1$ and $S_3$ give 3, 3 and 2, and the output comes out true. Condition: a driver and at most two pass devices per stack.
• Pad parity: a row below an odd number of inverter rows pads with $\bar A_{N-1}$AˉN−1​. At 32 bits with inverters after $S_1$ and $S_3$S3​, rows $S_2$ and $S_3$ take $\bar A_{31}$ on their 12 pads and the other 19 pads take $A_{31}$A31​. Condition: the pads taken from the input.
• Log against barrel: at 32 bits the barrel shifter has $32 \times 32 = 1024$ NFETs and the log shifter $2 \times 160 = 320$ in its muxes, 3.2 times fewer, at the price of more devices in series. Condition: two NFETs per pass mux; the barrel’s select decoder and the log shifter’s inverter rows not counted.

Traps.

• Swapping the mux inputs: every select bit then acts inverted, so the circuit shifts by $7 - s$s, and $S = 000$ shifts by 7.
• Padding an arithmetic shift with 0 (2 instead of $-2$ in the check above), or taking a pad from the wrong side or from a row’s own output.
• A rotate’s pads from a fixed bit: each row wraps the bits it pushes out at the bottom.
• Inserting inverters and leaving the following rows’ pads true: a negative number then fills with zeros.
• One select line per amount where the paper says “a three-bit control signal”: that is the barrel shifter.
• Making the shared fill with a pass mux: one more device in every pad path.
• No key error in this family: FN12-6’s key draws the same shifter (one $A_7$ label in row $S_2$ is illegible).

Practice.

Paper	Part (points)	Full solution	Exam way
FN12	6 (15): an 8-bit arithmetic right shifter from 2:1 muxes	FD1, FN12-6	6
FD1 (added)	Variation 4: one shifter, three kinds of shift; Variation 5: thirty-two bits, buffered	V4, V5	—

FN12-6 is the family’s only past-final part. The method is taught in Chapter 17: the three kinds of shift (§7), the logarithmic shifter, its arithmetic pads and its stack height (§8), and the barrel shifter with one-hot selects (§9).

PLAs

Recognize. The picture: a grid. Vertical literal lines in threes ($\bar x_i$xˉi​, a ground line, $x_i$xi​); rows, each starting at a pull-up on the left; NFETs at some crossings, gated by a line; a second grid of columns at the right, gated by the rows, with or without inverters at the bottom. A static PLA’s pull-ups are PFETs with grounded gates (FN12-10a); a dynamic one’s are clocked by $\phi_{AND}$ and $\phi_{OR}$ϕOR​, with a clocked foot on each plane (FN19-6). FN19-6b adds two generator circuits, each with a box marked “replica AND row”. The phrases: “find f0 and f1 (Boolean equations) as a function of x0, x1, and x2”, “the OR plane does not being (sic) to evaluate until after the AND plane has evaluated”, “what is the logic function of this PLA”, “design a replica AND row, two instance (sic) of which can be used in the circuits below to generate $\phi_{AND}$ and $\phi_{OR}$ϕOR​”.

The family’s picture: FN19-6’s dynamic PLA, which is FN12-10a’s static one with a fourth row, clocked, and without output inverters. Original figure ↗

Moves.

1. Label the lines at the bottom: true, complement, ground. Find each device’s gate line, and look at the bottom of each column for an inverter.
2. Each row: list its devices’ lines, flip each literal, AND them. A device on $\bar x_0$ puts $x_0$ in the product.
3. Each column: OR the rows that have devices in it; complement the OR if the column has no inverter (FN19-6).
4. Simplify ($a + ab = a$a+a; $\bar a + ab = \bar a + b$b), then check two input rows by tracing them through the grid, not through your formula.
5. A dynamic PLA “if the clocks satisfy this relationship”: the race is avoided, so it computes what a static PLA with the same devices computes. Read it by moves 1–4.
6. The clocks: the AND plane evaluates first. $\phi_{AND}$ stays low at least as long as the slowest row’s precharge, and $\phi_{OR}$ rises only after the slowest row has evaluated.
7. A replica row: a copy of a real row, in the same array, with as many devices as the widest product and exactly one of them on (gate at $V_{DD}$VDD​), loaded like the most heavily loaded real row. One design serves both boxes.
8. Edge times, if delays are given: trace each generator from clk’s rising edge, then the valid time and the period.
9. Building one runs the other way: sums of products, the fewest shared rows, each true literal’s device on the complement line.

Formulas.

• Derive: a row’s product. Path: (1) any device that is on pulls the row low, so the row is high only when all its lines are 0; (2) row $= \overline{\ell_1 + \ell_2 + \dots}$ℓ1​+ℓ2​+…​; (3) by De Morgan, $= \bar\ell_1\,\bar\ell_2\cdots$ℓˉ1​ℓˉ2​⋯: the complement of each device’s line.
• Memorize: a column is the NOR of its rows. With an inverter the output is their OR; without one, the complement of the OR.
• Memorize: the two requirements, $t_{\phi_{AND}\ \mathrm{low}} \ge t_{pre}$ and $t(\phi_{OR}\!\uparrow) \ge t(\phi_{AND}\!\uparrow) + t_{eval}$teval​, with $t_{pre}$ and $t_{eval}$ the slowest row’s precharge and evaluate.
• Memorize: the slowest precharge belongs to the row with the most capacitance (the most devices); the slowest evaluate is a row discharging through one device.
• Derive: the generators’ edges, clk rising at 0. Path: (1) the NAND falls at once, $\phi_{AND}\!\downarrow = t_{NAND}$tNAND​; $\overline{\mathrm{clk}}$ falls, the replica precharges, the inverter falls and the NAND rises, so $\phi_{AND}\!\uparrow = 2t_{inv} + t_{pre} + t_{NAND}$tNAND​, low for $2t_{inv} + t_{pre}$tpre​; (2) the second replica and its inverter follow $\phi_{AND}$ϕAND​: $\phi_{OR}\!\downarrow = \phi_{AND}\!\downarrow + t_{pre} + t_{inv}$tinv​, $\phi_{OR}\!\uparrow = \phi_{AND}\!\uparrow + t_{eval} + t_{inv}$tinv​; (3) valid one OR-plane evaluate later; the period adds the latch’s setup. The margins, $2t_{inv}$ and $t_{inv}$tinv​, are gate delays only.
• Memorize: a static (pseudo-NMOS) PLA has one NFET per programmed crossing, one PFET load per row and per column, and two devices per output inverter.

Shortcuts.

• FN12-10a’s two outputs are one function: $f_1 = \bar x_2 + x_0x_1x_2 = x_0x_1 + \bar x_2 = f_0$f0​, 1 on $x_0x_1x_2 =$ 000, 010, 100, 110 and 111. Condition: none; a PLA programmed by hand need not be minimal, so always try to simplify.
• FN19-6’s $y_0$ is the complement of FN12-10a’s $f_0$ (the same two rows, no inverter): $y_0 = x_2(\bar x_0 + \bar x_1)$xˉ1​), 1 on $x_0x_1x_2 =$ 001, 011 and 101; $y_1 = \bar x_1x_2$xˉ1​x2​, 1 on 001 and 101. Condition: the clocks meet both requirements.
• One replica row does both jobs: three devices, one on, precharge like the heaviest row and evaluate like the slowest. The one new condition: clk’s low phase must let the upper replica evaluate again, $2t_{inv} + t_{eval}$ (240 ps with the example delays below). Condition: FN19-6b’s single design.
• The example delays ($t_{inv} = 20$tinv​=20, $t_{NAND} = 30$30, $t_{pre} = 150$150, $t_{eval} = 200$200, the OR plane 150, setup 50 ps, for example): $\phi_{AND}$ low 30–220 ps (190 against 150), the slowest row done at 420, $\phi_{OR}$ low 200–440 ps, valid at 590, period 640 ps.
• A replica keeps its margins at every corner; a fixed delay does not. With the gates 10 % and the rows 30 % slower, the period grows to 804 ps (25.6 %) and the margins become 44 and 22 ps; an inverter chain tuned to the typical 220 ps gives 242 ps where the slowest row needs 260: 18 ps short. Condition: rows and gates slow by different amounts.
• Parity costs a row per minterm. A full adder needs $3 + 4 = 7$ rows, no fewer, and 38 devices when static ($18 + 7$18+ NFETs, 9 loads, 4 in the inverters). Condition: a row is shared only where its product is an implicant of both outputs.

Traps.

• Reading a device on $x_i$ as the literal $x_i$xi​: it puts $\bar x_i$ in the product.
• Writing the OR form for FN19-6, as if it had FN12-10a’s inverters: that is the complement of the right answer on every input.
• One clock on both planes: every row is high when evaluation starts, so every column with a device discharges for good. FN19-6 would read $y_0 = y_1 = 0$ on every input, 5 of its 16 entries wrong.
• A replica that copies a typical row, or has all its devices on for $\phi_{OR}$ (the fastest evaluate, not the slowest).
• A replica without the real rows’ load: as many OR-plane gates as the most heavily loaded row ($P_1$P1​ drives two in FN19-6), and the full row wire.
• Two different rows, the lecture’s pair: they work, but FN19-6b asks for one design used twice.
• No key error in this family so far: FN12-10a’s key agrees but leaves $f_1$ unsimplified; FN19 has no key, and its unofficial solutions agree.

Practice.

Paper	Part (points)	Full solution	Exam way
FN12	10a (9): read a static PLA	FD1, FN12-10a	10a
FN19	6a (10): a dynamic PLA’s function, with no output inverters	FD1, FN19-6a	6a
FN19	6b (8): a replica AND row for both clocks	FD1, FN19-6b (clock-generation card)	6b
FD1 (added)	Variation 6: a full adder as a PLA; Variation 7: the replica clocks at a slow corner	V6, V7	—
FN12	10d (9): a ROM, a decoder into a NOR plane, read without inverters	FM1, FN12-10d (memory-addressing card)	10d

The method is taught in Chapter 18: sums of products from NORs (§1), the pseudo-NMOS NOR (§2), programming a PLA (§3) and reading one back (§4), Espresso (§5), the dynamic PLA and its race (§7), self-timed clocks (§8) and replica rows (§9, with one design for both generators).

SRAM access path

Recognize. The picture: a row of five transistor-level stages with every width printed in µm. A domino NOR predecoder has its precharge PFET and foot on $\bar\phi_2$ϕˉ​2​; its output inverter sends arrows marked “256X fanout”; then come a race-based NOR on $\bar\phi_2$ϕˉ​2​, a stage footed on $\phi_1$ϕ1​, and an inverter into a capacitor marked “wordline load”. The phrases: “the wordline drives 256 SRAM cells with $1\mu m$ access transistors and 100 fF of wire capacitance”, “estimate the delay of the decode path … (for the critical evaluation edge) as a multiple of the fanout-of-one (FO1) delay, $\tau_1$τ1​”, “the bitline must be pulled from $V_{DD}$ to $V_{DD}/2$ for detection”, “if the fanout-of-four delay (FO4), $\tau_4\cong3\tau_1$3τ1​, what is the approximate memory access time”, “a cycle time of 12-15 FO4”, “Name one technique for improving SRAM access time”. On a clock, the same path belongs to the dynamic row-decoder card.

The family’s picture: FN10-5’s decode path, a domino predecoder, a race-based NOR, a clock-qualified stage and the word-line driver. Original figure ↗

Moves.

1. Name each stage’s critical edge. The dynamic stages (the domino NOR, the race NOR, the $\phi_1$ stage) fall on evaluation; the inverters after them rise.
2. Each stage’s drive. A falling stage pulls down through one input NFET in series with its foot (one input high is the worst case; parallel inputs do not help): $W_{eq} = 1/\sum(1/W_i)$1/∑(1/Wi​), normalized input $3W_{eq}$3Weq​. A rising inverter pulls up through its PFET: $1.5W_p$1.5Wp​. The precharge PFET is off on the evaluation edge, so leave it out.
3. Each stage’s load: the gates its output drives, times the fan-out. An inverter’s input is both its devices; a dynamic node drives only the NFET it gates (stage III drives stage IV’s 20 µm NFET, not its foot). Use the printed fan-out and say so.
4. The word line: $C_{WL} = C_{wire} + N_{cols}\cdot 2W_aC_g$2Wa​Cg​, two access gates per cell, converted to µm at $C_g$Cg​.
5. Divide and add, keeping two decimals and adding the unrounded gains. If the clocking matters, split the sum at $\phi_1$ϕ1​: the stages before it (I–III) and after it (IV–V).
6. The bitline: the cell’s access and pull-down NFETs in series, $C_{BL}/C_g$ over $3W_{eq}$3Weq​, to $V_{DD}/2$VDD​/2. Scale for the swing the detector needs.
7. The access time: decode plus bitline; then FO4 at the paper’s $3\,\tau_1$3τ1​; then cycles, dividing by 15 and by 12 FO4.
8. The remedy attacks the larger term, the bitline: a sense amplifier at a 50–100 mV swing, shorter bitlines (banks), a skewed detector, self-timing, pipelining.

Formulas.

• Derive: a falling stage’s gain, $g = C_{out}/(3W_{eq})$Cout​/(3Weq​). Path: (1) devices in series add resistance, so the input NFET and the foot act as one NFET of $W_{eq} = 1/\sum(1/W_i)$1/∑(1/Wi​); (2) that drives like the inverter with NFET $W_{eq}$ and PFET $2W_{eq}$2Weq​, input $3W_{eq}$3Weq​; (3) a stage’s delay in $\tau_1$ is its load over that input.
• Derive: a rising inverter’s gain, $g = C_{out}/(1.5W_p)$Cout​/(1.5Wp​). Path: (1) a PFET is as strong as an NFET of half its width; (2) the matching inverter has NFET $W_p/2$ and PFET $W_p$Wp​, input $1.5W_p$1.5Wp​; (3) divide the load by it.
• Memorize: $C_{WL} = C_{wire} + N_{cols}\cdot 2W_aC_g$2Wa​Cg​. A 6T cell hangs two access gates on its word line, one to bit and one to $\overline{\text{bit}}$bit.
• Derive: the bitline, $t_{BL} = (C_{BL}/C_g)/(3W_{eq})$ with $W_{eq} = W_aW_{pd}/(W_a + W_{pd})$Wpd​). Path: (1) the cell’s 0 node joins the bitline to ground through the access and the pull-down NFET in series; (2) so the cell is one more stage, a weak drive against the column’s capacitance in µm; (3) the gain model’s delay is to the 50 % point, which is $V_{DD}/2$VDD​/2.
• Derive: a smaller swing, $t(\Delta V) = t_{BL}\,\Delta V/(V_{DD}/2)$tBL​ΔV/(VDD​/2). Path: (1) near $V_{DD}$ the cell’s current $I$ is about constant; (2) the time for a swing $\Delta V$ is $C_{BL}\Delta V/I$CBL​ΔV/I; (3) so it scales with $\Delta V$ΔV, and $t_{BL}$ is the time for $V_{DD}/2$VDD​/2.
• Memorize: $t_{access} \approx t_{decode} + t_{BL}$tBL​, because the bitline starts only when the word line is up; FO4 $\approx 3\,\tau_1$ when the paper says so. $\mathrm{FO4}/\mathrm{FO1} = (4\eta + 1)/(\eta + 1)$ with $\eta = C_g/C_d$Cg​/Cd​: 4 with no drain capacitance, 3 at $\eta = 2$2.

Shortcuts.

• FN10-5a’s five gains: $115/30 = 3.83$3.83, $1024/150 = 6.83$6.83, $20/6 = 3.33$3.33, $115/30 = 3.83$ and $562/150 = 3.75$3.75, $21.57\,\tau_1$ in all: 13.99 before $\phi_1$ (I–III), 7.58 after it (IV–V). Condition: the printed widths and fan-out.
• A size check: the gains multiply to about 1253, and five equal gains with that product, $1253^{1/5} = 4.16$4.16, sum to $20.8\,\tau_1$20.8τ1​, the least possible; 21.57 is 3.6 % above. Condition: the first stage’s input and the word-line load fixed; resizing the inner stages changes the gains, not their product.
• The topology’s fan-out: 8 row bits in 2-bit groups make 16 lines, each shared by $2^{8-2} = 64$ race NORs, not 256. Stage II becomes $256/150 = 1.71$ and the path $16.45\,\tau_1$16.45τ1​. Condition: answer with the printed 256 and give this as a remark.
• Rows and columns load different stages. More rows load the predecoder (stage II) and the bitline; more columns load the word line (stage V); stages I, III and IV see neither. At 512 × 512 the bitline doubles, $83.3 \to 166.7\,\tau_1$166.7τ1​, and stage V goes from 3.75 to 7.49. Condition: the same circuits, wire capacitance in proportion to length.
• The bitline decides the verdict. At $V_{DD}/2$ it is 79 % of FN10-5’s access, and alone it is $83.3\,\tau_1 = 27.8$ FO4, already about two cycles of 12–15 FO4. Condition: a detector that waits for $V_{DD}/2$VDD​/2.
• After a sense amplifier, the decoder is the target. At 2.5 V a skewed inverter switching at $0.8\,V_{DD}$ waits for 0.5 V, $33.3\,\tau_1$33.3τ1​; a 100 mV sense amplifier needs $6.67\,\tau_1$6.67τ1​, and the access falls to $28.2\,\tau_1 = 9.4$ FO4, 76 % of it decode. Condition: a near-constant cell current near $V_{DD}$VDD​.

Traps.

• One access gate per cell on the word line, as FN10-5a’s key writes: 612 fF, stage V 2.04, a path of $19.86\,\tau_1$ (the key’s rounded gains; 19.87 unrounded), $1.71\,\tau_1$ short. It carries into 5c: the key’s $103.16\,\tau_1 \cong 34$ FO4, against $104.9\,\tau_1 = 35.0$ FO4.
• Forgetting the foot in series (stage I would come out $115/60 = 1.92$1.92, half its gain), or counting the precharge PFET as drive or load.
• $3W_p$ instead of $1.5W_p$ for a rising inverter: it halves stages II and V.
• The bitline through the access NFET alone: $125/3 = 41.7\,\tau_1$41.7τ1​, half of the right 83.3.
• FO4 taken as $4\,\tau_1$ (“fan-out of four”): 26.2 FO4. The paper fixes 3.
• Answering only 5c’s first question, as the key does: it also asks why 35 FO4 is a challenge (2.3–2.9 cycles, with an access in most cycles) and for a technique.

Practice.

Paper	Parts (points)	Full solution	Exam way
FN10	5a (10): the decode path’s delay in $\tau_1$	FM1, FN10-5a	5a
FN10	5b (10): the bitline to $V_{DD}/2$	FM1, FN10-5b	5b
FN10	5c (6): the access time in FO4, the cycle and a remedy	FM1, FN10-5c	5c
FM1 (added)	Variation 1: a 512 × 512 array from the same circuits; Variation 2: the detector decides the bottleneck	V1, V2	—

FN10-5 is the family’s only past-final part; FM1’s Variation 6 puts its path on a clock. The method is taught in Chapter 19: the 6T cell (§1), the bitline’s delay (§7), sense amplifiers (§10), predecoding counts (§11), the decode path’s delay (§12) and the access time (§13). The gain rule is Chapter 8 §1, a dynamic stage’s drive Chapter 12 §2, FO4 against FO1 Chapter 5 §13, and the array’s shape, which sets the bitline’s length, Chapter 18 §10.

Memory addressing and ROM decoders

Recognize. Two kinds of question. FN10-10 prints no figure: “assume that I have a memory with a logical organization of $4k\times16bits$16bits”, “how many bits of address do I need?”, “if the internal array is organized to be $256\times256$256, how many bits of the address are needed for column multiplexing? Explain.” FN12-10d prints a decoder-driven ROM: eight 3-input ANDs down the left on $x_1$x1​, $x_2$x2​, $x_3$x3​, their bubbles in a binary count, each driving a row; three columns $y_1$y1​, $y_2$y2​, $y_3$y3​, each topped by a PFET with a grounded gate; ground lines between row pairs, and NFETs from a column to a ground line, each gated by a row. The phrase: “complete the logic table shown below”, whose input columns are printed $x_1$x1​, $x_2$x2​, $x_3$x3​. Nothing is timed; the marks are for the counting and for reading the circuit exactly. FN12-10a on the same page is a PLA (PLA card); here a full decoder raises exactly one row.

The family’s picture: FN12-10d’s ROM, a full 3-to-8 decoder into three pseudo-NMOS columns with no output inverters. Original figure ↗

Moves.

1. Address bits $= \log_2 N_w$log2​Nw​, with k = 1024. The word width does not enter.
2. Row bits $= \log_2 R$log2​R.
3. Column bits: a row holds $C/W$ words, so a $C/W$C/W:1 multiplexer on $\log_2(C/W)$ bits, decoded into $C/W$ one-hot selects. “Explain” asks for the words per row.
4. Check that $R\cdot C = N_wW$ and that row bits plus column bits give move 1.
5. Predecoding, if asked: $n$ row bits in groups of $k$ give $(n/k)\,2^k$ lines; each row decoder takes $n/k$ of them; each line feeds $2^{n-k}$ decoders.
6. A ROM, the decoder’s order. An AND is high on the one input with 0 at its bubbles and 1 elsewhere. Write down which row decodes which input, and the bit order ($x_1$x1​ most significant in FN12-10d).
7. The devices by row. Each NFET belongs to the row its gate bar crosses; the ground line beside it is only its source.
8. Each output word: the selected row’s devices make 0s; every other column stays 1.
9. Check by counting: the table has as many 0s as the circuit has devices. Then read each column down for its function.

Formulas.

• Memorize: address bits $= \log_2 N_w$log2​Nw​; k is 1024 in memory sizes ($1k = 2^{10}$1k=210, $4k = 2^{12}$212, $16k = 2^{14}$214).
• Derive: the split, $\log_2 N_w = \log_2 R + \log_2(C/W)$log2​(C/W). Path: (1) each row holds $C/W$ words; (2) a word is named by its row ($\log_2 R$log2​R bits) and its place on the row ($\log_2(C/W)$log2​(C/W) bits); (3) $R\cdot C/W = N_w$ because $R\cdot C = N_wW$Nw​W, so the two add to $\log_2 N_w$log2​Nw​.
• Derive: the predecode counts. Path: (1) $k$ bits decode to $2^k$ one-hot lines, in $n/k$ groups; (2) a row decoder takes one line from each group, $n/k$ inputs; (3) a line fixes $k$ bits and leaves $n - k$ free, so $2^{n-k}$ decoders share it.
• Derive: the ROM rule, $y_j(x) = 0$ exactly when a device sits at (row $x$x, column $j$j). Path: (1) a pseudo-NMOS column is held high by its always-on PFET and pulled low by any conducting NFET, which wins the ratio: it is the NOR of its rows; (2) a full decoder raises exactly one row; (3) so only that row’s devices conduct: their columns read 0, every other column 1.
• Memorize: the column multiplexer’s selects are a full decode of the column bits; each passes one $W$-bit word, with an NFET on bit and one on $\overline{\text{bit}}$ per column, $2W$ NFETs a select.

Shortcuts.

• FN10-10 in one line: $4096 = 2^{12}$212, 12 bits; 256 rows, 8 bits; $256/16 = 16$ words a row, 16:1, 4 bits; $8 + 4 = 12$12. Condition: every count a power of two.
• Count from a size you know: 1k words take 10 bits, and each doubling adds one: 4k takes 12, 16k takes 14.
• Column bits by subtraction: address bits minus row bits, $12 - 8 = 4$4. Condition: the array holds the memory exactly ($256 \times 256 = 4096 \times 16$256×16).
• FN12-10d’s table: for $x_1x_2x_3 =$ 000, …, 111 the outputs $y_1y_2y_3$ are 001, 111, 010, 111, 011, 110, 011, 101. Down the columns: $y_1 = x_3$ (its devices sit on the four rows with $x_3 = 0$0); $y_2$ is 0 only at 000 and 111; $y_3$ only at 010 and 101. Condition: the bubbles in binary order, $x_1$ the most significant bit.
• Programming runs backwards: put a device at every 0 of the table. A function that is 0 on half its inputs puts half the rows on its column: the Gray-code ROM on FN12-10d’s decoder needs $3 \times 4 = 12$ devices. Condition: a NOR ROM with no output inverters.
• The shape sets the bitline. A $16k \times 32$ memory as 512 × 1024 splits 9 + 5 (32:1), as 1024 × 512 10 + 4 (16:1); at FN10-5b’s 250 fF per 256 rows their bitlines take 166.7 and $333.3\,\tau_1$333.3τ1​. Condition: the bitline’s capacitance in proportion to its rows; the wider array pays a few $\tau_1$ on its heavier word line.

Traps.

• Counting bits instead of words: $4096 \times 16 = 65{,}536 = 2^{16}$216, “16 bits”.
• Column bits as $\log_2 C$log2​C: $\log_2 256 = 8$8, and $8 + 8 = 16$ bits name 16 times as many things as the memory holds. The multiplexer picks words, not columns.
• Reading a ROM device as a 1, a “programmed bit”: here it pulls its column low. Programming by the 1s gives the complement.
• Adding output inverters, as FN12-10a’s PLA has: FN12-10d has none, and inverters would flip all 24 entries.
• Giving a device to the row whose ground line it sits on instead of the row whose gate bar crosses it.
• No key error in this family: the FN10-10a–b and FN12-10d keys agree with the re-solves.

Practice.

Paper	Parts (points)	Full solution	Exam way
FN10	10a (4): the address bits for $4k \times 16$	FM1, FN10-10a	10a
FN10	10b (6): the column-multiplexing bits of a 256 × 256 array	FM1, FN10-10b	10b
FN12	10d (9): a decoder-driven ROM’s table	FM1, FN12-10d	10d
FM1 (added)	Variation 3: a $16k \times 32$ memory, from address to array; Variation 4: programming the ROM, and a fault	V3, V4	—

The method is taught in Chapter 18 §10: the array and logical against physical organization; and in Chapter 19: column multiplexing (§9) and decoders (§11), with predecoding counts and a decoder driving a ROM. The pseudo-NMOS column is Chapter 10 §10.

Dynamic row decoders

Recognize. The picture: one decoder per word line, each a dynamic NOR of two address lines with a PFET and a foot on $\bar\phi_2$ϕˉ​2​, feeding a second stage (an NFET gated by the first stage’s node, a foot on $\phi_1$ϕ1​) and an inverter to the word line. Beside them, one SRAM column: precharge PFETs on $\bar\phi_2$ϕˉ​2​; write stacks enabled by an AND of $\phi_1$ and write, with data_in on the $B$ side and its complement on the $\overline B$ side; an inverter from $\overline B$ to data_out. Below, the given waveforms phi1, phi2, x0, x1, write and data_in, with empty rows to fill. The phrases: “a more area-efficient dynamic decoder”, “we show only one column of the SRAM”, “for the input waveforms shown, find the waveforms at $W_0$W0​, $B$B, $\overline B$B, and data_out”, “what criterion does the dynamic decoder put on the nonoverlap window of phi1 and phi2?”. FN10-5’s stages III and IV are the same race-based NOR.

The family’s picture: FN17-6’s four race-based NORs and one column. Stage 2’s PFET is on $\bar\phi_2$ϕˉ​2​, not on $\phi_1$ as on the lecture’s board. Original figure ↗

Moves.

1. Read each decoder’s inputs. A row is selected when every input of its NOR is 0, exactly one row per address. In FN17-6, W0 = NOR($\bar x_0$xˉ0​, $\bar x_1$xˉ1​), W1 = NOR($\bar x_0$xˉ0​, $x_1$x1​), W2 = NOR($x_0$x0​, $\bar x_1$xˉ1​), W3 = NOR($x_0$x0​, $x_1$x1​); the scan hides the bars on $x_1$ at W0 and W2.
2. Read every device’s clock, then walk the four intervals of a cycle: $\phi_2$ high (precharge); the gap to $\phi_1\!\uparrow$ (stage 1 evaluates, and every unselected row’s node falls); $\phi_1$ high (stage 2 fires on the selected row, and the column reads or writes); the gap to $\phi_2\!\uparrow$ϕ2​↑.
3. The word line rises just after $\phi_1\!\uparrow$ and falls when stage 2’s PFET turns on: at $\phi_1\!\downarrow$ if that PFET is on $\phi_1$ (the lecture’s), at $\phi_2\!\uparrow$ if it is on $\bar\phi_2$ (FN17-6).
4. The bitlines: both high in precharge, floating high in the gap. In $\phi_1$ a write pulls one low fast through its stack; a read lets the cell pull its 0 side low slowly through its two NFETs. A low bitline stays low until $\phi_2$ rises.
5. The detector: trace its polarity from the side it hangs on.
6. The criterion: the gap from $\phi_2\!\downarrow$ to $\phi_1\!\uparrow$ must cover every stage ahead of the clock-qualified one: stage 1’s evaluation in FN17-6; the domino predecoder, its inverter and the race NOR (I–III) in FN10-5. Give the reason: the race onto a second word line.
7. The address window, if asked: stable from $\phi_2\!\downarrow$ to $\phi_1\!\downarrow$ϕ1​↓, changed while $\phi_2$ is high.
8. In picoseconds, if gains are given: the gap holds the stages before $\phi_1$ϕ1​; $\phi_1$ holds the rest of the path, the bitline’s swing and the sense amplifier; precharge needs its own time; the period is the sum.

Formulas.

• Derive: the race condition, $t_{NO} = t(\phi_1\!\uparrow) - t(\phi_2\!\downarrow) \ge \sum t_i$ over the stages ahead of the clock-qualified one. Path: (1) stage 1 evaluates from $\phi_2\!\downarrow$ϕ2​↓, and every unselected row’s node starts high and needs $t_{eval}$ to fall; (2) stage 2’s foot opens at $\phi_1\!\uparrow$ and discharges $Y$ on every row whose node is still high, and a fallen dynamic node cannot recover before the next precharge; (3) so the gap must cover stage 1’s evaluation and every stage that feeds it from $\phi_2\!\downarrow$ϕ2​↓: a domino predecoder and its inverter too, I–III in FN10-5, whose inverter (6.83) is the largest term.
• Memorize: a dynamic NOR row is selected when all its inputs are 0, so the row for an address takes the complement of each address bit.
• Memorize: FN17-6’s column: a write of data_in = 1 pulls $B$ low, of 0 pulls $\overline B$ low; a read pulls the cell’s 0 side; data_out, an inverter on $\overline B$B, reports the cell’s $B$ side, the complement of the data written.
• Derive: the address window, $\phi_2\!\downarrow$ to $\phi_1\!\downarrow$ϕ1​↓. Path: (1) a dynamic gate’s input must not rise while it evaluates (it would discharge the selected row’s node), and one that falls cannot recharge a node already down; (2) stage 1 evaluates from $\phi_2\!\downarrow$ϕ2​↓, and the selected row’s node must stay high while stage 2’s foot is on, until $\phi_1\!\downarrow$ϕ1​↓; (3) so the address is held over that span and changed in precharge.
• Derive: the clock budget, $T \ge t_{\phi_2} + t_{NO} + t_{\phi_1}$tϕ1​​. Path: (1) precharge needs $\phi_2$ high; (2) the gap holds the stages before the clock qualification; (3) with the word line falling at $\phi_1\!\downarrow$ϕ1​↓, $\phi_1$ holds the remaining stages, the bitline’s swing and the sensing.

Shortcuts.

• One address, one row, every cycle. FN17-6a’s $x_0 = x_1 = 1$ selects W0 throughout. W0 is high in $\phi_1$ and the gap after it; $B$ is low in the same intervals (steeply in the first cycle, the write; more gently in the reads); $\overline B$ stays high and data_out low throughout. Condition: stage 2’s PFET on $\bar\phi_2$ϕˉ​2​.
• The column returns the complement. Write 0 at $x_1x_0 = 01$ and 1 at 10, then read both (FM1’s Variation 5): word lines W1, W2, W1, W2; data_out 1, 0, 1, 0. An inverter on $B$ instead (or the data_in inverter moved to the other stack) reads back 0, then 1. Condition: the data stack on $B$B, the detector on $\overline B$B.
• FN10-5’s path on a clock (FM1’s Variation 6, $\tau_1 = 30$ ps, for example). The gap holds I–III, $13.99\,\tau_1 = 420$ ps; $\phi_1$ holds IV, V, a 100 mV swing and $5\,\tau_1$ of sensing, $3.83 + 3.75 + 6.67 + 5 = 19.25\,\tau_1 = 577$ ps; with 300 ps of precharge the period is 1297 ps (771 MHz), 32 % of it gap. With the topology’s fan-out of 64 the gap is 266 ps and the period 1144 ps. Condition: the lecture’s stage 2 on $\phi_1$ϕ1​, no second gap.

Traps.

• Letting W0 fall with $\phi_1$ϕ1​, as on the lecture’s board: FN17-6’s stage 2 PFET is on $\bar\phi_2$ϕˉ​2​, so W0 stays up until $\phi_2$ rises.
• Reading the scan’s W0 as NOR($\bar x_0$xˉ0​, $x_1$x1​): it duplicates W1, and no row answers $x_0 = x_1 = 1$1.
• Assuming data_out = data_in. With FN17-6’s wiring a written 1 reads back as 0; FN17-6a writes only a 1, so only a trace through both values shows it.
• Putting the criterion on the gap after $\phi_1$ falls, where nothing races.
• Holding the address only until $\phi_1\!\uparrow$ϕ1​↑: stage 2’s foot is on $\phi_1$ϕ1​, so the selected row’s node must stay high until $\phi_1\!\downarrow$ϕ1​↓.
• One slope for writes and reads: a stack pulls a bitline down fast, the cell slowly.
• Copying the FN17-6a key’s later W0 pulses, which drift off their edges (the third a whole $\phi_1$ pulse late), or its FN17-6b criterion, which gives no reason: align every pulse to its edges, and give the race.

Practice.

Paper	Parts (points)	Full solution	Exam way
FN17	6a (about 8): the waveforms at W0, $B$B, $\overline B$ and data_out	FM1, FN17-6a	6a
FN17	6b (8): the criterion on the non-overlap window	FM1, FN17-6b	6b
FM1 (added)	Variation 5: four cycles at two addresses; Variation 6: the decode path as a clock budget	V5, V6	—

FN17-6 is the family’s only past-final part. The method is taught in Chapter 19: two phases for the periphery (§6), the read column (§7), the write column (§8) and the race-based NOR (§12), with its circuit and the race and the clock that removes it. The race between dynamic stages is Chapter 11 §5; the non-overlap gap is Chapter 14 §3, and the circuits that make it are on the clock-generation card.

Elmore wires

Recognize. The picture: a wire drawn as thick lines from a driver at A to one or more receivers (B, C) with a capacitor at each, the lengths in µm written along every run, often with a riser (“up 1000 µm, then 2000 µm across”); or one straight point-to-point wire from A to B. Then a line of technology data: a width (0.4 µm), a sheet resistance (0.076 Ω/square) and a capacitance per length, either one number (0.1 fF/µm) or a formula in the width ($0.04 + 0.15W$0.04+ fF/µm). The phrases: “calculate the Elmore delay from A to B”, “widen the wire from 0.4 µm to 4 µm and recompute”, “explain why such wire ‘tapering’ might be advantageous”, “would resistance have to be considered”. FN12-9a prints a hint that quotes $\tfrac12\mathcal{R}\mathcal{C}L^2$ alone.

The family’s picture: FN10-8’s tree, a trunk A–X and two branches, each with its riser. Original figure ↗

Moves.

1. Per-length values first. $\mathcal{R} = R_\square/W$ for each width, and $\mathcal{C}$ from the paper’s number or from its formula at that width. Work in Ω and fF; Ω·fF ÷ 1000 is ps.
2. Draw the path from the driver to the receiver the question names, and cut it at every branch point, every width change and every lumped load. Count the risers.
3. Each path segment’s totals, $R_k = \mathcal{R}L_k$ and $C_k = \mathcal{C}L_k$CLk​.
4. Each segment’s $C_{down,k}$Cdown,k​, walking back from the receiver: its load, then each later segment, and each side branch (its wire and its loads) at the node where it leaves the path.
5. Sum $R_k(\tfrac12C_k + C_{down,k})$Cdown,k​).
6. Check by the other grouping: the path’s own $\tfrac12RC$21​RC, plus the receiver’s load through the whole path, plus each side branch or lumped load times the resistance it shares with the path.
7. Widening or tapering. Recompute $\mathcal{R}$ and $\mathcal{C}$ for the changed segment. Its own term changes, and its new capacitance enters the $C_{down}$ of every segment before it. A taper is two segments in series. Give the comparison and the reason, not only the number.
8. “Must resistance be considered?” Compare $T_{Elmore}$ with the edge time; if none is given, with the FO1 delay, since edges last a few of them. Explain both effects: the edge arrives late, and its slope is stretched by about $2T_{Elmore}$2TElmore​.

Formulas.

• Memorize: $R = R_\square L/W$ and $\mathcal{R} = R_\square/W$R□​/W; $\mathcal{C} = C_{areal}W + C_{fringe}$Cfringe​, a plate term from the wire’s bottom face that grows with $W$ and a fringe term from its sides that does not; about 0.1 fF/µm for a minimum wire.
• Memorize: the Elmore rule. Every capacitance counts times the resistance it shares with the path from the driver to the receiver, and the result is quoted as the delay, with no ln 2.
• Derive: the uniform line, $T_{Elmore} = \tfrac12\mathcal{R}\mathcal{C}L^2 + \mathcal{R}L\,C_{load}$RLCload​. Path: (1) a slice $\mathcal{C}\,dx$ at distance $x$ charges through $\mathcal{R}x$Rx; (2) $\int_0^L \mathcal{R}x\,\mathcal{C}\,dx = \tfrac12\mathcal{R}\mathcal{C}L^2$21​RCL2; (3) the load at the far end sees all of $\mathcal{R}L$RL.
• Derive: the segment form, $T_{Elmore}(A{\to}B) = \sum_{k\,\in\,\text{path}} R_k(\tfrac12C_k + C_{down,k})$Cdown,k​). Path: (1) every capacitance counts with the path resistance it shares with B’s path; (2) collect the terms of each path resistor: $R_k$ multiplies everything beyond its far end, side branches included; (3) its own capacitance sees on average half of it. It holds for grounded capacitance and one pole; off-path resistance never appears.
• Derive: widening. Path: (1) $\mathcal{R} = R_\square/W$R□​/W; (2) $\mathcal{C} = C_{areal}W + C_{fringe}$Cfringe​; (3) $T(W) = \tfrac12R_\square(C_{areal} + C_{fringe}/W)L^2 + (R_\square/W)L\,C_{load}$(R□​/W)LCload​. The intrinsic term falls only to the floor $\tfrac12R_\square C_{areal}L^2$21​R□​Careal​L2.
• Derive: two segments (a taper), from the segment form: $T = \tfrac12R_1C_1 + R_1(C_2 + C_{load}) + \tfrac12R_2C_2 + R_2C_{load}$R2​Cload​, with segment 1 at the driver.
• Memorize: the resistance test. If $T_{Elmore} \ll t_r$tr​, the wire is a lumped capacitance; if $T_{Elmore} \gtrsim t_r$tr​, include $R$ (delay, slew, shielding).

Shortcuts.

• A lumped load costs its capacitance times the resistance it shares, and nothing else. FN10-8b: each 200 fF adds $760\ \Omega \times 200\ \text{fF} = 152$ ps on B’s path and $380\ \Omega \times 200\ \text{fF} = 76$ ps on C’s branch, so 522.5 ps becomes 750.5 ps. Condition: the sizes and the other loads stay as they were.
• A side branch costs its whole capacitance times the resistance up to where it leaves. In FN10-8a that is $380\ \Omega \times 500\ \text{fF} = 190$ ps of the 522.5 ps, from a wire that does not lead to B.
• A one-line bound: all the capacitance through the whole path resistance. FN10-8a: $1100\ \text{fF} \times 950\ \Omega = 1045$ ps, at least the 522.5 ps. Condition: no capacitance sees more than the path’s resistance.
• Widen the segment nearest the driver, because its resistance multiplies the most capacitance. FN19-7d: the trunk’s term falls from 380 to 37.1 ps and the branch’s 142.5 ps stays, so the delay is 179.6 ps. Condition: the widened segment is the first, so no earlier term sees its larger capacitance. The bill is capacitance: the tree holds 3980 fF instead of 1100 fF (loads included).
• Widening has a floor. FN12-9’s wire gives $T(W) = 91.2 + 33.44/W$ ps, so no uniform width beats 91.2 ps, while the taper reaches 82.46 ps. Condition: the areal-plus-fringe law.
• Taper wide near the driver. It wins while the load is small next to the wire’s own capacitance (30 fF against 1480 fF in FN12-9c).
• No edge time given? Count FO1 delays. FN19-7c: 522.5 ps is 10.45 FO1 delays of 50 ps, so resistance matters.

Traps.

• Forgetting the risers: FN10-8’s X–B is 1000 µm up and 2000 µm across, 3000 µm of wire.
• Putting a side branch’s own resistance into the sum, or leaving its capacitance out (332.5 ps instead of 522.5 ps in FN10-8a).
• Dropping the ½, or squaring $L$ in the load term.
• Obeying FN12-9a’s hint literally: $\tfrac12\mathcal{R}\mathcal{C}L^2 = 152$ ps leaves out the 22.8 ps load term (174.8 ps in all).
• Keeping 0.1 fF/µm after widening when the paper gives $\mathcal{C}(W)$C(W): 17.48 ps instead of 99.56 ps in FN12-9b, 157.7 ps instead of 179.6 ps in FN19-7d.
• Measuring a lumped load’s resistance from the receiver instead of from the driver.
• Tapering the wrong way: 0.4 µm at the driver and 4 µm at the receiver gives 561.26 ps on FN12-9’s wire.
• A number without the “explain”: FN12-9c’s key gives 82.44 ps (82.46 rounded) and no reason, which the part grades.

Practice.

Paper	Parts (points)	Full solution	Exam way
FN10	8a–b (20): a tree with two receivers, then two lumped loads	FW1, FN10-8: a, b	a, b
FN12	9a–c (32): a point-to-point wire, widened, then tapered	FW1, FN12-9: a, b, c	a, b, c
FN19	7a–d (36): the width law (0.1 fF/µm at 0.4 µm, so 7b is FN10-8a’s 522.5 ps), the tree, the resistance test, a widened trunk	FW1, FN19-7: a, b, c, d	a, b, c, d
FW1 (added)	Variation 1: a third receiver, a budget and a wider trunk; Variation 2: 12 mm of wire, repeaters or a taper; Variation 3: where to split a taper	V1, V2, V3	—
FN17	3a (11): the same sums on a clock tree, with buffers	FW1, FN17-3a (clock-tree card)	a

The method itself is taught in Chapter 20: wire R and C (§1), the Elmore delay (§3), the uniform line (§4) and its worked example (§5), when resistance matters (§6), trees and side branches (§7), widening (§8) and tapering (§10).

Clock-tree wires

Recognize. The picture: an H-tree. A root inverter at A drives the middle of a trunk; branches halve in length every two levels (4000, 4000, 2000, 2000, 1000 µm in FN17-3) and end in columns of leaf inverters; one leaf’s output is B, with a load written beside it (500 fF, the key’s handwriting). The data: the FO1 delay $\tau_{inv}$ (100 ps), the gate capacitance per width (2 fF/µm), the inverter’s pFET and nFET widths (200 and 100 µm), and the wires’ $\mathcal{R}$ and $\mathcal{C}$ per µm (0.1 Ω/µm, 0.2 fF/µm). Later parts add a supply sensitivity with a nominal supply, then an inductance per length. The phrases: “calculate the total delay from A to B”, “do not consider resistive shielding to calculate buffer delay”, “what jitter can one expect from power supply noise”, “should inductance be included”. The paper calls the inductance per length $L$L; the guide writes $\mathcal{L}$L, and the length $\ell$ℓ, wherever inductance is in play.

The family’s picture: FN17-3’s H-tree, 32 leaves, B at the top right. Original figure ↗

Moves.

1. Count the tree level by level. The number of wires doubles at every level, 2, 4, 8, 16, 32: multiply each count by its level’s length, and count the leaves.
2. One inverter’s input: (pFET + nFET width) × the gate capacitance per width.
3. The root buffer charges everything, because the paper says to ignore resistive shielding: its load is all the wire’s capacitance plus every leaf input, and its delay is $\tau_{inv} \times$ load $/ C_{in}$/Cin​.
4. B’s path from the root’s output, cut at every branch node: each segment’s $R_k$ and $C_k$Ck​.
5. Each $C_{down,k}$Cdown,k​, walking back from B: B’s leaf input first; then, at each node, add the next path segment, its $C_{down}$Cdown​, and the side subtree that leaves there (its wire and its leaf inputs). The half of the tree that leaves at the root node is in no $C_{down}$Cdown​: it only loads the root buffer.
6. Sum $R_k(\tfrac12C_k + C_{down,k})$Cdown,k​), then add the leaf buffer, $\tau_{inv} \times C_B/C_{in}$CB​/Cin​, and the root buffer.
7. Jitter: $|S| \times$ (fractional supply change) $\times$ (root + leaf buffer delays), never the wire. Say how you read “10 % noise”.
8. Inductance: convert to per-mm units, find $\sqrt{\mathcal{L}\mathcal{C}}$LC​, $\ell^{*}$ and $2\mathcal{L}/\mathcal{R}$2L/R; compare the wires’ lengths with $\ell^{*}$ℓ∗, and the edge time (at least $\tau_{inv}$ if none is given) with $2\mathcal{L}/\mathcal{R}$2L/R.

Formulas.

• Memorize: a buffer’s delay, $t_{buf} = \tau_{inv}\,C_{load}/C_{in}$ (Chapter 7), with $C_{in}$ = (pFET + nFET width) × the gate capacitance per width.
• Derive: the path delay, $T_{A\to B} = \tau_{inv}\dfrac{C_{tree}}{C_{in}} + \sum_k R_k\big(\tfrac12C_k + C_{down,k}\big) + \tau_{inv}\dfrac{C_B}{C_{in}}$τinv​Cin​CB​​. Path: (1) the root buffer, the wire and the leaf buffer are in series, so their delays add; (2) the root buffer charges every node, so with no shielding its load is the whole tree; (3) the wire’s segment form starts at the root’s output, and a subtree that leaves at a node counts there, whole, with the path resistance up to that node.
• Derive: the supply rule, $\Delta\tau \approx S\,\tau_{silicon}\,\Delta V_{DD}/V_{DD}$Sτsilicon​ΔVDD​/VDD​. Path: (1) $S = (V_{DD}/\tau)(\partial\tau/\partial V_{DD})$(VDD​/τ)(∂τ/∂VDD​); (2) replace the derivative by a difference, $\Delta\tau/\tau \approx S\,\Delta V_{DD}/V_{DD}$SΔVDD​/VDD​; (3) apply it to the gates only, because $\mathcal{R}$ and $\mathcal{C}$ are set by the metal and the dielectric. A change that comes and goes from cycle to cycle is jitter.
• Memorize: the two wire delays, $t_{RC} = \tfrac12\mathcal{R}\mathcal{C}\ell^2$ and $t_{LC} = \sqrt{\mathcal{L}\mathcal{C}}\,\ell$LC​ℓ.
• Derive: the inductance window. Path: (1) equate $\tfrac12\mathcal{R}\mathcal{C}\ell^2 = \sqrt{\mathcal{L}\mathcal{C}}\,\ell$LC​ℓ; (2) $\ell^{*} = 2\sqrt{\mathcal{L}\mathcal{C}}/(\mathcal{R}\mathcal{C})$2LC​/(RC); (3) substitute back: both delays are $2\mathcal{L}/\mathcal{R}$ there, so inductance can matter only if $t_{slew} \lesssim 2\mathcal{L}/\mathcal{R}$2L/R.

Shortcuts.

• Count by the doubling: FN17-3 has 104,000 µm and 32 leaves, so the root drives 40 pF in 6.667 ns.
• The $C_{down}$ values nest. Each is the next segment’s capacitance plus that segment’s $C_{down}$ plus the side subtree, so walk in from the leaf and add: FN17-3 gives 600, 1600, 4000, 8800 and 19,200 fF.
• The first segment dominates. It carries half the tree: FN17-3’s trunk half gives 7.84 of the wire’s 12.79 ns. Condition: a balanced H-tree.
• Regroup to check: own wire 0.41 + side subtrees 10.32 + B’s leaf input 0.78 + later path wire 1.28 = 12.79 ns. Bound: the 19.2 pF beyond the trunk lies behind 400 to 1300 Ω (the trunk’s own 0.8 pF behind less), so 7.68 to 26 ns.
• Jitter is a fixed fraction of the buffer delay. With $S = -0.1$ and 10 % noise, 1 % of FN17-3’s 6.75 ns of buffers: 67.5 ps. Read as ±10 %, the edge moves over 135 ps. Condition: first order, every buffer on the same noisy supply; the wire’s 12.79 ns does not move.
• Convert before the square root. 0.1 Ω/µm is 100 Ω/mm and 0.2 fF/µm is 0.2 pF/mm, and 1 Ω × 1 pF = 1 ps. FN17-3c: $\sqrt{\mathcal{L}\mathcal{C}} = 4.47$ ps/mm, $\ell^{*} = 0.447$ mm and $2\mathcal{L}/\mathcal{R} = 2$ ps, 50 times below $\tau_{inv}$τinv​. Every wire is longer than $\ell^{*}$ℓ∗, so inductance is out.
• A sized chain at the root (FW1’s Variation 4) cuts the root’s 6.667 ns to 1.158 ns with five stages, and the jitter from 67.5 to 12.4 ps.

Traps.

• Counting one branch per level per quarter, as the FN17 key does: 64,000 µm for 104,000.
• Each path segment’s $\tfrac12\mathcal{R}\mathcal{C}L^2$ against itself only (the key’s terms): 1.28 ns missing.
• Leaving the side subtrees out of $C_{down}$Cdown​, or putting their own resistance into the sum.
• Loading the root buffer with B’s half only: it charges all 40 pF.
• Taking a leaf load other than the figure’s. The key’s arithmetic uses 2000 fF (333 ps) where its own figure has 500 fF (83.3 ps). With its six slips the key reaches 17.48 ns instead of 19.54 ns.
• Applying $S$ to the whole delay, wires included (195.4 ps), or to the key’s slipped buffer delays (its 56.6 ps).
• Reading “10 % noise” without saying how.
• Mixing Ω/µm with nH/mm inside $\sqrt{\mathcal{L}\mathcal{C}}$LC​.

Practice.

Paper	Parts (points)	Full solution	Exam way
FN17	3a (11): the total delay from A to B	FW1, FN17-3: a	a
FN17	3b (11): jitter from supply noise	b	b
FN17	3c (illegible): should inductance be included?	c	c
FW1 (added)	Variation 4: a buffer chain at the root; Variation 5: two leaves, two loads, and two ways to fix the skew	V4, V5	—
FN10	6c–d (15): a clock tree’s jitter, with the latency given	FS1, FN10-6: c, d (flip-flop card)	c, d

The method is taught in Chapter 20: trees and side branches (§7), resistive shielding (§6) and the clock-tree note in its On the exam; the buffer delay in Chapter 7 §7; and in Chapter 21: supply noise and delay (§8) and when inductance matters (§7).

Power grids and decap

Recognize. No picture: short-answer questions of 5 to 7 points, alone (FN12-3, FN12-4) or among the short parts of a question 1 (FN17-1b), answered with a few ranked lines and at most one number. The phrases: “why are grids preferred for power-ground distributions? Provide at least two reasons”, “please name at least three sources of on-chip decoupling capacitance”, “why is on-chip decoupling capacitance necessary for power-supply integrity?”, “if the total clock load in a microprocessor is 1 nF, what is a reasonable decoupling capacitance target to ensure no more than a 10% droop on the power supply? Explain your reasoning”. The same supply noise returns in the clock-tree card, where it becomes jitter.

The family’s one calculation: sizing a decap by charge sharing (Chapter 21 §10). The edge joins the empty load to the charged decap faster than the package can respond. Original figure ↗

Moves.

1. Name the noise. DC is IR drop, caused by the network’s resistance; AC is $L\,dI/dt$LdI/dt, caused by the inductance of the grid and the package. Say which defence answers which: a grid lowers both, decap the AC.
2. “Why grids”: ranked: low $R$ and low $L$ from many redundant paths; built-in decap; signal returns. The cost: routing tracks.
3. “Sources of decap”: implicit metal–metal (the lowest series resistance), n-well and quiet gates; explicit thin-oxide MOS (an NFET, gate at $V_{DD}$VDD​).
4. “Why on-chip decap”: the edge’s charge cannot come through the package’s inductance in time, so it is stored next to the circuits and refilled between edges.
5. “A decap target”: the charge balance across one edge, solved for $C_{decap}$Cdecap​, then put back as a check.
6. “Explain your reasoning”: state the conditions. The load starts discharged; the package delivers nothing within the edge; the decap is close and fast; one edge at a time. Say that the result is a floor, since other switching loads and decap behind series resistance push it up.
7. One number makes each short answer convincing: one strap’s IR drop against $N$ straps’, or the edge’s $L\,dI/dt$ through the package.

Formulas.

• Memorize: DC noise $\Delta V = IR$IR; AC noise $\Delta V = L\,dI/dt$LdI/dt; $N$ equal paths in parallel give $R/N$ and, if they do not couple, about $L/N$L/N.
• Memorize: an edge’s current, about $C_{sw}V_{DD}/t_r$Csw​VDD​/tr​: the charge the edge moves, over its time.
• Derive: the decap target. Path: (1) before the edge the decap holds $C_{decap}V_{DD}$ and the load nothing; (2) after it both sit at $V_{DD} - \Delta V$ with the same charge, $C_{decap}V_{DD} = (C_{decap} + C_{sw})(V_{DD} - \Delta V)$ΔV), so $\Delta V/V_{DD} = C_{sw}/(C_{sw} + C_{decap})$Cdecap​); (3) a droop of at most $\varepsilon$ needs $C_{decap} \ge C_{sw}(1 - \varepsilon)/\varepsilon$ε)/ε.
• Memorize: a decap behind a series resistance $R_s$ responds only on times longer than about $R_sC$Rs​C. Metal–metal has the lowest $R_s$Rs​; the n-well (well and substrate resistance) and the quiet circuits (an on transistor) have more.
• Memorize: a MOS decap cell is a distributed RC, so its time constant grows as the square of its size. Hence unit cells of about 10 µm, tiled and strapped in metal, each with an electromigration fuse against pinholes.
• Memorize: what a droop does to a gate, $\Delta\tau \approx S\,\tau_{silicon}\,\Delta V_{DD}/V_{DD}$ (the clock-tree card). A droop that is the same on every cycle only adds latency; one that comes and goes is jitter.

Shortcuts.

• For a droop of $\varepsilon$ε, the decap is $(1 - \varepsilon)/\varepsilon$ times the switching load: 9 times for 10 % (FN17-1b: 9 nF), 19 times for 5 %, 4 times for 20 %. Condition: one edge, charge sharing alone, the decap close and fast.
• Area: at, for example, 10 fF/µm² of thin-oxide MOS capacitance, 9 nF is 0.9 mm² of chip.
• One strap cannot feed the centre. For example, 2 A through one 1.5 Ω strap drops 3 V, more than the 1.2 V supply; 100 paths in parallel drop 30 mV (2.5 %), and 1 nH per path becomes about 10 pH. Condition: equal paths sharing the current.
• The edge through the package: FN17-1b’s 1 nF clock rising 1.2 V in 100 ps draws 12 A; through even 10 pH that is 1.2 V, the whole supply. Condition: an illustrative 100 ps edge (the paper gives none).
• Count the decap that can respond in the edge’s time. Compare $R_sC$ with the edge: in Chapter 21’s example, 1 nF behind 0.5 Ω has 0.5 ns, too slow for a 100 ps edge, while 1 nF behind 0.05 Ω has 50 ps.

Traps.

• Writing $C_{decap} = C_{sw}/\varepsilon$ (10 nF), which forgets that the load keeps part of the shared charge: put it back, $1/(1 + 9) = 10$ %, and the slip shows (10 nF gives 9.09 %).
• Giving only the resistance as the grid’s reason: the most important reason is low resistance and low inductance.
• Calling the grid’s capacitance a cost: on the supply it is decap, and the only cost is routing.
• Listing switching gates as decap: only the quiet gates lend their input capacitance.
• Answering FN12-4’s list but not its “why”: the key does exactly that.
• Counting a capacitor on the board as decap: it sits behind the same package inductance.
• Counting every nanofarad as equally useful. In FW1’s Variation 6, the n-well’s 10 nF behind 50 mΩ meets 10 % by charge sharing alone (9.09 %), but on a 100 ps edge the droop is about 59 %.
• An NFET decap with its gate at ground: the channel is off.
• No key error in this family: the FN12-3, FN12-4 and FN17-1b keys agree, but FN12-4’s gives no “why” and FN17-1b’s explains only “charge sharing”.

Practice.

Paper	Part (points)	Full solution	Exam way
FN12	3 (7): why grids, at least two reasons	FW1, FN12-3	3
FN12	4 (7): three sources of on-chip decap, and why it is needed	FW1, FN12-4	4
FN17	1b (5): a decap target for a 1 nF clock and a 10 % droop	FW1, FN17-1b	1b
FW1 (added)	Variation 6: a decap behind series resistance; Variation 7: a droop budget, the grid and the decap	V6, V7	—
FN17	3b (11): what the supply noise does to a clock tree	FW1, FN17-3b (clock-tree card)	b

The method is taught in Chapter 21: the two kinds of supply noise (§8), power and ground grids (§9), off-chip inductance and decap sizing (§10), implicit and explicit decap, and series resistance (§11) and MOS decap cells (§12).