FW1. Wires, repeaters and power: the exam way

This is the exam way of FW1: each part as you would write it on the paper, with what to recognize, the lines to write, the trap to watch and the answer. Every part keeps the anchor it has on FW1, so the switch at the top of the page takes you to the same part’s full solution. The methods are three cards of the playbook: Elmore wires for FN10-8, FN12-9 and FN19-7, clock-tree wires for FN17-3, and power grids and decap for FN12-3, FN12-4 and FN17-1b. FW1’s seven harder variations stay on FW1 only, at the end of each family: Elmore wires, clock-tree wires and power grids and decap. Work them there, against the budgets their titles give.

The clock. The past finals gave 180 minutes. FN10 and FN12 had 200 points, 0.9 min a point, so a 10-point part has 9 minutes and a 7-point short answer about 6; FN17 and FN19 had 250, 0.72 min a point, so a 10-point part has about 7 minutes and FN17-1b’s 5 points about 4. (The past midterms gave 75 minutes for 150 points, 0.5 min a point: a final part has more time, and more steps.)

Two conventions run through every line below. Work in Ω and fF: a product in Ω·fF divided by 1000 is in ps. And the Elmore delay is quoted as the delay, with no ln 2, as the lecture and every key do.

FN10-8: a wire tree with two receivers (20 points)

FN10-8, p13. Consider a long global wire from driver A to receivers B and C as shown below. Assume that the wire is $0.4\,\mu m$ wide and and (sic) has a resistance of 0.076 $\Omega/square$Ω/square. Its capacitance per unit length is $0.1\,fF/\mu m$0.1fF/μm.

FN10-8’s wire tree (p13, redrawn): from A, 2000 µm to the branch point X; up 1000 µm and across 2000 µm to B; down 1000 µm and across 3000 µm to C; 100 fF at B and at C. The risers are wire too.

Part (a): the Elmore delay from A to B (10 points)

FN10-8a, p13. Calculate the Elmore delay from A to B assuming 100 fF of loading at receivers B and C. (10 points)

Hint

Which parts of the tree lie on the path from A to B, and what does the branch to C contribute if its resistance is not on that path?

Recognize. Elmore wires, moves 1–6: a tree, “from A to B”, so the wire to C is a side branch. About 9 minutes.

On the paper.

1. $\mathcal{R} = 0.076/0.4 = 0.19\ \Omega/\mu$m; $\mathcal{C} = 0.1$ fF/µm
2. Risers count: A–X 2000, X–B 3000, X–C 4000 µm
3. $R$ = 380, 570, 760 Ω; $C$ = 200, 300, 400 fF
4. $C_{down}$(A–X) $= 300 + 100 + 400 + 100 = 900$ fF; $C_{down}$(X–B) = 100 fF
5. $T = \sum R_k(\tfrac12C_k + C_{down,k})$
6. A–X: $380 \times (100 + 900) = 380$ ps
7. X–B: $570 \times (150 + 100) = 142.5$ ps
8. $T = 380 + 142.5 = 522.5$ ps (X–C’s 760 Ω never enters)
9. Check, by capacitance: $\tfrac12R_{AB}C_{AB} + R_{AB}C_B + R_{AX}(C_{XC} + C_C) = 237.5 + 95 + 190 = 522.5$ ✓

Watch out. The side branch costs its whole 500 fF through the trunk’s 380 Ω, 190 ps; leaving it out gives 332.5 ps. Its own resistance stays out, and X–B is 3000 µm, not 2000.

Answer: $T_{Elmore}(A{\to}B) = 522.5$ ps: 380 ps from the trunk A–X, 142.5 ps from the branch X–B.

Full solution

Part (b): two more loads (10 points)

FN10-8b, p14. In addition to the receiver loading, assume that there are two additional lumped capacitance loads of 200 fF introduced $1000\,\mu m$ from each of the receivers B and C. Calculate the Elmore delay in this case from A to B. (10 points)

FN10-8b’s tree (p14, redrawn): part (a)‘s wires, with an extra 200 fF load 1000 µm before B (call it Y) and another 1000 µm before C.

Hint

Each new 200 fF adds its capacitance times one resistance. Which resistance does each one share with the path to B?

Recognize. Elmore wires, the first shortcut: a lumped load costs its capacitance times the resistance it shares with B’s path. About 9 minutes.

On the paper.

1. Linear in $C$C: (a)‘s 522.5 ps plus one term per new load
2. Y is 1000 µm before B, so 2000 µm past X along X–B
3. $R_{AY} = 380 + 0.19 \times 2000 = 760\ \Omega$
4. Y on B’s path: $760 \times 200 = 152$ ps
5. C-branch load shares only $R_{AX}$RAX​: $380 \times 200 = 76$ ps
6. $T = 522.5 + 152 + 76 = 750.5$ ps
7. Check (cut at Y): $532 + 190 + 28.5 = 750.5$ ✓

Watch out. “1000 µm from each receiver” gives the position, not the resistance: measure from A (760 Ω, not the 190 Ω of the last 1000 µm), and give the C-branch load the trunk only.

Answer: $T_{Elmore}(A{\to}B) = 750.5$ ps: 522.5 ps, plus 152 ps for the load on B’s path and 76 ps for the one on the branch to C.

Full solution

FN12-9: widening and tapering a point-to-point wire (32 points)

FN12-9, p12. Consider a long point-to-point global net from driver A to receiver B as shown below. Assume that the wire is $0.4\,\mu m$ wide and has a resistance of $0.076\,\Omega/square$0.076Ω/square. Its capacitance per unit length is given by:

$$0.04\ \text{fF}/\mu\text{m} + 0.15\ \text{fF}/\mu\text{m}^2 \times W$$

Assume the receiver at B represented a (linear) capacitance of 30 fF.

FN12-9’s wire (p12, redrawn): 4000 µm from the driver end A to the receiver B, which loads it with 30 fF.

Part (a): the 0.4 µm wire (10 points)

FN12-9a, p12. Calculate the Elmore delay from A to B. Hint: Remember that the Elmore delay of a distributed RC line of length L with a resistance per unit length of $\mathcal{R}$ and a capacitance per unit length of $\mathcal{C}$ is given by $\tau = \tfrac12\mathcal{R}\mathcal{C}L^2$21​RCL2. (10 points)

Hint

The paper’s hint gives the wire against itself. What else does the wire’s resistance have to charge?

Recognize. Elmore wires, moves 1, 3 and 5 on one uniform segment: the uniform line. The printed hint is half the formula. About 9 minutes.

On the paper.

1. $\mathcal{C} = 0.04 + 0.15 \times 0.4 = 0.10$ fF/µm
2. $\mathcal{R} = 0.076/0.4 = 0.19\ \Omega/\mu$m
3. $R = 760\ \Omega$760 Ω, $C_w = 400$ fF
4. $T = \tfrac12RC_w + RC_{load}$
5. $= \tfrac12(760)(400) + (760)(30)$ Ω·fF $= 152 + 22.8$ ps
6. $T = 174.8$ ps
7. Bound: $760 \times 430 = 326.8$ ps $> 174.8$ ✓

Watch out. The hint’s $\tfrac12\mathcal{R}\mathcal{C}L^2$ alone (152 ps) leaves out B’s 30 fF. And multiply the areal term by $W$W: 0.19 fF/µm is wrong.

Answer: $T_{Elmore} = 152 + 22.8 = 174.8$ ps.

Full solution

Part (b): widening to 4 µm (10 points)

FN12-9b, p13. Widen the wire from $0.4\,\mu m$ to $4\,\mu m$ and recompute the Elmore delay. (10 points)

Hint

When the wire is ten times wider, which of its per-length values falls tenfold, and does the other one stay put?

Recognize. Elmore wires, move 7 (widening): recompute both per-length values. About 9 minutes.

On the paper.

1. $\mathcal{R} = 0.076/4 = 0.019\ \Omega/\mu$m, $R = 76\ \Omega$
2. $\mathcal{C} = 0.04 + 0.15 \times 4 = 0.64$ fF/µm, $C_w = 2560$ fF
3. Intrinsic: $\tfrac12(76)(2560) = 97.28$ ps
4. Extrinsic: $76 \times 30 = 2.28$ ps
5. $T = 99.56$ ps (from 174.8)
6. Check: $T(W) = 91.2 + 33.44/W$ ps; at 4 µm, $91.2 + 8.36 = 99.56$ ✓
7. Floor $\tfrac12R_\square C_{areal}L^2 = 91.2$ ps: no width beats it

Watch out. Keeping 0.1 fF/µm divides every term by 10 (17.48 ps). The areal part of the intrinsic delay does not fall at all.

Answer: $T_{Elmore} = 97.28 + 2.28 = 99.56$ ps, from 174.8 ps; the wire’s capacitance rises from 400 to 2560 fF.

Full solution

Part (c): tapering (12 points)

FN12-9c, p13. Now assume that the wire width is set to $4\,\mu m$ for the first $2000\,\mu m$ and $0.4\,\mu m$ for the last $2000\,\mu m$2000μm. Compare with your result in (b) and explain why such wire “tapering” might be advantageous. (12 points)

Hint

In the Elmore sum, whose capacitance does the near half’s resistance multiply, and whose resistance does the far half’s capacitance see?

Recognize. Elmore wires, move 7: a taper is two segments in series, and “explain why” is graded. About 11 minutes.

On the paper.

1. Near (4 µm, 2000 µm): $R_1 = 38\ \Omega$38 Ω, $C_1 = 1280$ fF
2. Far (0.4 µm, 2000 µm): $R_2 = 380\ \Omega$380 Ω, $C_2 = 200$ fF
3. $T = R_1(\tfrac12C_1 + C_2 + C_{load}) + R_2(\tfrac12C_2 + C_{load})$
4. $= 38 \times 870 + 380 \times 130$ Ω·fF $= 33.06 + 49.4$ ps
5. $T = 82.46$ ps; (b) 99.56: 17.1 ps faster (17.2 %)
6. Why: $R_1C_2$ falls 48.64 → 7.6 ps (saves 41.04); the narrow far half costs 13.68 + 10.26; net 17.1 ps
7. Near $R$ carries everything after it: wide. Far $C$ sees all $R$ before it: narrow

What to draw (FW1’s taper): two segments, wide at the driver, narrow at the receiver. Original figure ↗

Watch out. Adding the two halves’ own uniform-line delays drops the cross term $R_1C_2$R1​C2​. A number without the “why” loses points.

Answer: $T_{Elmore} = 82.46$ ps, 17.1 ps faster than (b), with 1480 fF of wire instead of 2560 fF. The near resistance multiplies all the capacitance after it and the far capacitance sees all the resistance before it, so wide near the driver and narrow near the receiver lowers both: faster, lighter to drive, less metal.

Full solution

FN19-7: a wire tree whose capacitance depends on its width (36 points)

FN19-7, p15. Consider a long global wire from driver A to receivers B and C as shown below. Assume that the wire is 0.4 mm (sic) wide and has a resistance of 0.076 Ω/square. Its capacitance per unit length is given by:

$$0.04\ \text{fF}/\mu\text{m} + 0.15\ \text{fF}/\mu\text{m}^2 \times W$$

Assume that each receiver has a load of 100 fF.

FN19-7’s wire tree (p15, redrawn): FN10-8’s geometry, 100 fF at each receiver (in the text, not on the drawing). Read the width as 0.4 µm: part (d) widens it “from 0.4 µm”.

Part (a): why the capacitance has this form (8 points)

FN19-7a, p15. Explain why the capacitance has the functional form specified above. (8 points)

Hint

Picture the wire’s cross-section over the layer below it. Which of its surfaces grows when the wire is made wider?

Recognize. Elmore wires, the first formula: $\mathcal{C} = C_{areal}W + C_{fringe}$Cfringe​. A words part: sketch, name both terms, give one number. About 6 minutes.

On the paper.

1. Sketch the cross-section over the plane below
2. $0.15W$0.15W: areal (parallel plate), bottom face $W$ wide, so ∝ $W$
3. $C_{areal} = \varepsilon/d$ε/d, per unit area (fF/µm²)
4. $0.04$0.04: fringe from the sides; set by thickness and spacing, not $W$
5. At 0.4 µm: $0.06 + 0.04 = 0.10$ fF/µm (60 % areal)

What to draw (Chapter 20, Lecture19 @ 49:19, redrawn): the cross-section, straight lines from the bottom face, fringing arcs from the sides. Original figure ↗

Watch out. “Capacitance ∝ area” alone predicts $\mathcal{C} \to 0$ as $W \to 0$0; the constant 0.04 fF/µm is the sides, which a narrow wire still has.

Answer: an areal (parallel-plate) part from the bottom face, proportional to the width, $0.15\ \text{fF}/\mu\text{m}^2 \times W$W, plus a fringe part from the sides that does not depend on the width, 0.04 fF/µm. At 0.4 µm: 0.10 fF/µm.

Full solution

Part (b): the Elmore delay from A to B (10 points)

FN19-7b, p16. Calculate the Elmore delay from A to B. (10 points)

Hint

What does the capacitance law give at 0.4 µm, and which segments lie on the path from A to B?

Recognize. Elmore wires, moves 1–6: FN10-8a once $\mathcal{C}$ is evaluated. About 7 minutes.

On the paper.

1. $\mathcal{C}(0.4) = 0.10$ fF/µm, $\mathcal{R} = 0.19\ \Omega/\mu$m: FN10-8’s wire
2. A–X 380 Ω, 200 fF; X–B 570 Ω, 300 fF; X–C 760 Ω, 400 fF
3. $C_{down}$Cdown​: 900 fF beyond X, 100 fF beyond X–B
4. $380 \times 1000 + 570 \times 250$ Ω·fF
5. $T = 380 + 142.5 = 522.5$ ps
6. Check: $237.5 + 95 + 190 = 522.5$ ✓

Watch out. $0.04 + 0.15 = 0.19$ fF/µm forgets the $W$W. The risers count, and X–C’s resistance is off B’s path.

Answer: $T_{Elmore}(A{\to}B) = 380 + 142.5 = 522.5$ ps.

Full solution

Part (c): must resistance be considered? (8 points)

FN19-7c, p16. Assume the Elmore delay calculated in (b). If the FO1 delay of this technology is 50 psec, would resistance have to be considered for this line in calculating the delay from A to B? Explain. (8 points)

Hint

How long does an edge in this technology take to switch, and how does that compare with 522.5 ps?

Recognize. Elmore wires, move 8: “would resistance have to be considered”, and no edge time given, so count FO1 delays. About 6 minutes.

On the paper.

1. $522.5/50 = 10.45$ FO1 delays
2. An edge lasts a few FO1 delays: about 100–150 ps
3. $T_{Elmore} \gg t_r$tr​: include $R$
4. B’s edge: late by hundreds of ps, stretched to about $2T_{Elmore} \approx 1045$ ps
5. Yes

Watch out. The ratio is the evidence, not the explanation: say that the FO1 delay stands for the edge time, and that the wire both delays and stretches the edge.

Answer: yes. 522.5 ps is 10.45 FO1 delays, far longer than an edge (a few FO1 delays, 100–150 ps), so B’s edge is delayed by hundreds of picoseconds and stretched to about 1 ns; a lumped capacitance would miss both.

Full solution

Part (d): widening the trunk to 10 µm (10 points)

FN19-7d, p17. Now imagine widening the wire from A to X from $0.4\,\mu m$ to $10\,\mu m$10μm. What is the Elmore delay now from A to B? (10 points)

Hint

Which per-length values change on the trunk, and which term of the sum is the only one that moves?

Recognize. Elmore wires, move 7: widen the segment nearest the driver; only its term changes. About 7 minutes.

On the paper.

1. Trunk: $\mathcal{R} = 0.076/10 = 0.0076\ \Omega/\mu$m, $R_{AX} = 15.2\ \Omega$
2. $\mathcal{C} = 0.04 + 0.15 \times 10 = 1.54$ fF/µm, $C_{AX} = 3080$ fF
3. $C_{down}$(A–X) still 900 fF
4. A–X: $15.2 \times (1540 + 900) = 37.088$ ps (from 380)
5. X–B unchanged: 142.5 ps
6. $T = 37.088 + 142.5 = 179.588 \approx 179.6$ ps
7. Floor, any trunk width: $22.8 + 142.5 = 165.3$ ps ✓
8. The bill: the tree holds 3980 fF instead of 1100 fF (loads included)

Watch out. Keeping 0.1 fF/µm on the widened trunk gives 157.7 ps: the wider plate holds more charge. Leave the branches at 0.4 µm.

Answer: $T_{Elmore}(A{\to}B) = 179.6$ ps, from 522.5 ps; the branch’s 142.5 ps is now 79 % of it.

Full solution

FN17-3: a clock H-tree, its jitter and its inductance (22 points, and (c))

FN17-3, p5. Consider the clock tree shown below. Let the fanout-of-one delay be given by $\tau_{inv} = 100$ psec. Let the gate capacitance per unit width be 2 fF/µm. Let all of the wires have a capacitance per unit length of $\mathcal{C} = 0.2$ fF/µm and a resistance per unit length of $\mathcal{R} = 0.1\ \Omega/\mu$m. Let the inverter have a pFET width of 200 µm and an nFET width of 100 µm.

FN17-3’s H-tree (p5, redrawn): a root inverter at A drives 32 leaf inverters through five levels of wire, 4000, 4000, 2000, 2000 and 1000 µm each way; the 500 fF at B, the top-right leaf’s output, is the key’s handwriting.

Part (a): the total delay from A to B (11 points)

FN17-3a, p7. Calculate the total delay from A to B. Use Elmore delay to estimate the interconnect delay. Do not consider resistive shielding to calculate buffer delay. Ignore wire inductance. (11 points)

Hint

The signal passes three things in series on its way from A to B. What does each of them have to charge?

Recognize. Clock-tree wires, moves 1–6: root buffer + wire + leaf buffer. About 8 minutes, tight for the arithmetic: write the $C_{down}$ column first.

On the paper.

1. Wire: $8000 + 16{,}000 + 16{,}000 + 32{,}000 + 32{,}000 = 104{,}000$ µm; 32 leaves
2. $C_{in} = (200 + 100) \times 2 = 600$ fF
3. $C_{tree} = 32 \times 600 + 0.2 \times 104{,}000 = 40{,}000$ fF
4. Root: $100 \times 40{,}000/600 = 6.667$ ns
5. Path: $R_k$ = 400, 400, 200, 200, 100 Ω; $C_k$ = 800, 800, 400, 400, 200 fF
6. $C_{down,k}$ = 19,200, 8800, 4000, 1600, 600 fF
7. $400(400 + 19{,}200) + 400(400 + 8800) + 200(200 + 4000)$ $+ 200(200 + 1600) + 100(100 + 600)$ Ω·fF
8. $= 7.84 + 3.68 + 0.84 + 0.36 + 0.07 = 12.79$ ns
9. Leaf: $100 \times 500/600 = 83.3$ ps
10. $T = 6.667 + 12.79 + 0.083 = 19.54$ ns

What to draw (FW1’s path, unrolled): the five path segments, their $C_{down,k}$Cdown,k​, and the side subtree that leaves at each node. Original figure ↗

Watch out. Count every branch: the key’s 64,000 µm counts one branch per level per quarter, and with its other slips it reaches 17.48 ns. Each path segment also carries the path wire after it, not only its own $\tfrac12R_kC_k$21​Rk​Ck​: leaving that out loses 1.28 ns.

Answer: $T_{A\to B} = 6.667 + 12.79 + 0.083 = 19.54$ ns: the root buffer 6.667 ns, the wire 12.79 ns, the leaf buffer 83.3 ps.

Full solution

Part (b): jitter from supply noise (11 points)

FN17-3b, p7. If the buffers have a power-supply sensitivity of $(V_{DD}/\tau_{inv})(\partial\tau_{inv}/\partial V_{DD}) = -0.1$ and operate at a nominal supply voltage of 1.2 V, what jitter can one expect from power supply noise that is 10% of the nominal supply voltage. (11 points)

Hint

Which parts of the 19.54 ns change when the supply moves?

Recognize. Clock-tree wires, move 7: jitter from a sensitivity, on the buffers only. About 8 minutes; the answer itself is short.

On the paper.

1. Only the buffers move: $\tau_{silicon} = 6666.7 + 83.3 = 6750$ ps
2. The wire’s 12.79 ns does not
3. $\Delta V_{DD}/V_{DD} = 0.12/1.2 = 0.1$
4. $\Delta\tau \approx S\,\tau_{silicon}\,\Delta V_{DD}/V_{DD} = (-0.1)(6750)(-0.1) = +67.5$ ps
5. Read as a 10 % droop and back: the edge wanders over 67.5 ps
6. Read as ±10 %: ±67.5 ps, a 135 ps range

Watch out. $S$ on the whole 19.54 ns gives 195.4 ps: two-thirds of the path is wire, which the supply does not move. Say how you read “10 % noise”.

Answer: about 67.5 ps of jitter at B: 1 % of the 6.75 ns of buffer delay (a 135 ps range if the noise is ±10 %).

Full solution

Part (c): should inductance be included? (points illegible)

FN17-3c, p7 (the second page labelled 7). If the inductance per unit length for these wires is $L = 0.1$ nH/mm, should inductance be included in the interconnect delay analysis? Please explain. [The point value is overwritten and illegible.]

Hint

Where do the RC and LC delays of these wires cross, and how long is the shortest wire in the tree?

Recognize. Clock-tree wires, move 8: the inductance window. The points are illegible; budget it as an 8-point part, about 6 minutes.

On the paper.

1. Per mm: $\mathcal{R} = 100\ \Omega$/mm, $\mathcal{C} = 0.2$ pF/mm, $\mathcal{L} = 0.1$ nH/mm
2. $\sqrt{\mathcal{L}\mathcal{C}} = 4.472$ ps/mm
3. $\ell^{*} = 2\sqrt{\mathcal{L}\mathcal{C}}/(\mathcal{R}\mathcal{C}) = 2(4.472)/20 = 0.447$ mm
4. There $t_{RC} = t_{LC} = 2\mathcal{L}/\mathcal{R} = 2$ ps
5. Shortest wire 1 mm $> \ell^{*}$ℓ∗: RC rules (10 ps against 4.47 ps)
6. Edges ≥ $\tau_{inv}$ = 100 ps ≫ 2 ps: no window at any length
7. No

Watch out. Convert to per-mm before the square root. Don’t assume a slew without saying why: the lengths alone settle it, since every wire is longer than $\ell^{*}$ℓ∗.

Answer: no. The RC and LC delays cross at 0.447 mm, at only 2 ps; every wire in the tree is longer, so RC dominates, and the edges (at least 100 ps) are far slower than 2 ps.

Full solution

FN12-3: why grids for power and ground (7 points)

FN12-3, p3. Why are grids preferred for power-ground distributions? Provide at least two reasons. (7 points)

What to draw (FW1’s figure; the paper has none): (a) one strap from an edge pad to the centre, all of $I$ through one $R$ and $L$L; (b) a grid, $N$ parallel paths, about $R/N$ and $L/N$L/N, and a signal $s$ returning in the adjacent strap.

Two reasons, and a third (7 points)

FN12-3, p3. Why are grids preferred for power-ground distributions? Provide at least two reasons. (7 points)

Hint

What does a gate at the centre of the die need from the supply wiring, and what happens to resistances and inductances that sit side by side?

Recognize. Power grids and decap, move 2: “why grids”, ranked, with one number. About 6 minutes.

On the paper.

1. Job: small $IR$ and $L\,dI/dt$ at every point, the centre included
2. (1), most important: $N$ redundant parallel paths, $R/N$ and $L/N$
3. e.g. 2 A: one 1.5 Ω strap drops 3 V (> 1.2 V); 100 paths: 15 mΩ, 30 mV; 1 nH → 10 pH
4. (2) $V_{DD}$ and gnd lines side by side: built-in decap
5. (3) every signal has a return close by: small loop, low inductance

Watch out. Resistance alone is half of reason 1: parallel paths divide the inductance too. The grid’s capacitance is not a cost: on the supply it is decap.

Answer: (1) many redundant parallel paths give every point low resistance and low inductance, so low IR drop and low $L\,dI/dt$LdI/dt; (2) the grid’s metal capacitance is built-in decap; (3) every signal gets a nearby current return. The cost is routing tracks.

Full solution

FN12-4: sources of on-chip decap, and why it is needed (7 points)

FN12-4, p4. Please name at least three sources of on-chip decoupling capacitance. Why is on-chip decoupling capacitance necessary for power-supply integrity? (7 points)

What to draw (FW1’s figure; the paper has none): (a) without decap, the transient runs through the package’s $L$ in both rails and the chip’s rail moves by $L\,di/dt$Ldi/dt; (b) with $C_{decap}$ beside the load, the transient stays in the short loop and the package carries only $\bar{I}$Iˉ.

Four sources, and the reason (7 points)

FN12-4, p4. Please name at least three sources of on-chip decoupling capacitance. Why is on-chip decoupling capacitance necessary for power-supply integrity? (7 points)

Hint

What does the package’s inductance do to a current that must rise to amperes within 100 ps?

Recognize. Power grids and decap, moves 3–4: a list and a “why”, both graded. About 6 minutes.

On the paper.

1. Implicit: (1) metal–metal grid capacitance (lowest $R_s$Rs​)
2. (2) n-well junctions; (3) quiet (non-switching) gates
3. Explicit: (4) thin-oxide MOS decap, an NFET with its gate at $V_{DD}$
4. Why, e.g.: 1 nF × 1.2 V = 1.2 nC in a 100 ps edge, about 12 A
5. Through even 10 pH: $L\,dI/dt$ = 1.2 V, the whole supply
6. On-chip decap supplies the edge in a loop with no package $L$L; the package refills it with $\bar{I}$ between edges (a board capacitor sits behind the same $L$L)

Watch out. Answer the “why” as well as the list (the key skips it): it is graded too. “Decap filters the supply” is a description, not a reason, and switching gates are not decap.

Answer: metal–metal grid capacitance, n-well junctions and non-switching circuits (implicit), and thin-oxide MOS decap (explicit). It is needed because an edge’s current cannot come through the package inductance without an $L\,dI/dt$ droop as large as the supply; on-chip decap supplies it locally.

Full solution

FN17-1b: a decap target for a 1 nF clock (5 points)

FN17-1b, p2. If the total clock load in a microprocessor is 1 nF, what is a reasonable decoupling capacitance target to ensure no more than a 10% droop on the power supply? Explain your reasoning. (5 points)

The setting (FN12-4’s figure; the paper has none): the clock net is the load, and in (b) its charge comes from $C_{decap}$Cdecap​. Original figure ↑

Part (b): the decap target (5 points)

FN17-1b, p2. If the total clock load in a microprocessor is 1 nF, what is a reasonable decoupling capacitance target to ensure no more than a 10% droop on the power supply? Explain your reasoning. (5 points)

Hint

When the clock rises, where does the charge for its 1 nF come from, and at what voltage do the two capacitors end?

Recognize. Power grids and decap, moves 5–6: “a decap target … no more than a 10 % droop”, the charge balance. About 4 minutes.

On the paper.

1. Before: decap at $V_{DD}$VDD​; the clock net at 0
2. The edge beats the package: the clock’s charge comes from the decap
3. $C_{decap}V_{DD} = (C_{decap} + C_{clock})(V_{DD} - \Delta V)$
4. $\Delta V/V_{DD} = C_{clock}/(C_{clock} + C_{decap}) \le 0.1$
5. $C_{decap} \ge 9\,C_{clock} = 9$ nF
6. Check: $1/(1 + 9) = 10$ % ✓
7. A floor: other switching logic and decap behind $R_s$ push it up

Watch out. $C_{clock}/\varepsilon$ = 10 nF forgets that the clock keeps its share of the charge (it gives 9.09 %). “Explain” wants the assumptions, not just “charge sharing”.

Answer: about 9 nF of on-chip decap, nine times the clock load: $\Delta V/V_{DD} = C_{clock}/(C_{clock} + C_{decap}) \le 0.1$0.1, because the package’s inductance cannot deliver the edge’s charge in time. Treat it as a minimum.

Full solution