M6. Past midterms: dynamic and domino logic

This page works every past-midterm problem on dynamic and domino logic. The family has grown on each recent exam: 8 of 150 points in 2017 (a single delay), 32 of 150 in 2023 (a whole question), 50 of 200 in 2024 (a whole question, the largest on the paper). Both recent questions use a p-type dynamic stage, the polarity that Lecture 12 introduces for NP domino, so read Chapter 12, Section 6 first if it is new to you.

Every answer below is re-solved here; none is copied from an answer key. Where a key disagrees, the folded note on the key at the end of the part explains why, and the table at the end lists them all. Two problems from past finals follow the midterm questions as extra drills, because the midterms have only one domino-sizing problem and none on clocking two dynamic stages.

After this page you can:

1. read the function of a dynamic stage, n-type or p-type, and follow a cascade of them to its outputs;
2. find the one edge each stage makes along a path, and notice when a question names an edge the circuit cannot make;
3. compute an evaluate delay by $(R/W)C$ and by dynamic logical effort, with the whole stack counted from the rail to the node, in either strength convention;
4. resize a path whose widths also sit beside fixed loads or fixed devices, where equal gains are no longer exact;
5. explain what skewing the inverter after a dynamic node does to its noise margins, and add the half latch that protects the node;
6. time two dynamic stages on two clocks: the race, and the collision a footless stage risks.

Before you start

How to use this page. Each section restates one exam question with its source page (MT23-3b, p8 is Fall 2023, question 3b, physical PDF page 8) and its points, and shows the exam’s own figure. The page opens with a short How to approach section: how to recognize a dynamic-logic question, the moves in order, why the formulas apply, and the traps. Then every part is worked the same way: what it asks, the idea behind the method, the solution in steps (each step gives its reason first), a check on the result, the answer, and one thing to remember. Try each part on your own first; open the Hint if you are stuck, and step through the solution before you press “Show all”. The answer key’s verdict is folded at the end of each part. The chapters teach each method in full, and every solution links the section.

Question	Parts	Points	Chapters
MT24-5	function, delay, resizing	50 (of 200)	8, 11, 12
MT23-3	function, delay, noise margins, half latch	32 (of 150)	6, 7, 11, 12
MT17-3c	evaluate delay	8 (of 150)	7, 11, 12
FN12-8 (final)	delay, sizing	30 (of 200)	8, 12
FN17-2 (final)	race, collision, function	25 (of 250)	11, 12

MT21 has no dynamic question. The other parts of MT17-3 (static inverters and a NAND4) are on page M3.

Conventions the exams use

• n-type and p-type stages (Chapter 11, Section 4; Chapter 12, Sections 5–6). An n-type stage is precharged to 1 by a clocked PFET and evaluates through NFETs; its node is $\overline f$f​, where $f$ is the network’s conduction function, and the domino inverter after it gives $f$f. A p-type stage is pre-discharged to 0 by a clocked NFET and evaluates through PFETs, which conduct on 0s; its node is $f$f. Which clock phase evaluates depends on how the clocked devices are wired: read it from the figure.
• The logical edge (Chapter 12, Section 1). In evaluate an n node can only fall and a p node can only rise. So along a path each stage makes exactly one edge, and the inverter after an n node rises, the one after a p node falls. Find the edges before you choose a resistor.
• Strength conventions. “The nFET and pFET have the same strength” (MT17-3, MT24-5): the balanced inverter is W/W, $\tau_{inv} = 2R_{nfet}C_g$2Rnfet​Cg​, and a $k$-high stack of equal devices has $g = k/2$k/2, n-type or p-type. With $R_{pfet} = 2R_{nfet}$ (MT23-3, FN12-8, FN17-2): $\tau_{inv} = 3R_{nfet}C_g$3Rnfet​Cg​, $g = k/3$ for an n stage and $2k/3$ for a p stage (Chapter 12, Section 2).
• Stacks. Count every device between the rail and the node, the footer (n) or the clocked header (p) included; the precharge or pre-discharge device is off during evaluate and never counts. Equal devices in series: $W_{eq} = 1/\sum (1/W_i)$ (Chapter 7, Section 8).
• Delay $= (R/W)\,C$(R/W)C, or $\tau_{inv}\sum g_ih_i$τinv​∑gi​hi​; the two agree. MT23-3b’s key multiplies by 0.69; where it matters this page gives both. Loads are written as widths: $C/C_g$ µm of gate.
• Names. Node names added on this page: X and Z in MT24-5 (the outputs of its stages 1 and 2). The exams’ own names (W1–W9, M1–M9, V_n, Y₁, Y₂, I–IV) are kept.

How to approach a dynamic-logic question

Recognize it by the clock. Some transistors have clk (or $\overline{\text{clk}}$clk, or $\phi$ϕ) on their gates: a clocked PFET from $V_{DD}$ to a node, a clocked NFET from the node or the network to ground, and a network of logic transistors between them. Often an inverter follows the node. The exams ask “what logic function does this circuit perform”, “the delay from A falling to Y falling”, “resize … to minimize the delay”, “how do the noise margins compare”, “add a transistor”, or, on the finals, how two clocks must be timed. The family carried 8 of 150 points in MT17, 32 of 150 in MT23 and 50 of 200 in MT24, the largest question on that paper.

The moves, in order.

1. n-type or p-type, and which phase evaluates. Read the clocked devices. A clocked PFET above an NFET network precharges the node to 1: an n-type stage, which evaluates while that PFET is off. A clocked NFET below a PFET network pre-discharges the node to 0: a p-type stage, which evaluates while that NFET is off. Whether that is clk = 1 or clk = 0 depends on which clock drives the device, so read it from the figure.
2. The node’s function. Write the network’s conduction function $f$f: series devices are AND, parallel ones OR, and a PFET conducts on a 0. An n node is $\overline f$f​; a p node is $f$f. Then follow the inverters.
3. The one edge each stage can make. In evaluate an n node can only fall and a p node can only rise; the inverter after an n node rises, the one after a p node falls. Mark the edges along the path before you pick any device, and check that the edge the question names is one the path can make.
4. The delay, with the whole stack. Count every device in series from the rail to the node: the footer (n) or the clocked header (p) is in, the precharge device is out. Then use $(R/W)\,C$ or $\tau_{inv}\sum g h$τinv​∑gh.
5. Resizing. For each width you may change, ask what it drives and what it loads. If it also loads a fixed branch, or sits beside a fixed device, the path effort $F$ moves with it and equal gains are no longer exact: balance the parts that change.
6. Noise. The inverter after a dynamic node is skewed toward the edge that carries the logic. That moves its threshold toward the node’s resting value and shrinks the margin that protects the node. A half latch holds the resting value.
7. Two clocks. A second dynamic stage must not start evaluating before the first has finished (a race), and a footless stage must not precharge while its input is 1 (a collision).

Why these formulas.

• The function. In evaluate the precharge device is off, so the node changes only if the network conducts. An n node is pulled to 0 exactly when its NFETs conduct, so it is $\overline f$f​; a p node is pulled to 1 exactly when its PFETs conduct, so it is $f$ (Chapter 11, Section 4; Chapter 12, Section 6).
• The delay. The course models a conducting transistor of width $W$ as a resistor $R/W$R/W, with $R$ in kΩ·µm; 1 kΩ × 1 fF = 1 ps. Devices in series carry the same current, so their resistances add, and $k$ of them act like one device of width $W_{eq} = 1/\sum(1/W_i)$ (Chapter 7, Section 8). The evaluate delay is then $(R/W_{eq})\,C_{node}$ (Chapter 11, Section 4). The model fits best when the device nearest the node switches last, with the nodes below it already at the rail (Chapter 8, Section 10).
• Dynamic logical effort. Compare the stage with the balanced inverter that pulls as hard as its evaluate path added: $g = C_{in}/\big((1 + R_{pfet}/R_{nfet})\,W_{eq}\big)$ for an n stage, and the mirror, $C_{in}/\big((1 + R_{nfet}/R_{pfet})\,W_{eq}\big)$Rnfet​/Rpfet​)Weq​), for a p stage. For a $k$-high stack of equal devices that is $g = k/2$ at equal strengths, and $k/3$ (n) or $2k/3$ (p) with $R_{pfet} = 2R_{nfet}$2Rnfet​. An input drives only its own devices, never a PFET partner, which is why a dynamic stage beats a static gate (Chapter 12, Sections 2 and 6). The path delay is $\tau_{inv}\sum g_ih_i$τinv​∑gi​hi​, with $h$ the load over the input (Chapter 8, Section 2).

Decisions to make on the way. The strength convention: it sets $\tau_{inv}$ ($2R_{nfet}C_g$2Rnfet​Cg​ at equal strengths, $3R_{nfet}C_g$ with $R_{pfet} = 2R_{nfet}$2Rnfet​) and every $g$g. Which edge the path makes. Which node a load hangs on, and which gates sit on each node. Whether to multiply by 0.69: the chapters don’t; say so when a key does.

Traps. An edge the circuit cannot make (MT24-5b, FN17-2c). Dropping series devices because an internal node is “precharged” (MT23-3b). Leaving out the footer or header, or counting the precharge device. The wrong strength convention (MT17-3c: 9.375 or 6.25 $\tau_{inv}$τinv​). $NM_H$ for $NM_L$ on a p node (MT23-3c). Holding $F$ fixed while the widths you change move a branch (MT24-5c). Delayed reset when no inverter follows the first stage (FN17-2b).

1. MT24-5: a dynamic full adder

MT24-5, p10 (source figure; the circled stage numbers, the reference inverters and the g values are the key’s handwriting). Zoomed in, the clock labels on W1 and on the bottom NFET W2 both carry the bar: clk̄.

MT24-5, p10–12 (Fall 2024, 50 points). Consider the dynamic logic circuit shown above. In this technology, the nFET and pFET have the same drive strength. The gate capacitance per unit width is 1 fF/µm. Assume that the FO1 delay is $\tau_{inv} = 50$ ps. A minimum width device is 1.0 µm. Please ignore source-drain diffusion capacitances and overlap capacitances; that is, worry only about the gate input capacitances of the devices. (a) What logic function does this dynamic circuit perform to outputs Sum and Carry? (15 points) (b) Estimate the delay of the critical path from A falling to Sum falling. In this case, assume Sum is loaded with 500 fF of capacitance and let $W_1 = W_2 = \dots = W_9 = 2\,\mu\mathrm{m}$2μm. (15 points) (c) Now resize $W_4$ and $W_7$ with the goal of minimizing the delay of this path. What is the new path delay? (20 points)

(The stem also says $C_{load} = 1$ pF; part (b) replaces it with 500 fF on Sum.) Read the circuit once, stage by stage, before answering anything.

Reading MT24-5 stage by stage

1. Clocks first, because they decide what kind of stage each one is. W1 (a PFET) and the bottom NFET W2 of stage 1 are on $\overline{\text{clk}}$clk; W3 (a PFET) and the bottom W4 of stage 2 are on clk; one W7 of the Sum stage is on clk, one W8 of the Carry stage on $\overline{\text{clk}}$clk.
2. Precharge, clk = 0, to find each node’s resting value. $\overline{\text{clk}} = 1$1, so W2 is on and pre-discharges stage 1’s node, which we call X, to 0; W3 is on and precharges stage 2’s node, Z, to 1. The clocked W7 (gate clk = 0) and W8 (gate $\overline{\text{clk}} = 1$1) are off, so Sum and Carry are cut off from one rail and hold their values.
3. Evaluate, clk = 1, to find the type of each stage. W1 turns on and W2 off: X is no longer held at 0 and can only be pulled up through PFETs, so stage 1 is a p-type stage, and X rises if its PFETs conduct. W3 turns off and the footer W4 on: Z can only be pulled down through NFETs, so stage 2 is an ordinary n-type stage, and Z falls if its NFETs conduct. This is Lecture 12’s NP arrangement (Chapter 12, Section 5), with the header PFET and the pre-discharge NFET both on $\overline{\text{clk}}$clk, as they must be: the p stage evaluates in the same phase as the n stage.
4. Networks, because they give the functions and the stacks. Stage 1, from W1 down to X: (A ∥ B) in series with C, all in parallel with A in series with B. Stage 2, from Z down to the footer: the NFET gated by X in series with (A ∥ B ∥ C), all in parallel with A, B, C in series (the W5 devices).
5. Output stages, because they set the last edge and the loads on X and Z. Sum: the PFET W6 (gate Z) pulls Sum up; the two W7 NFETs (gates clk and Z) pull it down. Carry: the two W8 PFETs (gates X and $\overline{\text{clk}}$clk) pull up; W9 (gate X) pulls down. In evaluate the clocked devices are on, so these are inverters, Sum $= \overline Z$ and Carry $= \overline X$X; in precharge they hold. So X carries three gates (the X-input NFET, one W8 and W9) and Z two (W6 and the lower W7).

MT24-5a: the functions

MT24-5a, p10 (15 points). What logic function does this dynamic circuit perform to outputs Sum and Carry?

Hint

A PFET conducts on a 0. When does stage 1’s network conduct, and what does that make X?

What it asks. The Boolean functions that appear at Sum and Carry once the circuit has evaluated, as functions of A, B and C. “Dynamic circuit” tells you to read each node in the evaluate phase, stage by stage, with the polarity you found above.

The idea. In evaluate the precharge device is off, so a node changes only if its network conducts. Write each network’s conduction function: series devices are AND, parallel ones OR, and a PFET conducts when its gate is 0, so a PFET gated by A contributes $\overline A$A. An n node is pulled to 0 when its NFETs conduct, so it is the complement of its network’s function; a p node is pulled to 1 when its PFETs conduct, so it equals its network’s function (Chapter 11, Section 4; Chapter 12, Section 6). The tempting slip is to treat stage 1 like an n stage and complement it: that swaps Carry and its complement.

Sum and Carry

1. Stage 1’s network, with each PFET’s input complemented. A PFET conducts when its gate is 0, so A contributes $\overline A$A, and so on. Series is AND and parallel is OR, so the network conducts when $(\overline A + \overline B)\,\overline C + \overline A\,\overline B$AB.
2. Simplify, to recognize it. By De Morgan, $(\overline A + \overline B)\,\overline C = \overline{AB}\;\overline C = \overline{AB + C}$ and $\overline A\,\overline B = \overline{A + B}$A+B​, so the sum is $\overline{(AB + C)(A + B)} = \overline{AB + AC + BC}$AB+AC+BC​.
3. X and Carry. A p node equals its network’s conduction function: $X = \overline{AB + AC + BC}$AB+AC+BC​, the complement of the majority. The Carry stage inverts X: Carry $= AB + AC + BC$BC.
4. Stage 2 and Sum. Its NFETs conduct on 1s: the X-input NFET in series with the parallel A, B, C gives $X(A + B + C)$C), and the three series W5 devices give $ABC$ABC, so the network conducts when $X(A + B + C) + ABC$ABC. An n node is the complement of that, and the Sum stage inverts it again: Sum $= X(A + B + C) + ABC$ABC.
5. Read Sum by the number of inputs at 1, because X depends only on that count. None: $A + B + C = 0$ and $ABC = 0$0, Sum = 0. One: X = 1 (no majority) and $A + B + C = 1$1, Sum = 1. Two: X = 0 and $ABC = 0$0, Sum = 0. Three: $ABC = 1$1, Sum = 1. Sum is 1 for an odd count: $A \oplus B \oplus C$C.

Check. A full adder must satisfy Sum + 2·Carry = A + B + C, the number of inputs at 1, in binary. Zero ones: 0 + 0 = 0. One: 1 + 0 = 1. Two: 0 + 2 = 2. Three: 1 + 2 = 3. ✓ All eight rows pass.

Answer: Sum $= A \oplus B \oplus C$ and Carry $= AB + AC + BC$BC: a full adder. Stage 1 computes $\overline{\text{carry}}$ and stage 2 reuses it, which is why its network is so small.

Remember. An n node is NOT f, a p node is f; then count the inverters. When a later stage takes an earlier node as an input (X here), it is reusing a result: say what that result means.

The answer key agrees

MT24-5b: the delay

MT24-5b, p11 (15 points). Estimate the delay of the critical path from A falling to Sum falling. In this case, assume Sum is loaded with 500 fF of capacitance and let all of $W_1$ to $W_9$ be 2 µm.

Hint

In evaluate, which way can X move, which way can Z move, and so which way can Sum move? Find the edges before you pick any device.

What it asks. The delay along the path A → X → Z → Sum, with every width 2 µm and 500 fF on Sum, in units of $\tau_{inv} = 50$ ps and then in ns. The words “A falling to Sum falling” name the two edges, and the first job is to test them: each dynamic stage can make only one edge in evaluate, so the edges along the path are fixed by the circuit, not by the question.

The idea. Find the edge each stage makes, because the edge decides which devices carry the current, and so the logical effort. Then add the stage gains: delay $= \tau_{inv}\sum g_ih_i$ (Chapter 8, Section 2). Each $g$ compares the stage with the balanced inverter that pulls as hard as the devices making that edge, with the whole stack from the rail counted (Chapter 12, Sections 2 and 6). Each $h$ is all the gate on the node over the stage’s input. With equal strengths the balanced inverter is W/W, a $k$-high stack has $g = k/2$k/2, and $\tau_{inv} = 2R_{nfet}C_g$2Rnfet​Cg​. The tempting move is to take “Sum falling” as given and use the W7 pull-down. That is an edge the clock makes, not A.

MT24-5, p10, marked up by the study guide: the path from A falling (with B = 1, C = 0) through X, Z and W6 to Sum rising.

Which edges, then the efforts

1. Follow the edges from A. Inputs to a p stage evaluate by falling: A falling can turn on its PFETs, so X can only rise. X rising turns on stage 2’s X-input NFET, so Z can only fall. Z falling turns W6 on and the lower W7 off, so Sum rises. (A also drives stage 2’s A NFETs directly, but A falling only turns them off, and an n node cannot rise in evaluate.)
2. Test it on one input pattern. B = 1, C = 0, and A falls from 1 to 0 during evaluate. Before: a majority, so X stays 0, Z stays 1 and Sum is pulled to 0 through the two W7s as soon as clk rises. After: no majority, X rises, Z falls through the X-input NFET and B, and Sum rises to $0 \oplus 1 \oplus 0 = 1$1.
3. So the path ends with Sum rising. Sum can fall only through the W7 stack while Z stays high, and that happens when the clock rises, not because A fell.
4. Stage 1’s effort, with the header counted. The current that lifts X flows from $V_{DD}$ through W1, A and C (or W1, A and B): three 2 µm PFETs in series, $W_{eq} = 2/3\,\mu\mathrm{m}$2/3μm. The W/W inverter with that pull-up has input $4/3\,\mu\mathrm{m}$4/3μm. A appears twice in the network, so it drives two PFETs, 4 µm: $g_1 = 4/(4/3) = 3$3.
5. Stage 2’s effort, with the footer counted. Z discharges through the X-input NFET, one of A, B, C and the footer: again three 2 µm devices, $W_{eq} = 2/3\,\mu\mathrm{m}$2/3μm, reference $4/3\,\mu\mathrm{m}$4/3μm. X drives one 2 µm NFET: $g_2 = 2/(4/3) = 3/2$3/2.
6. The Sum stage on its rising edge. W6 alone pulls Sum up, so the reference is a 2/2 µm inverter (4 µm). Z drives W6 and the lower W7, $2 + 2 = 4\,\mu\mathrm{m}$4μm: $g_3 = 4/4 = 1$1.
7. Electrical efforts: every gate on each node. X drives the X-input NFET and the Carry stage’s W8 and W9 (the other W8 is on $\overline{\text{clk}}$clk): $h_1 = (2 + 2 + 2)/4 = 1.5$1.5; the Carry stage is a branch off the path. Z drives W6 and W7: $h_2 = 4/2 = 2$2. Sum: $h_3 = 500/4 = 125$125.
8. Add the gains. Delay $= g_1h_1 + g_2h_2 + g_3h_3 = 4.5 + 3 + 125 = 132.5\,\tau_{inv} = 6.63\,\mathrm{ns}$6.63ns.

Check. The big term by $(R/W)C$(R/W)C: W6 is $R/2\,\mu\mathrm{m}$ driving $500\,\mu\mathrm{m}\cdot C_g$Cg​, that is $250\,RC_g = 125\,\tau_{inv}$ with $\tau_{inv} = 2RC_g$2RCg​. ✓ Both routes agree, as they must: logical effort is the same model in other units.

Answer: about $132.5\,\tau_{inv} = 6.63$ ns, almost all of it the 2 µm PFET W6 driving 500 fF. The edge this path makes at the output is Sum rising.

Remember. In a dynamic path the edges are set by the stages, not by the question’s wording: n nodes fall, p nodes rise, and each inverter flips the edge. If the named edge is impossible, say in one line which edge you compute and why.

The answer key differs

It uses $g_3 = 4/2 = 2$ (a reference inverter with 1 µm devices, the strength of the two W7s in series) and gets 12.875 ns ($257.5\,\tau_{inv}$257.5τinv​). That is Sum’s falling edge, which a falling A cannot cause. Its $g_1$g1​, $g_2$ and all three $h$ values are right. The rubric gives 13 of the 15 points to the $h$ values, the $g$ values and the delay formula. If you follow the question’s wording instead, the falling edge gives the key’s $257.5\,\tau_{inv}$257.5τinv​.

MT24-5c: resizing W4 and W7

MT24-5c, p12 (20 points). Now resize $W_4$ and $W_7$ with the goal of minimizing the delay of this path. What is the new path delay?

Hint

On the edge you found in (b), which stages does each width drive, and which does it only load?

What it asks. Choose $W_4$ and $W_7$ (every other width stays 2 µm) to make the delay of (b)‘s path as small as possible, and give the new delay. Each name covers several devices: $W_4$ is all five devices labelled W4 in stage 2, $W_7$ both NFETs of the Sum stage. “Resize $W_4$ and $W_7$W7​” therefore means two numbers, and the first job is to see where each one enters the delay.

The idea. Write the delay as a function of the two widths, and ask of each width what it drives and what it loads. A width that only adds load to the path belongs at the minimum. A width that drives one stage and loads the one before would normally be set by the equal-gain rule, $f = F^{1/N}$ (Chapter 8, Section 3). But that rule needs a fixed product of gains, and here X also drives the Carry stage, a fixed 4 µm that does not grow with $W_4$W4​: the branch, and with it $F$F, changes as $W_4$ changes (Chapter 8, Section 8). So balance only what $W_4$ changes. Making $W_4$ larger loads X more (stage 1 slows by $g_1 W_4/C_0$g1​W4​/C0​, with $C_0 = 4\,\mu\mathrm{m}$ the input of stage 1) and makes stage 2 stronger (its gain, $g_2L/W_4$g2​L/W4​, shrinks, with $L$ the load on Z). Their sum is least where the two are equal, which gives $x^* = \sqrt{g_2LC_0/g_1}$g2​LC0​/g1​​. The tempting route, the key’s, is to hold $F$ at its part-(b) value and take $f = F^{1/3}$F1/3; the widths it then picks change that very $F$F.

Resizing for the edge this path makes (Sum rising)

1. List what each width touches, because a width can speed up only the stage it drives. $W_4$ drives Z: all of stage 2 scales with it, so $g_2 = 3/2$ stays and $h_2 = (2 + W_7)/W_4$W7​)/W4​. It also loads X: $h_1 = (4 + W_4)/4$W4​)/4. $W_7$ loads Z through the lower W7. But Sum’s rising edge is W6 alone, so the Sum stage’s gain is $g_3h_3 = \dfrac{2 + W_7}{4}\cdot\dfrac{500}{2 + W_7} = 125$ whatever $W_7$ is.
2. Write the delay. $3(4 + W_4)/4 + 1.5(2 + W_7)/W_4 + 125$125.
3. $W_7$ is pure load: take the minimum, 1 µm. It appears only on top of stage 2’s fraction. A wider W7 adds gate to Z and does nothing for W6, the only device that lifts Sum.
4. Balance what $W_4$ changes. With $W_7 = 1$1, $L = 2 + W_7 = 3\,\mu\mathrm{m}$3μm, and only $0.75W_4 + 4.5/W_4$ moves with $W_4$W4​; the 3 is the Carry branch’s fixed share of stage 1. One part grows with $W_4$ and one shrinks, so the sum is least where they are equal: $0.75W_4 = 4.5/W_4$4.5/W4​, $W_4 = \sqrt6 = 2.45\,\mu\mathrm{m}$2.45μm. That is $x^* = \sqrt{g_2LC_0/g_1}$ (the Fall 2026 recitation’s form), with $g_1 = 3$3, $C_0 = 4$4, $g_2 = 3/2$3/2, $L = 3$3. At the optimum, the delay $W_4$ adds to stage 1 by loading X equals stage 2’s whole gain. The stage gains, 4.84 and 1.84, are not equal, because stage 1 also carries the fixed branch.
5. The delay. $3 + 1.84 + 1.84 + 125 = 131.7\,\tau_{inv} = 6.58\,\mathrm{ns}$6.58ns. Leaving $W_7$ at 2 µm, $W_4 = \sqrt8 = 2.83\,\mu\mathrm{m}$ gives $132.2\,\tau_{inv} = 6.61\,\mathrm{ns}$6.61ns.
6. Why the gain is tiny. $125\,\tau_{inv}$ of the path is W6 driving 500 fF, and W6 is not one of the widths you may change. Shrinking $W_7$ also slows Sum’s other edge, the clocked pull-down when the sum is 0 ($500/W_7\,\tau_{inv}$500/W7​τinv​); in a real design you would keep it.

The question’s choice of widths only makes sense for Sum’s falling edge, the one the key computes in (b): $W_7$ then drives Sum. Solved that way, with the sizes kept consistent:

If you read Sum's falling edge, as the key does

1. The Sum stage now pulls down through the two W7s in series, so its gain is $g_3h_3 = 500/W_7$500/W7​. $W_6$ stays 2 µm, so $g_3 = (2 + W_7)/W_7$ changes as $W_7$ grows: $G$ is not fixed.
2. The branch at X moves too. It is $(4 + W_4)/W_4$W4​)/W4​, so $B$ (and with it $F$F) is not fixed either. The delay is $0.75(4 + W_4) + 1.5(2 + W_7)/W_4 + 500/W_7$500/W7​.
3. Equal gains, kept consistent. Because $F$ moves, set all three gains equal to $t$ and solve for the widths that really give $t$t: $W_4 = t/0.75 - 4$4, $W_7 = 500/t$500/t, and $1.5(2 + W_7)/W_4 = t$t. That gives $t = 9.49$9.49, $W_4 = 8.65\,\mu\mathrm{m}$8.65μm, $W_7 = 52.7\,\mu\mathrm{m}$52.7μm, delay $28.5\,\tau_{inv} = 1.42\,\mathrm{ns}$1.42ns.
4. The exact minimum (the widget below) is $28.0\,\tau_{inv} = 1.40\,\mathrm{ns}$ at $W_4 = 11.2\,\mu\mathrm{m}$11.2μm, $W_7 = 61.2\,\mu\mathrm{m}$61.2μm: equal gains are within 2%.

Check. Try the neighbours on the rising edge: the part that moves, $0.75W_4 + 4.5/W_4$4.5/W4​, is 3.75 at both $W_4 = 2$ and $W_4 = 3$3, and 3.67 at $\sqrt6$6​. The minimum lies between them, and it is shallow: the whole resizing saves only $0.8\,\tau_{inv}$ ($132.5 \to 131.7$132.5→131.7).

Answer: on the edge the path of (b) makes (Sum rising), $W_7$ to the minimum, 1 µm, and $W_4 \approx 2.45\,\mu\mathrm{m}$2.45μm: $131.7\,\tau_{inv} \approx 6.58$ ns, barely better than (b), because the fixed W6 sets $125\,\tau_{inv}$125τinv​. On the falling edge the key intends: about $28\,\tau_{inv} \approx 1.4$ ns, with $W_4 \approx 9$–$11\,\mu\mathrm{m}$ and $W_7 \approx 53$–$61\,\mu\mathrm{m}$61μm.

Remember. Before resizing, ask what each width drives and what it loads: pure load goes to the minimum. When a width also feeds a fixed branch, balance the delay it adds against the delay it saves; $F^{1/N}$ is only a guess.

The answer key differs

It says 2.25 ns with $W_4 = 6.7\,\mu\mathrm{m}$ and $W_7 = 64.6\,\mu\mathrm{m}$64.6μm. It takes $F = 375 \times 9 = 3375$ from part (b), $f = \sqrt[3]{3375} = 15$ and $45\,\tau_{inv} = 2.25\,\mathrm{ns}$2.25ns, then sizes $W_7 = 64.6\,\mu\mathrm{m}$ from $2 \cdot 500/(2 + W_7) = 15$ and $W_4 = 6.7\,\mu\mathrm{m}$ from $1.5(2 + 64.6)/W_4 = 15$15. But its widths change its $F$F: with $W_4 = 6.7$ the first gain is $3 \times 10.7/4 = 8.0$8.0, not 15, and with W6 held at 2 µm the Sum stage’s falling gain is $500/64.6 = 7.7$7.7, not 15. Its widths actually give $8.0 + 14.9 + 7.7 = 30.7\,\tau_{inv} = 1.53\,\mathrm{ns}$ on the falling edge (or $38.0\,\tau_{inv} = 1.90\,\mathrm{ns}$ even with its own $g_3 = 2$2), not 2.25 ns. Its grading note admits that equal gains are “not exactly correct” with a branch. On the rising edge its widths make the path slower than (b): $147.9\,\tau_{inv} = 7.40$ ns, because a 64.6 µm $W_7$ is pure load.

MT24-5cFN12-8b

Sum rises (the edge this path makes)Sum falls (the key’s edge)

W₄

2.00 µm

W₇

2.00 µm

as in (b): all 2 µmthe key’s sizeslowest delay

stage 1 (p-type, X rises)

gain 4.50

stage 2 (n-type, node falls)

gain 3.00

Sum stage (W6 pulls Sum up)

gain 125.00

delay Σ gains

132.50 τ_inv = 6.625 ns

path effort F = Π gains

1687.5

lowest delay

131.67 τ_inv = 6.584 ns at W4 = 2.45, W7 = 1.00 µm

Each stage's gain is g·h at the widths set above; the path delay is their sum. Solid line: the delay as W₇ moves with the other widths as set (orange point); dashed: with the other widths re-chosen for every value of W₇. The green point is the lowest delay within the slider ranges. Watch F: it changes whenever a width also sits beside a fixed load or a fixed device, which is why equal gains are then only close to the best. Gate capacitance only.

What to notice.

• On “Sum rises”, drag $W_7$W7​: the delay only grows. The dashed curve (with $W_4$ re-chosen) bottoms out at the left end.
• On “Sum falls”, press “the key’s sizes” and read $F$F: it is not 3375, and the stage gains are far from 15 each.
• In both readings $F$ changes as you move $W_4$W4​, because X also drives the fixed Carry stage. Compare FN12-8b (the second button), where nothing sits beside the resized widths: there $F$ stays fixed and the lowest delay has equal gains.

2. MT23-3: a p-type domino XOR

MT23-3, p7 (source figure; faint handwriting from the key’s next page shows through).

MT23-3, p7–9 (Fall 2023, 32 points). Consider the domino gate shown above. Let $C_g = 1\,\mathrm{fF/\mu m}$1fF/μm, $R_{nfet} = 1\,\mathrm{k\Omega\cdot\mu m}$ and $R_{pfet} = 2\,\mathrm{k\Omega\cdot\mu m}$2kΩ⋅μm. Let C = 50 fF. (a) What logic function does this domino gate perform (Y as a function of A and B)? (8 points) (b) If M4 = 10 µm and M1 = M6 = M7 = M8 = M9 = 3 µm, what is the delay from B falling to Y falling? Assume that M4 is four times stronger than M3 (that is, at the same overdrive, it has four times the drain current). (10 points) (c) If M4 is four times stronger than M3, how do the static DC noise margins of this inverter compare with the case the M4 and M3 are sized for equal drive strength? How might this be significant in this circuit? (8 points) (d) How might the $NM_L$ on $V_n$ be improved in this circuit with the addition of a transistor? (6 points)

Reading MT23-3

1. The clocked devices first, because they decide the stage’s type. CLK drives M1, a PFET from $V_{DD}$VDD​, and M5, an NFET from $V_n$ to ground.
2. The two phases. CLK = 1: M5 on, M1 off, so $V_n$ is pre-discharged to 0. CLK = 0: M1 on, M5 off, and the PFET network may pull $V_n$ up. The node rests at 0 and can only rise through PFETs, so this is a p-type stage, and it evaluates while CLK is low, the phase in which an n-type stage on the same clock would precharge (Chapter 12, Section 5).
3. The network, because it gives the function and the stack. (M6, gate A ∥ M7, gate $\overline B$B) in series with (M8, gate $\overline A$ ∥ M9, gate B).
4. The inverter, because it sets the last edge and $V_n$‘s load. M3 (PFET) and M4 (NFET) invert $V_n$ to Y, which drives C. So $V_n$ carries the two gates M3 and M4.

MT23-3a: the function

MT23-3a, p7 (8 points). What logic function does this domino gate perform (Y as a function of A and B)?

Hint

Which value of each input turns its PFET on? Then: are the two pairs in series or in parallel?

What it asks. Y as a Boolean function of A and B, after the gate has evaluated. The words “domino gate” tell you there is a dynamic node and an inverter; the figure tells you that the node is p-type.

The idea. This is MT24-5a’s reading with a single p stage. A PFET conducts when its gate is 0, so write each PFET’s input complemented; parallel devices are OR, series ones AND. A p node is pulled up exactly when its network conducts, so it equals the conduction function, and the inverter complements it (Chapter 12, Section 6). The tempting slip is to read the PFETs as NFETs: that gives the complement of every term, and the opposite answer.

Y

1. The upper pair. M6 conducts for A = 0 and M7 for B = 1, and they are in parallel: the pair conducts for $\overline A + B$B.
2. The lower pair. M8 conducts for A = 1 and M9 for B = 0: $A + \overline B$B.
3. The two pairs in series must both conduct: $(\overline A + B)(A + \overline B) = AB + \overline A\,\overline B$AB, the XNOR.
4. The node and the inverter. A p node equals its network’s conduction function, so in evaluate $V_n = \overline{A \oplus B}$A⊕B​, and $Y = \overline{V_n} = A \oplus B$B.

Check. Walk the truth table through the transistors (A B → Y). 00: M6 and M9 on, a path from M1 to $V_n$Vn​, so $V_n$ rises and Y = 0. 01: M6 and M7 on, but M8 and M9 off, so $V_n$ stays 0 and Y = 1. 10: M8 and M9 on, but M6 and M7 off, Y = 1. 11: M7 and M8 on, $V_n$ rises, Y = 0. ✓ That is the XOR.

Answer: $Y = A \oplus B$B.

Remember. For a p stage, complement each PFET’s input, then read series as AND and parallel as OR; the node is that function itself.

The answer key agrees

MT23-3b: the delay

MT23-3b, p8 (10 points). If M4 = 10 µm and M1 = M6 = M7 = M8 = M9 = 3 µm, what is the delay from B falling to Y falling? Assume that M4 is four times stronger than M3.

Hint

With A = 0 and B falling, which PFETs carry the charge that lifts $V_n$Vn​, all the way from $V_{DD}$VDD​?

What it asks. The delay from B falling to Y falling, in ps, with the widths given and M3 not given: you know only that M4 is four times stronger. Two phrases decide the method: “B falling” picks the PFET that switches, and so the path; “four times stronger” sets M3’s width, which you need for $V_n$‘s load.

The idea. Each stage takes $(R/W)\,C$(R/W)C: the conducting devices act as a resistor that charges or discharges the node (Chapter 11, Section 4). Devices in series carry the same current, so their resistances add (Chapter 7, Section 8): three 3 µm PFETs at $R_{pfet} = 2\,\mathrm{k\Omega\cdot\mu m}$ give $3 \times 2/3\,\mathrm{k\Omega}$2/3kΩ. The clocked header M1 is one of them: it is on during evaluate and every bit of charge passes through it. The chapters don’t multiply by 0.69; the key does, so give both. The tempting shortcut, the key’s, is to count only M9 because “the intermediate node is precharged”. The node between the pairs does sit at $V_{DD}$VDD​, but with diffusion capacitance ignored it stores no charge: all the charge that lifts $V_n$ still comes from $V_{DD}$ through M1, M6 and M9. The charged node only means that M9, nearest $V_n$Vn​, switches with its source already high, the fast case in which the model fits well (Chapter 8, Section 10).

MT23-3, p7, marked up by the study guide: with A = 0, B falling lifts $V_n$ through M1, M6 and M9 in series; then M4 pulls Y down.

B falling to Y falling

1. M3’s width, from the strength ratio, because M3’s gate is half of $V_n$‘s load. “Four times stronger at the same overdrive” means four times the current, so a quarter of the resistance. M4 is $1\,\mathrm{k\Omega\cdot\mu m}/10\,\mu\mathrm{m} = 0.1\,\mathrm{k\Omega}$0.1kΩ, so M3 is $0.4\,\mathrm{k\Omega}$0.4kΩ: a PFET of $2/0.4 = 5\,\mu\mathrm{m}$5μm.
2. The edges and the path. In evaluate, B falling turns M9 on and M7 off. For $V_n$ to rise, the upper pair must conduct without M7: A = 0, so M6 is on (and M8 off). $V_n$ rises through M1, M6 and M9 in series, and Y falls through M4.
3. Stage 1’s resistance: the series PFETs add. $3 \times (2\,\mathrm{k\Omega\cdot\mu m}/3\,\mu\mathrm{m}) = 3 \times 2/3 = 2\,\mathrm{k\Omega}$2kΩ.
4. Stage 1’s load: the inverter’s two gates. $V_n$ drives M3 and M4, $15\,\mu\mathrm{m} \times 1\,\mathrm{fF/\mu m} = 15\,\mathrm{fF}$15fF. Delay $2\,\mathrm{k\Omega} \times 15\,\mathrm{fF} = 30\,\mathrm{ps}$30ps.
5. Stage 2: M4 alone pulls Y down. $0.1\,\mathrm{k\Omega} \times 50\,\mathrm{fF} = 5\,\mathrm{ps}$5ps.
6. Add. Total 35 ps; with the key’s $0.69RC$0.69RC, $24.2\,\mathrm{ps}$24.2ps.

Check. Logical effort gives the same number (Chapter 12, Section 6). $\tau_{inv} = 3R_{nfet}C_g = 3 \times 1 \times 1 = 3\,\mathrm{ps}$3ps. Stage 1: a three-high p stack, $g = 2k/3 = 3/1.5 = 2$2, $h = 15/3 = 5$5. Stage 2: M4’s balanced inverter is 20/10 µm, so $g = 15/30 = 0.5$0.5, $h = 50/15$50/15. $10 + 1.67 = 11.67\,\tau_{inv} = 35\,\mathrm{ps}$35ps. ✓

Answer: 35 ps by $(R/W)C$(R/W)C, as the chapters compute delays (24.2 ps if you multiply by 0.69, as the key does). Stage 1 is 30 of the 35.

Remember. Count every device between the rail and the node, the clocked header included; series resistances add whatever the internal nodes held. A strength ratio sets a missing width.

The answer key differs

It gives 10.35 “ns”: it counts stage 1 as one PFET ($2000/3\,\Omega$2000/3Ω, 6.9 ps with the 0.69) because “the intermediate node is precharged”, and it labels picoseconds as nanoseconds. The charged internal node is why the delay model fits well here; it does not take M1 and M6 out of the path (see the idea above). The key’s stage 2 (3.45 ps with the 0.69) is right.

MT23-3c: the skewed inverter’s noise margins

MT23-3c, p8 (8 points). If M4 is four times stronger than M3, how do the static DC noise margins of this inverter compare with the case the M4 and M3 are sized for equal drive strength? How might this be significant in this circuit?

Hint

A strong NFET pulls Y down sooner. Does the inverter’s threshold move up or down, and which way can noise push a resting $V_n$Vn​?

What it asks. Two things. First, how the static noise margins of the M3/M4 inverter change when M4 is four times stronger than M3, compared with equal strengths. Second, why that matters “in this circuit”: the inverter’s input is not an ordinary node but $V_n$Vn​, a p-type dynamic node.

The idea. A noise margin runs from where a node sits to where the next gate starts to amplify, the VTC’s −1 points: $NM_L = V_{IL} - V_{OL}$ and $NM_H = V_{OH} - V_{IH}$ (Chapter 6, Section 4). Changing the strength ratio slides the curve sideways and trades one margin for the other; this is MT24-1c’s question with the NFET made stronger instead of the PFET (M3’s noise-margin approach, MT24-1c). The second half is about the node: which margin protects it depends on where it rests and which way noise can push it.

Noise margins and why they matter

1. Why the inverter is skewed at all. Y’s falling edge carries the logic ($V_n$Vn​ rises in evaluate), and its rising edge only resets Y during the pre-discharge, which has time. So the inverter after a p node gets the strong NFET (the mirror of Chapter 11, Section 7).
2. The curve slides left. The output switches where the NFET’s current matches the PFET’s. A stronger NFET matches the PFET at a smaller input, so the switching threshold moves down, and with it $V_{IL}$ and $V_{IH}$VIH​. $V_{OH}$ and $V_{OL}$VOL​, on the flat ends, barely move.
3. The margins follow. $NM_L = V_{IL} - V_{OL}$ shrinks, because its first term fell. $NM_H = V_{OH} - V_{IH}$ grows, because the term it subtracts fell.
4. In numbers added. In Chapter 6’s square-law model ($V_{DD} = 5\,\mathrm{V}$VDD​=5V, $V_T = \pm 1\,\mathrm{V}$±1V, $\lambda = 0.05$0.05; illustrative): equal strengths switch at 2.50 V with $NM_L = NM_H = 1.67\,\mathrm{V}$1.67V; an NFET four times stronger switches at 2.01 V with $NM_L = 1.04\,\mathrm{V}$ and $NM_H = 2.51\,\mathrm{V}$2.51V.
5. Why it matters here: the node rests at 0 and floats. $V_n$ is a p node. It rests at 0, and when the XNOR is 0 it floats at 0 through the whole evaluate phase, with nothing driving it. Leakage through the off PFETs (Chapter 11, Section 8), charge sharing (Section 10) and coupling can only pull it up, toward the lowered threshold. The margin that protects it is $NM_L$NML​, the one that shrank; and a dynamic node that flips cannot recover until the next pre-discharge.

Check. The mirror of MT24-1c. There a stronger PFET slid the curve right, and $NM_L$ grew while $NM_H$ shrank. Here a stronger NFET slides it left, so the trade must go the other way, and it does: in the model $NM_L$ falls by 0.63 V and $NM_H$ rises by 0.84 V.

Answer: $NM_L$ is smaller and $NM_H$ larger than with equal strengths. It matters because $V_n$ sits at a floating 0 and noise can only push it up: the small $NM_L$ is exactly the margin it needs.

Remember. Skewing the inverter toward the logic edge moves its threshold toward the dynamic node’s resting value, and shrinks the margin that protects that value: $NM_L$ after a p node, $NM_H$ after an n node.

The answer key differs

It states the first part correctly, then ends “With a smaller $NM_H$ the noise can switch the inverter”: that should read $NM_L$NML​.

The widget starts with the NFET four times stronger (strength ratio 0.25). Move the ratio to 1 and back, and watch $V_{IL}$VIL​, $V_{IH}$ and the two margins.

input V_in

2.00 V

PFET strength ÷ NFET strength

0.25

output slope λ (how far the saturated curves tilt)

0.05 V⁻¹

At V_in = 2.00 V: NFET saturated, PFET saturated; V_out = 2.50 V.

current through both devices

0.141 mA

gain dV_out/dV_in here

−33.75

(V_IL, V_OH)

(1.447, 4.800) V

(V_IH, V_OL)

(2.289, 0.406) V

NM_L = V_IL − V_OL

1.041 V

NM_H = V_OH − V_IH

2.511 V

largest gain (size)

34

Top: the NFET current rises with V_out and the PFET current falls; the output settles where they are equal. Bottom: that crossing traced for every V_in. The shaded band is where the gain is larger than 1 in size; the dashed segments have slope −1. The devices follow Chapter 4's long-channel (square-law) model with the saturated curves tilted by (1 + λV_DS), at the lecture's V_DD = 5 V and V_T = ±1 V; the strengths are illustrative. The lecture draws the curves without a model, so read the shapes, not the decimals. PFET ÷ NFET strength = 0.25 means β_p = 0.25 β_n.

MT23-3d: one transistor for the low noise margin

MT23-3d, p9 (6 points). How might the $NM_L$ on $V_n$ be improved in this circuit with the addition of a transistor?

Hint

What could hold $V_n$ at 0 while Y is high, and let go by itself once Y falls?

What it asks. One added transistor that improves $NM_L$ on $V_n$Vn​: how much noise the resting 0 can take before the inverter misreads it. Part (c) found why it is needed: the node floats at 0 and its margin is small.

The idea. A floating node has no defence: any charge that leaks onto it stays. The cure is to stop it floating, with a weak device that holds the resting value, driven by the inverter’s output so that it turns itself off once the node has really switched. That is Lecture 11’s half latch (Chapter 11, Section 8), drawn there for an n node as a weak PFET to $V_{DD}$VDD​; a p node needs its mirror. It must be weak, because during a real evaluation the network has to overpower it (Chapter 11, Section 9).

The half latch for a p node

1. What is needed. Something that holds $V_n$ at 0 while it should be 0, and lets go when the PFETs really pull it up.
2. Mirror Lecture 11’s half latch. For an n node it is a weak PFET from $V_{DD}$VDD​, gated by the inverter’s output. The node here rests at 0 instead of 1, so swap the rail and the device: a weak NFET from $V_n$ to ground, gated by Y.
3. At rest it holds. While $V_n = 0$0, Y = 1 and the NFET is on: noise current is drained to ground, and $V_n$ stays at 0.
4. In a real evaluation it lets go. The network fights the NFET until $V_n$ passes the inverter’s threshold; then Y falls and turns the NFET off, and the fight ends.
5. Keep it weak, because in a real evaluation the PFET network must overpower it before Y can fall and switch it off: about one tenth of the evaluate network’s strength (Chapter 11, Section 9). added Here the worst pull-up path is three 3 µm PFETs, one 1 µm PFET, as strong as a 0.5 µm NFET; a tenth of that is a 0.05 µm NFET, below any minimum width, so it needs a series device or a longer channel.

MT23-3d, p9: the key’s sketch of the NFET half latch.

Check. Run the loop through both phases. Pre-discharge: $V_n = 0$0, Y = 1, the NFET is on and only helps M5. Evaluate with the XNOR 0: the NFET keeps holding the 0. Evaluate with the XNOR 1: $V_n$ rises, Y falls, the NFET turns off, and $V_n$ is free to reach $V_{DD}$VDD​. ✓ It never fights a correct result for longer than the switching itself.

Answer: add a weak NFET from $V_n$ to ground, its gate driven by Y: a half latch that holds the resting 0.

Remember. A half latch holds a dynamic node’s resting value, is driven by the node’s own inverter, and is weak. For a p node, everything is mirrored: an NFET to ground.

The answer key agrees

It draws the same circuit (the sketch above).

3. MT17-3c: a footed dynamic stack

MT17-3c, p6 (source figure).

MT17-3, p5–6 (Fall 2017). Consider the following circuits. In each case, please estimate the delays specified as a multiple of the fanout-of-one delay, $\tau_{inv}$τinv​, for the technology. Assume that the nFET and pFET have the same strength in this problem. [Handwritten addition: assume 2 fF/µm of gate cap.] (c) Calculate the A-rising-to-Y-falling delay in evaluation (clk = 1) for B = 1. (8 points)

Hint

Which devices carry the current that discharges Y, and how many $R_{nfet}C_g$ is one $\tau_{inv}$ when the two devices have the same strength?

What it asks. The time for Y to fall after A rises, in evaluate (clk = 1) with B already 1, in units of $\tau_{inv}$τinv​. Two phrases decide the answer: “in evaluation” (so the precharge PFET is off) and, in the stem, “the nFET and pFET have the same strength” (so $\tau_{inv}$ is the W/W inverter’s FO1 delay). The stem’s handwritten 2 fF/µm turns the 50 fF into gate width.

The idea. The evaluate delay is $(R/W_{eq})\,C$(R/Weq​)C: the node discharges through the whole evaluate path, the footer included, and the stack rule turns that path into one equivalent device (Chapter 11, Section 4). Then divide by $\tau_{inv}$ in the page’s convention. The two usual slips are leaving out the footer (Chapter 11 shows it costs 50% here: $12.5$ against $18.75\,R_{nfet}C_g$18.75Rnfet​Cg​) and using $\tau_{inv} = 3R_{nfet}C_g$ out of habit.

The evaluate delay

1. Which devices conduct. In evaluate the 1 µm PFET is off and plays no part. Y falls through A, B and the clocked footer, 4 µm each, in series.
2. Why the model fits here. B = 1 and clk = 1 are already on, so the nodes below A are already at ground: A, nearest the output, switches like the top of a stack, the case the model describes well (Chapter 8, Section 10).
3. The stack as one device. Three 4 µm devices in series act as one $4/3\,\mu\mathrm{m}$ NFET.
4. The load in µm of gate, so that it multiplies $C_g$Cg​: $50/2 = 25\,\mu\mathrm{m}$25μm.
5. $\tau_{inv}$ in the page’s convention. “Same strength”: the FO1 inverter is W/W, $\tau_{inv} = (R_{nfet}/W)(2W C_g) = 2R_{nfet}C_g$2Rnfet​Cg​.
6. The delay. $\dfrac{R_{nfet}}{4/3} \times 25\,C_g = 18.75\,R_{nfet}C_g = 9.375\,\tau_{inv}$9.375τinv​.

Check. Logical effort gives the same (Chapter 12, Section 2): a three-high n stack at equal strengths has $g = k/2 = 3/2$3/2; A is 4 µm, so $h = 25/4 = 6.25$6.25, and the gain is $1.5 \times 6.25 = 9.375$9.375. ✓

Answer: $9.375\,\tau_{inv}$ (about 9.4). With $R_{pfet} = 2R_{nfet}$ instead, $\tau_{inv} = 3R_{nfet}C_g$ and the same circuit is $6.25\,\tau_{inv}$6.25τinv​: read the convention first.

Remember. Evaluate delay = the whole stack from the node to ground, footer in, precharge device out; then divide by $\tau_{inv}$ in the question’s strength convention.

The answer key agrees

Check yourself Same circuit, but A = 1 and B rises (clk = 1). Is the delay from B rising larger, smaller or the same as from A rising? What does the course's model give?

Larger. With A on and B off, the node between A and B has been charged from Y through A to about V_DD − V_T; B must discharge it before Y can fall, and the lecture says the penalty grows roughly as the square of the stack height (Chapter 8, Section 10). The (R/W)C model still gives 9.375 τ_inv: it describes the device nearest the output and has no term for that internal charge. (MT17-3d asks the same of a NAND4; page M3 solves it.)

4. Extra drill: FN12-8, a domino path

From the Fall 2012 final, adapted as a drill: the midterms have only one domino-sizing problem (MT24-5c). It is re-solved like the rest.

FN12-8, p12 (source figure; the arrows and stage numbers are the key’s).

FN12-8, p12–13 (Fall 2012 final, 30 points). Consider the following path of domino logic. The gate capacitance per unit width is 2 fF/µm. The unit width nFET resistance is 4 kΩ, while the unit width pFET resistance is 8 kΩ. Assume that the minimum device width is 0.5 µm. Please ignore source-drain diffusion capacitances and overlap capacitances. (a) Estimate the evaluation delay from A to G if $W_1 = W_2 = W_3 = W_4 = 1\,\mu\mathrm{m}$1μm. Assume that $\phi = 1$ (evaluate phase) and that E is high (already evaluated) and B is low. (15 points) (b) Assume that $W_1$ is fixed at 1 µm, but you are free to tune $W_2$W2​, $W_3$ and $W_4$W4​. Find approximate values of $W_2$W2​, $W_3$ and $W_4$ to minimize evaluation delay and estimate the new delay of your resized network. (15 points)

FN12-8a. The evaluation delay (15 points).

Hint

Mark the logical edge of each of the four stages first; each stage’s $g$ then comes from the devices that make that edge.

What it asks. The delay from A to G through all four stages in evaluate, with every resizable width at 1 µm, in ns. The conditions pick the path: $\phi = 1$ (evaluate), E already high (so stage III waits only for D), B low (so stage I discharges through A alone). The strengths are 4 and 8 kΩ·µm: $R_{pfet} = 2R_{nfet}$2Rnfet​.

The idea. A domino path alternates dynamic stages and inverters, and each makes one edge: an n node falls, and the inverter after it rises (Chapter 12, Section 1). Add the stage gains, delay $= \tau_{inv}\sum g h$τinv​∑gh, with $\tau_{inv} = 3R_{nfet}C_g$ in this convention. A dynamic stage’s $g$ is $k/3$ for a $k$-high stack, footer counted (Chapter 12, Section 2). The inverters are skewed (PFET 4W over NFET W), and only their rising edge counts, so compare each with the balanced inverter that has the same PFET: 4/2 µm, input 6 µm (Chapter 12, Section 4).

FN12-8a: the evaluation delay

1. τ_inv and the load, in the exam’s units. $\tau_{inv} = 3R_{nfet}C_g = 3 \times 4\,\mathrm{k\Omega\cdot\mu m} \times 2\,\mathrm{fF/\mu m} = 24\,\mathrm{ps}$24ps. The load is $500/2 = 250\,\mu\mathrm{m}$ of gate.
2. The logical edges, because they pick the devices: C falls (I), D rises (II), F falls (III), G rises (IV).
3. Stage I: A and the footer in series. B is low, so its parallel device doesn’t help. Two 1 µm devices act as 0.5 µm; the reference is $3 \times 0.5 = 1.5\,\mu\mathrm{m}$1.5μm; A is 1 µm: $g = 2/3$2/3. C drives II’s $4 + 1 = 5\,\mu\mathrm{m}$5μm: $h = 5$5, gain 3.33.
4. Stage II on its rising edge. Its 4 µm PFET pulls D up; the balanced inverter with that PFET is 4/2 µm (6 µm); its input is 5 µm: $g = 5/6$5/6. D drives III’s 1 µm D NFET: $h = 1/5$1/5, gain 0.167.
5. Stage III: D, E and the footer, a three-high 1 µm stack: $g = k/3 = 1$1. F drives IV’s 5 µm: gain 5.
6. Stage IV, like II: $g = 5/6$5/6, $h = 250/5 = 50$50: gain 41.67.
7. Add. Delay $= 3.33 + 0.17 + 5 + 41.67 = 50.17\,\tau_{inv} = 1.20\,\mathrm{ns}$1.20ns.

Check. The big term by $(R/W)C$(R/W)C: stage IV’s 4 µm PFET is $8/4 = 2\,\mathrm{k\Omega}$2kΩ, driving 500 fF, so $1000\,\mathrm{ps}$1000ps, and $1000/24 = 41.67\,\tau_{inv}$41.67τinv​. ✓ It also shows where the time goes: a 1 µm-sized last stage against 500 fF.

Answer: (a) $50.17\,\tau_{inv} = 1.20$ ns.

Remember. In a domino path, mark the edges first: n nodes fall, inverters rise. A skewed inverter’s $g$ for its fast edge compares it with the balanced inverter that has the same strong device.

The answer key differs

It adds its own four gains to 50.76 (they add to 50.17), so it gets 1.22 ns. Its gains and its method are right.

FN12-8b. Resizing W2, W3 and W4 (15 points).

Hint

Nothing branches off this path. Multiply the four gains with $W_2$–$W_4$ as unknowns: what is left?

What it asks. Keep $W_1$ at 1 µm, choose $W_2$W2​, $W_3$ and $W_4$ for the least evaluation delay, and estimate it. Fixing $W_1$ fixes the path’s input; without it, you could make everything huge.

The idea. The equal-gain rule of M4’s MT23-5b applies exactly here. Each inner width is the load of one stage and the size of the next, so it cancels from the product of the gains: $F = GH$ is fixed. With a fixed product, the sum is smallest when every gain is the same, $f = F^{1/N}$F1/N: making one stage faster forces another to be slower by a larger factor (Chapter 8, Section 3). This is what MT24-5c lacked: there a fixed branch at X moved $F$F; here nothing sits beside the resized widths.

FN12-8b: resizing W2, W3, W4

1. F is fixed, so find it. With $W_1$ fixed, A’s input is 1 µm and the load 250 µm: $H = 250$250. $G = \tfrac23 \cdot \tfrac56 \cdot 1 \cdot \tfrac56 = 0.463$0.463. Nothing branches off and every stage keeps its proportions, so $F = GH = 115.7$ whatever $W_2$–$W_4$ are.
2. Equal gains. $f = 115.7^{1/4} = 3.28$3.28; delay $4 \times 3.28 = 13.12\,\tau_{inv} = 315\,\mathrm{ps}$315ps.
3. Size back from the load, because the last stage’s equation has only one unknown. IV: $\tfrac56 \cdot 250/(5W_4) = 3.28$3.28, so $W_4 = 12.7\,\mu\mathrm{m}$12.7μm. III: $5W_4/W_3 = 3.28$3.28, so $W_3 = 19.4\,\mu\mathrm{m}$19.4μm. II: $\tfrac56 \cdot W_3/(5W_2) = 3.28$3.28, so $W_2 = 0.98\,\mu\mathrm{m}$0.98μm.
4. Stage I checks the work. $\tfrac23 \times 5 \times 0.98 = 3.28$3.28. ✓ Every width is above the 0.5 µm minimum.

Check. From 1.20 ns to 315 ps, about 3.8 times faster, by resizing alone. A gain of 3.28 per stage is inside the 3–4 that Chapter 8 aims for (Section 4), so four stages are about right for this $F$F.

Answer: (b) $W_2 \approx 1.0$1.0, $W_3 \approx 19.4$19.4, $W_4 \approx 12.7\,\mu\mathrm{m}$12.7μm, about 315 ps. FN12-8b is also the second case of the widget in Section 1.

Remember. No branch and nothing fixed beside the resized widths: $F$ is fixed, take $f = F^{1/N}$F1/N, size back from the load, and let the first stage check the arithmetic.

The answer key differs

It gives 128.94 for the product of the gains (it is 115.7, or 115.9 with its rounded gains). From $f = 3.37$ it gets 323 ps and $W_4 = 12.4$12.4, $W_3 = 18.6$18.6, $W_2 = 0.92\,\mu\mathrm{m}$0.92μm. Its method is right.

5. Extra drill: FN17-2, two dynamic stages on two clocks

From the Fall 2017 final, adapted as a drill on the race and the collision (Chapter 11, Sections 4–5; Chapter 12, Section 7).

FN17-2, p4 (source figure).

FN17-2, p4–5 (Fall 2017 final, 25 points). Consider the dynamic circuit shown above. Let the fanout-of-one delay of this technology be $\tau_{inv} = 100$ ps. Let the gate capacitance per unit device width be 2 fF/µm. (a) What relation must the rising edge of $\phi_1$ have with respect to the rising edge of $\phi_1'$ to avoid a race condition? Explain. Please be precise with calculated delay values. (10 points) (b) What relation must the falling edge of $\phi_1$ have with respect to the falling edge of $\phi_1'$ to avoid collisions? Explain. Please be precise with calculated delay values. (10 points) (c) With $\phi_1$ and $\phi_1'$ as chosen in (a) and (b), what logic function does the circuit perform? What is the delay from A rising to Y falling? (5 points)

Two facts in the figure decide every part. The first-stage outputs $Y_1$ and $Y_2$ are bare dynamic nodes: no inverter follows them, so they sit at 1 at the start of each evaluation and go back to 1 at each precharge. And the second stage has no footer, so nothing stops its NFETs from conducting while it precharges. Like the key, take $R_{pfet} = 2R_{nfet}$2Rnfet​.

FN17-2a. The race (10 points).

Hint

At the instant the first stage starts evaluating, what are $Y_1$ and $Y_2$Y2​, and what would they do to a second stage that is already evaluating?

What it asks. How much later than $\phi_1$ the clock $\phi_1'$ must rise so that the second stage never evaluates on a wrong input, with the delay computed. “Race condition” names the hazard; “precise with calculated delay values” asks for the first stage’s evaluate delay in ps.

The idea. A dynamic node starts every evaluation at 1, its precharged value. Fed straight into the next dynamic stage, that 1 turns on the next stage’s NFET before the first stage has decided, and whatever charge the second node loses in the meantime is lost for good (Chapter 11, Section 5). Domino cures this with an inverter; this circuit has none, so the second stage has to wait: its evaluation may start only once the first stage’s outputs are final. The wait is the first stage’s evaluate delay, $g h\,\tau_{inv}$ with the footer in the stack.

FN17-2a: the race

1. What goes wrong if both clocks rise together. $Y_1$ and $Y_2$ are precharged to 1, so both second-stage NFETs are on as evaluation starts, and Y begins to discharge even when $Y_1$ and $Y_2$ are about to fall: the race.
2. The rule. The second stage may start evaluating only after the first has finished: $\phi_1'$ rises at least one first-stage evaluate delay after $\phi_1$ϕ1​.
3. The first stage’s effort. A, B and the footer are three 1 µm NFETs in series, $W_{eq} = 1/3\,\mu\mathrm{m}$1/3μm; the 2:1 reference has input $3 \times 1/3 = 1\,\mu\mathrm{m}$1μm; A is 1 µm: $g = k/3 = 1$1.
4. Its load. $Y_1$ drives one 5 µm NFET of the second stage: $h = 5$5. (The first stage’s own PFET has its gate on $\phi_1$ϕ1​, not on $Y_1$Y1​.)
5. The delay. $g h = 5\,\tau_{inv} = 500\,\mathrm{ps}$500ps.

Check. By $(R/W)C$(R/W)C: the stack is $R_{nfet}/(1/3\,\mu\mathrm{m})$ driving $5\,\mu\mathrm{m}\cdot C_g$Cg​, which is $15\,R_{nfet}C_g$15Rnfet​Cg​, and with $\tau_{inv} = 3R_{nfet}C_g$ that is $5\,\tau_{inv}$5τinv​. ✓

Answer: $\phi_1'$ must rise at least 500 ps after $\phi_1$ϕ1​.

Remember. Two dynamic stages with no inverter between them race. Delay the second stage’s evaluation by the first stage’s evaluate delay, or put an inverter in (domino).

The answer key differs

It says 556 ps: it rounds the stack’s $1/3\,\mu\mathrm{m}$ to $0.3\,\mu\mathrm{m}$ ($5/0.9 = 5.56$5/0.9=5.56); its own method gives $5/(1/3 + 2/3) = 5$5, 500 ps.

FN17-2b. The collision (10 points).

Hint

When the second stage starts to precharge, what are $Y_1$ and $Y_2$Y2​, whatever the inputs were?

What it asks. How the falling edge of $\phi_1'$ (the second stage’s precharge) must be placed against the falling edge of $\phi_1$ (the first stage’s) so that the second stage never collides. “Collision” names the hazard, and the second stage’s missing footer is what makes it possible.

The idea. A footless stage collides when its precharge PFET is on while its pull-down conducts: current flows straight from $V_{DD}$ to ground (Chapter 11, Section 4). So it is safe only if its inputs are 0 whenever it precharges. Lecture 12’s delayed reset gets that by letting the second stage precharge a little later, once the first stage’s output has fallen to 0 (Chapter 12, Section 7). That works for domino, where the input comes from an inverter that falls to 0 at precharge. Here the inputs are bare dynamic nodes, which go to 1 at precharge: the rule does the opposite of what it is for. The tempting answer, the key’s, applies it anyway.

FN17-2b: the collision

1. When the second stage collides. Its precharge PFET is on ($\phi_1' = 0$ϕ1′​=0) while one of its NFETs is on ($Y_1$Y1​ or $Y_2 = 1$1).
2. What $Y_1$ and $Y_2$ are. $Y_1$ is 1 whenever $AB = 0$ during evaluation, and always once the first stage precharges ($\phi_1 = 0$ϕ1​=0); $Y_2$ likewise with C and D.
3. Try both orders. If $\phi_1'$ falls before $\phi_1$ϕ1​, the second stage collides in every cycle in which $AB = 0$ or $CD = 0$0. If it falls after, $Y_1$ and $Y_2$ have been precharged to 1 by then and the collision is certain.
4. Why delayed reset fails here. It works only because a domino inverter’s output falls to 0 when its stage precharges. A bare dynamic node rises to 1.
5. So no timing avoids it; change the circuit. The circuit needs a footer on $\phi_1'$ in the second stage; or inverters after the NANDs, and then delayed reset (which changes the function).

Check. Count the safe cases when $\phi_1'$ falls first: the NOR’s pull-down is off only when $Y_1 = Y_2 = 0$0, that is $AB = CD = 1$1, one input row in 16. Every other row collides, so no choice of the falling edges can be “safe”.

Answer: with bare dynamic nodes driving a footless stage, no timing of the falling edges avoids the collision; delaying $\phi_1'$‘s fall makes it certain. Add a footer to the second stage.

Remember. Delayed reset needs inputs that fall to 0 when their stage precharges, as domino outputs do. A stage fed by bare dynamic nodes needs its footer.

The answer key differs

It says $\phi_1'$ must fall after $\phi_1$ by the first stage’s precharge time, $5/1.5\,\tau_{inv} = 333\,\mathrm{ps}$333ps. The number is the precharge time (a 1 µm PFET driving 5 µm), but the rule is delayed reset, which assumes inverters between the stages; here it guarantees that both NFETs are on when the precharge PFET turns on.

FN17-2c. Function and delay (5 points).

Hint

Does A rising turn a second-stage NFET on or off?

What it asks. The logic function at Y with the clocks of (a) and (b), and the delay from A rising to Y falling. As in MT24-5b, the named edge pair has to be tested before it is timed.

The idea. Read each node in evaluate: an n node is the complement of its network’s function, so the NANDs give $Y_1 = \overline{AB}$ and $Y_2 = \overline{CD}$CD, and the second stage’s two parallel NFETs make a NOR of them (Chapter 11, Section 4). Then follow the edges: an n node can only fall, so $Y_1$ can only fall, and a falling input can only turn an NFET off. The second stage’s own delay is $g h\,\tau_{inv}$ghτinv​, with a single 5 µm NFET (no footer) as its stack.

FN17-2c: function and delay

1. The function. In evaluation $Y_1 = \overline{AB}$AB, $Y_2 = \overline{CD}$ and $Y = \overline{Y_1 + Y_2} = AB \cdot CD = ABCD$ABCD.
2. The edge test. A rising (with B = 1) makes $Y_1$ fall, which turns one second-stage NFET off: it can never make Y fall. Y falls only when $\phi_1'$ rises while $Y_1$ or $Y_2$ is still 1.
3. The second stage’s delay. One 5 µm NFET, footless: its 2:1 reference has input 15 µm, so $g = 5/15 = 1/3$1/3; Y is $50/2 = 25\,\mu\mathrm{m}$25μm: $h = 5$5; $1.67\,\tau_{inv} = 167\,\mathrm{ps}$167ps.
4. Put the two stages together. From $\phi_1$ rising: the first stage settles in 500 ps, $\phi_1'$ rises then, and a falling Y is done 167 ps later, 667 ps in all. From A rising (B = 1): $Y_1$ falls in 500 ps, and Y stays at 1 if $CD = 1$1.

Check. The second stage by $(R/W)C$(R/W)C: $R_{nfet}/5\,\mu\mathrm{m}$ driving $25\,\mu\mathrm{m}\cdot C_g$ is $5\,R_{nfet}C_g = 1.67 \times 3R_{nfet}C_g$3Rnfet​Cg​. ✓ And the function agrees with (b): Y stays high only in the one row of 16 with $AB = CD = 1$1.

Answer: $Y = ABCD$ABCD. A rising cannot make Y fall; Y’s falling evaluation takes 167 ps after $\phi_1'$ rises, 667 ps after $\phi_1$ rises.

Remember. Before timing an edge pair, check that the circuit can make it: a falling n node only turns NFETs off. In a dynamic circuit, the clock often starts the edge, not the input.

The answer key differs

It gives $556 + 167 = 723\,\mathrm{ps}$ “from A rising to Y falling”: the same two stage delays (with its 556 ps for 500), on an edge pair that this circuit cannot produce.

Patterns

Dynamic and domino logic (MT17: 5% of the points; MT23: 21%; MT24: 25%).

• Asked every time: the function (8–15 points), a delay along one path (8–15 points), then resizing (MT24, 20 points) or noise and a half latch (MT23, 14 points). The approach section has the moves and why they work.
• Moves: n or p and the evaluate phase; the node as $\overline f$ (n) or $f$ (p); the one edge each stage makes; the stack from the rail (footer or header in, precharge device out); then $\sum g h$ or $(R/W)C$(R/W)C.
• Recurring results: an XOR or a full adder; $g = k/2$ at equal strengths, $k/3$ (n) and $2k/3$ (p) with $R_{pfet} = 2R_{nfet}$2Rnfet​; after a p node, $NM_L$ shrinks and the half latch is an NFET to ground.
• Traps: an impossible edge (MT24-5b, FN17-2c); a “precharged” node dropping series devices (MT23-3b); the strength convention (MT17-3c); $NM_H$ for $NM_L$ (MT23-3c); a fixed $F$ beside a fixed branch (MT24-5c); delayed reset without inverters (FN17-2b).
• Time: MT24-5 is about 19 minutes (22.5 seconds a point on a 200-point exam), MT23-3 about 16 (30 seconds a point at 150), MT17-3c about 4.

What the keys get wrong

Re-solving every part found these disagreements; all are recorded in this page’s review/decisions.md.

Part	The key	Here
MT24-5b	$g_3 = 2$ (Sum’s pull-down), 12.875 ns	a falling A makes Sum rise, through W6: $g_3 = 1$1, $132.5\,\tau_{inv} = 6.63$ ns
MT24-5c	$F = 3375$ held fixed, $f = 15$15, 2.25 ns ($W_4 = 6.7$W4​=6.7, $W_7 = 64.6\,\mu\mathrm{m}$64.6μm)	the widths move the branch and $g_3$g3​; its widths give 1.53 ns on the falling edge (best about 1.40 ns); on the rising edge $W_7$ is only load (best 6.58 ns)
MT23-3b	one PFET in stage 1, 10.35 “ns”	M1, M6 and M9 in series: 35 ps (24.2 ps with 0.69)
MT23-3c	“with a smaller $NM_H$NMH​”	$NM_L$ (its first sentence is right)
FN12-8a	gains sum to 50.76, 1.22 ns	50.17, 1.20 ns
FN12-8b	product 128.94, $f = 3.37$3.37, 323 ps	115.7, $f = 3.28$3.28, 315 ps
FN17-2a	556 ps (1/3 µm rounded to 0.3)	500 ps
FN17-2b	$\phi_1'$ falls 333 ps after $\phi_1$	no timing avoids the collision without inverters; that one makes it certain
FN17-2c	723 ps from A rising to Y falling	A rising cannot make Y fall; Y evaluates 167 ps after $\phi_1'$ rises (667 ps after $\phi_1$ϕ1​)

Every other part (MT24-5a, MT23-3a, MT23-3d, MT17-3c) agrees with its key after re-solving.