F2. Past finals: inverters, chains and low-voltage operation

The past finals ask the midterm’s inverter questions again, with one new twist: the inverter run below threshold. This page re-solves every final-exam part on inverters and inverter chains that uses midterm material: an inverter at 0.2 V (its off-current, its $I_{on}/I_{off}$Ion​/Ioff​, its delay and its power), and chains of inverting stages (their delay, their energy per transition and the width that minimizes the delay).

Exam	Parts on this page	Answer source
Fall 2019 (FN19)	1a–d, 3a–d	an unfilled exam: no key
Fall 2017 (FN17)	10a–b	the revised key
Fall 2010 (FN10)	2a–b, 4a–b	the key

Every number below is re-solved here; none is copied from a key. FN19 has no key, so its solutions are this guide’s own. Where a key disagrees, the folded note on the key at the end of the part explains why, and the table at the end lists them.

Left out. FN17-10c (the supply that minimizes the chain’s energy) and FN10-2c (the lowest supply that still gives a 10–90% swing) need low-voltage and minimum-energy operation, which the course does not teach before the midterm. The other questions on these exams (latches and clocking, wires, power grids, test, memory, datapath blocks, PLAs) are later material. The device questions of the same finals are on F1, path sizing on F3, and pass-transistor and dynamic logic on F4.

After this page you can:

1. find an off-current from a current at threshold and the subthreshold slope, and an $I_{on}/I_{off}$ ratio above and below threshold;
2. estimate a low-voltage inverter’s delay with the constant-current 50% formula, and its average power from switching and leakage;
3. write a subthreshold chain’s delay as a function of $V_{DD}$VDD​;
4. turn a gate with stacked devices into a gain, and get a chain’s delay and energy per transition with a symbolic side load;
5. say why “the width that minimizes delay” has no finite answer when the load is fixed, and what happens when there is no fixed load.

Before you start

How to use this page. Each section restates one exam question with its source page (FN19-1c, p3 is Fall 2019, question 1c, physical PDF page 3) and its points, and shows the exam’s own figure. The inverter below threshold is new on the finals, so it opens with a How to approach section: how to recognize the question, the moves in order, why the formulas apply, and the traps. The chains are the midterm’s inverter-chain family, which M3’s approach section teaches; their parts say what is new. Every part is worked the same way: what it asks, the idea behind the method, the solution in steps (each step gives its reason first), a check on the result, the answer, and one thing to remember. Try each part on your own first; open the Hint if you are stuck, and step through the solution before you press “Show all”. Where there is a key, its verdict is folded at the end of the part. The chapters teach each method in full, and every solution links the section.

Family	Questions (newest first)	Chapters	Midterm twin
An inverter below threshold	FN19-1, FN17-10, FN10-2	4, 5, 6	the off-current of MT23-1b and MT24-2b (M3)
Chains: delay, energy, best width	FN19-3, FN10-4	6, 7	MT24-2, MT21-4, MT17-4 (M3)

Conventions the exams use

State these at the top of your answer.

• Currents per device. FN19-1, FN17-10 and FN10-2 give currents per transistor, not per µm, and the same numbers for the NFET and the PFET, so rise and fall are alike.
• Subthreshold current falls tenfold for every $S$ volts of gate voltage below threshold (Chapter 4, Section 11). The finals say “ignore DIBL”, so it does not depend on $V_{DS}$VDS​.
• Delay at constant current. With a constant current $I$I, the output reaches 50% after $t_p \approx C_LV_{DD}/(2I)$ added (Chapter 6, Section 10), Chapter 5’s $t = CV/I$ (Section 11) taken to the 50% point. The full swing takes twice as long.
• Delay in τ. FN19-3 and FN10-4 give the fan-out-of-one delay $\tau_1$ and $k_{gate}$ in fF/µm. Both size the PFETs 2W against W NFETs, so $R_{pfet} = 2R_{nfet}$2Rnfet​, the inverter’s input is $3W\,k_{gate}$ and $\tau_1 = 3R_{nfet}k_{gate}$ (Chapter 7, Section 7). A stage’s delay is its gain $g\cdot h$ times $\tau_1$τ1​; no 0.69 factor; drain capacitance is ignored.
• Energy per transition. One input edge through a chain: half the nodes rise and half fall. The rising nodes draw $CV_{DD}^2$ each from the supply; counted as dissipation instead, every switching node burns $\tfrac12 CV_{DD}^2$21​CVDD2​. Both counts give the same total (Chapter 6, “Energy in a chain of gates”). A square wave’s cycle charges every node once.

How to approach a subthreshold-inverter question

Recognize it by a supply below the threshold (“let $V_{DD} = 0.2$ V”, “this will be subthreshold operation”), by the words “$I_{on}/I_{off}$Ion​/Ioff​”, “subthreshold slope” and “ignore DIBL”, and by a single inverter or a chain of identical ones with a load in fF. The parts come in the same order on every final: the off-current, the on/off ratio, the delay into a load, and sometimes the power or the chain’s delay as a function of $V_{DD}$VDD​. The family carried 40 points of FN19 (FN19-1), about 16 of FN17 (FN17-10a–b) and 15 of FN10 (FN10-2a–b).

The moves, in order.

1. Compare $V_{DD}$ with $V_T$VT​. It decides which current law the “on” device obeys: above threshold the question’s law, below it the subthreshold line. The “off” device ($V_{GS} = 0$VGS​=0) is always on the subthreshold line.
2. The off-current from the calibration point, in decades. If the question gives the current at $V_T$VT​, count the decades of $S$ from $V_T$ down to $V_{GS} = 0$ and divide the current by ten for each. If it gives $I_{off}$ itself (the current at $V_{GS} = 0$0), you already have it.
3. The on-current. Above threshold, from the question’s law; below it, from the same subthreshold line at $V_{GS} = V_{DD}$VDD​. Below threshold the ratio is simply $I_{on}/I_{off} = 10^{V_{DD}/S}$10VDD​/S.
4. The delay at constant current. The switching device carries $I_{on}$ into the load until the output crosses 50%: $t_p \approx C_LV_{DD}/(2I_{on})$CL​VDD​/(2Ion​). A chain of identical stages takes $N$ times that.
5. The power. Switching, $C_LV_{DD}^2f$ at the switching frequency $f$f, plus leakage, $V_{DD}I_{off}$VDD​Ioff​. First check that the output finishes its swing within half a period, because the switching count assumes it does.

Why these formulas.

• The subthreshold line. Below threshold the current is set by carriers crossing a barrier with their thermal energy, so it falls exponentially as the gate drops: one decade for every $S$ millivolts below $V_T$VT​: $I = I(V_T)\cdot 10^{-(V_T - V_{GS})/S}$ for $V_{GS} < V_T$ (Chapter 4, Section 11). With DIBL ignored the drain voltage doesn’t enter, so lowering $V_{DD}$ doesn’t change $I_{off}$Ioff​. Divide the on state by the off state and $I(V_T)$ and $V_T$ cancel: $I_{on}/I_{off} = 10^{V_{DD}/S}$10VDD​/S.
• The above-threshold law. FN19-1 gives $I_D = WC_{ox}v_{sat}(V_{GS} - V_T)$VT​), the fully velocity-saturated current of Chapter 4, Section 7. It holds only above $V_T$ and with the drain saturated.
• Delay as charge over current. A node of capacitance $C_L$ holds $C_LV_{DD}$CL​VDD​; a constant current $I$ moves half of it, enough to cross the 50% point that defines delay, in $C_LV_{DD}/(2I)$ added (Chapter 6, Section 10). Below threshold the current depends only on $V_{GS}$VGS​, which stays at $V_{DD}$ once the input has switched, so a constant current is a fair estimate.
• Power. Each rise of the output draws $C_LV_{DD}^2$ from the supply (Chapter 6, Section 6), once per period, so the switching power is that energy times the frequency $f$f. The off device leaks $I_{off}$ with $V_{DD}$ across it all the time, so the leakage power is $V_{DD}I_{off}$ (Chapter 4, Section 11; M3’s MT24-2b).

Decisions to make on the way. Per device or per µm (these finals give currents per device). The delay to 50% or the full swing (the course measures 50% to 50%; say which you use). Which load each stage drives (in FN17-10 the end load is one more inverter).

Traps. The above-threshold law below threshold: it gives a negative current. The factor of 2 between the 50% delay and the full swing (FN17-10b’s key). Expecting the two current laws to meet at $V_T$VT​: they are separate fits added. A lower $V_{DD}$ changing $I_{off}$ (not with DIBL ignored). Counting the switching energy when the output can’t finish its swing.

1. FN19-1: a low-voltage inverter

FN19-1, p2 (source figure).

FN19-1, p2 (Fall 2019, 40 points). An inverter with supply $V_{DD}$VDD​; logic swings between ground and $V_{DD}$VDD​. $V_T = 0.32$ V for the NFET and $-0.32$ V for the PFET. Above threshold, $I_D = WC_{ox}v_{sat}(V_{GS} - V_T)$ with $WC_{ox}v_{sat} = 1$ mA/V for the NFET, and $I_D = WC_{ox}v_{sat}(V_{SG} + V_T)$ with 1 mA/V for the PFET. $I_{off}$ is the current at $V_{GS} = 0$ ($V_{SG} = 0$VSG​=0) with $V_{DS} = V_{DD}$ ($V_{SD} = V_{DD}$VSD​=VDD​); $I_{on}$ is the current at $V_{GS} = V_{DD}$ ($V_{SG} = V_{DD}$VSG​=VDD​) with $V_{DS} = V_{DD}$VDD​.

The two devices are mirror images: the same $|V_T|$∣VT​∣, the same 1 mA/V, and (in part a) the same subthreshold calibration. Every answer holds for both.

FN19-1a: off-current and the on/off ratio at 1.2 V

FN19-1a, p2 (10 points). Let $V_{DD} = 1.2$ V. If the current of the NFET (PFET) is 100 µA at $V_{DS}$ ($V_{SD}$VSD​) of $V_{DD}$ and $V_{GS}$ ($V_{SG}$VSG​) of 0.32 V, what is the off-current? Assume a subthreshold slope of 90 mV/decade and ignore DIBL. What is the $I_{on}/I_{off}$ ratio for each transistor?

Hint

The 100 µA is a point at the threshold. How far below that point is the gate of an off transistor, measured in decades?

What it asks. Two currents of one transistor and their ratio. The off-current is the leak of a transistor whose gate is at 0 V; the on-current is the current with the gate at the full 1.2 V. The phrase “at $V_{GS}$ of 0.32 V” decides the method: the 100 µA is a calibration point on the subthreshold line, exactly at threshold.

The idea. The course uses one current law per region, so first place each state against $V_T$ (the approach). Off, $V_{GS} = 0$ is below threshold: the current lies on the subthreshold line, falling one decade for every $S$ millivolts below $V_T$ (Chapter 4, Section 11):

$$I = I(V_T)\cdot 10^{-(V_T - V_{GS})/S}.$$

On, $V_{GS} = 1.2$ V is well above threshold, and the question’s law applies: $I_D = WC_{ox}v_{sat}(V_{GS} - V_T)$VT​), the fully velocity-saturated current of Chapter 4, Section 7, valid with the drain saturated ($V_{DS} = V_{DD}$VDS​=VDD​). The off-current is the move of MT23-1b and MT24-2b (M3), for a whole device instead of a µm. added The two current models don’t meet at threshold: the above-threshold law gives 0 at $V_{GS} = V_T$VT​, the subthreshold calibration 100 µA. Each is a fit for its own region; use the one the question puts you in.

FN19-1a

1. Place each state. Because the law depends on the region: off, $V_{GS} = 0 < 0.32$ V, subthreshold; on, $V_{GS} = 1.2\,\mathrm{V} > 0.32$ V, above threshold.
2. Count the decades to the off state. Because the line falls one decade per 90 mV below $V_T$VT​, count from the calibration point down to $V_{GS} = 0$0, 320 mV at 90 mV per decade: $320/90 = 3.56$ decades, a factor of $10^{3.556} = 3594$3594.
3. The off-current. Because the current falls by that factor, divide the current at threshold by it: $I_{off} = 100\,\mu\mathrm{A}/3594 = 27.8\,\mathrm{nA}$27.8nA. The PFET is the mirror image, with $V_{SG}$VSG​, so it leaks the same.
4. The on-current. Because the on state is above threshold with $V_{DS} = V_{DD}$VDD​, the question’s law holds: $I_{on} = 1\,\mathrm{mA/V} \times (1.2 - 0.32)\,\mathrm{V} = 0.88\,\mathrm{mA}$0.88mA.
5. The ratio. With both currents known, divide: $I_{on}/I_{off} = 0.88\,\mathrm{mA}/27.8\,\mathrm{nA} = 3.16\times10^4$104.

Check. Count the ratio in decades instead. From the off state up to threshold is 3.56 decades; from threshold to the on state the current grows from 100 µA to 0.88 mA, a factor of 8.8, or $\log_{10} 8.8 = 0.94$ decades. Together $3.56 + 0.94 = 4.50$ decades, and $10^{4.50} = 3.16\times10^4$104. ✓

Answer: $I_{off} = 27.8$ nA and $I_{on}/I_{off} = 3.16\times10^4$104, for each transistor.

Remember. An off-current is the current at threshold divided by $10^{V_T/S}$10VT​/S: count the decades from $V_T$ down to 0. Place each state against $V_T$ before choosing a law.

FN19-1b: the on/off ratio at 0.2 V

FN19-1b, p3 (10 points). Now let $V_{DD} = 0.2$ V. What is the $I_{on}/I_{off}$ ratio for each transistor?

Hint

Where does a gate at 0.2 V sit against a 0.32 V threshold, and which current law does that leave for the “on” device?

What it asks. The same ratio with the supply lowered to 0.2 V. The “on” device now has $V_{GS} = 0.2$ V, and the “off” device still has $V_{GS} = 0$0, with only 0.2 V across it. The number that decides the method is 0.2 V: it is below the 0.32 V threshold.

The idea. Move 1 of the approach: compare $V_{DD}$ with $V_T$VT​. Here both states lie on the subthreshold line, so the ratio is just the decades between $V_{GS} = V_{DD}$ and $V_{GS} = 0$0. Write both currents with the line of (a) and divide: $I(V_T)$ and $V_T$ cancel, and $I_{on}/I_{off} = 10^{V_{DD}/S}$10VDD​/S. The tempting wrong method is the question’s above-threshold law: $1\,\mathrm{mA/V} \times (0.2 - 0.32)\,\mathrm{V} = -0.12$ mA, a negative current, which says the law doesn’t apply below $V_T$VT​.

FN19-1b

1. Place the on state. Because $V_{DD} = 0.2\,\mathrm{V} < V_T = 0.32$ V, even the “on” device is below threshold: it is on the subthreshold line, not on the above-threshold law.
2. The on-current. Because the on device is on the subthreshold line, count its decades below $V_T$VT​: 0.2 V is $320 - 200 = 120$ mV below, that is $120/90 = 1.33$ decades: $I_{on} = 100\,\mu\mathrm{A}/10^{1.333} = 4.64\,\mu\mathrm{A}$4.64μA.
3. The off-current. Because $I_{off}$ is set at $V_{GS} = 0$0, and with DIBL ignored the lower drain voltage doesn’t change it, it stays 27.8 nA from (a).
4. The ratio. With both currents on the same line, divide: $I_{on}/I_{off} = 4.64\,\mu\mathrm{A}/27.8\,\mathrm{nA} = 167$167.

Check. The shortcut gives it without $V_T$ or the 100 µA: $10^{V_{DD}/S} = 10^{0.2/0.09} = 10^{2.22} = 167$167. ✓

Answer: $I_{on}/I_{off} = 167$ for each transistor, against $3.16\times10^4$ at 1.2 V: below threshold the supply buys only one decade of on/off ratio per 90 mV.

Remember. Below threshold $I_{on}/I_{off} = 10^{V_{DD}/S}$10VDD​/S, whatever the threshold and the calibration: one decade per $S$ of supply.

FN19-1c: delay at 0.2 V

FN19-1c, p3 (10 points). If this inverter drives a load of 10 fF, estimate the delay of this inverter at $V_{DD} = 0.2$ V.

Hint

Which current moves the charge on the 10 fF, and how much of that charge has moved when the output crosses 50%?

What it asks. How long the inverter takes, at 0.2 V, to switch a 10 fF load: the delay from the input’s 50% point to the output’s. “Estimate” invites the simplest model: a constant current.

The idea. Delay is charge over current: Chapter 5’s $t = CV/I$ (Section 11). The course measures delay between the 50% points (Chapter 6, Section 10), so the switching device has to move only half the charge $C_LV_{DD}$CL​VDD​, and with a constant current $I$ that takes $t_p \approx C_LV_{DD}/(2I)$ added. A constant current is a fair estimate here: below threshold the course’s current depends only on $V_{GS}$ (DIBL is ignored), and $V_{GS}$ stays at $V_{DD}$ once the input has switched. The tempting slip is $C_LV_{DD}/I$CL​VDD​/I, the time for the full swing: twice the delay.

FN19-1c

1. The current that switches the load. Because the input switches fully, to 0.2 V or to 0, the switching device has $|V_{GS}| = 0.2$ V and carries $I_{on} = 4.64\,\mu\mathrm{A}$ from (b).
2. The current against it. Because the other device is off, it leaks 27.8 nA the other way: 0.6% of $I_{on}$Ion​, negligible.
3. The charge to move. Because the delay ends at the 50% point, the device must move half of $C_LV_{DD} = 10\,\mathrm{fF} \times 0.2\,\mathrm{V} = 2\,\mathrm{fC}$2fC: $t_p \approx \dfrac{C_LV_{DD}}{2I_{on}} = \dfrac{2\,\mathrm{fC}}{9.28\,\mu\mathrm{A}} = 215\,\mathrm{ps}$215ps.
4. Both edges. Because the two devices are mirror images with the same current, the rising and falling outputs take the same time.

Check. Units: a femtocoulomb at a microampere takes a nanosecond, so $2/9.28 = 0.215$ ns. ✓ And the size is plausible: the same estimate at 1.2 V (in the answer) is about 30 times faster, because the current there is about 190 times larger while the charge is only 6 times larger.

Answer: about 215 ps to the 50% point. The full swing, $C_LV_{DD}/I_{on}$CL​VDD​/Ion​, takes 431 ps. For comparison, at 1.2 V the same estimate gives $10\,\mathrm{fF} \times 1.2\,\mathrm{V}/(2 \times 0.88\,\mathrm{mA}) = 6.8$ ps: dropping the supply below threshold costs a factor of about 30 in speed.

Remember. At constant current the delay to 50% is $C_LV_{DD}/(2I)$CL​VDD​/(2I); the full swing takes twice as long. Below threshold $I$ is tiny, so the delay is long.

FN19-1d: average power at 1 GHz

FN19-1d, p4 (10 points). If the inverter (with $V_{DD} = 0.2$ V) is stimulated with a 50%-duty-cycle square wave at its input switching between 0 and 0.2 V with a period of 1 ns, what is the average power consumed by this inverter?

Hint

Which kinds of energy does the inverter spend in one period, and does its output have time to reach the rail in each half?

What it asks. The inverter’s average power when a 1 ns square wave drives it at 0.2 V: the energy it uses in one period, divided by the period. “50% duty cycle” means each output swing has half the period, 500 ps.

The idea. A static inverter spends power in three ways. Switching: each rise of the output draws $C_LV_{DD}^2$ from the supply (Chapter 6, Section 6), once per period, so $P = C_LV_{DD}^2f$CL​VDD2​f. Crowbar: current straight through both devices while a slow input edge holds both on (Chapter 6, Section 7). Leakage: the off device, with $V_{DD}$ across it, leaks $I_{off}$ all the time, $P = V_{DD}I_{off}$VDD​Ioff​. Below threshold one new question comes first: the $C_LV_{DD}^2$ count assumes the output reaches the rail, and at these currents the swing is slow. Keep the 10 fF load of (c): the question names “the inverter” of the previous part.

FN19-1d

1. Does the swing finish? Because the switching count assumes a full swing, compare its time with the 500 ps available: the full swing takes $C_LV_{DD}/I_{on} = 431$ ps (c), so it just finishes. Assume a full swing.
2. Switching. Because the output rises once per period, it draws $C_LV_{DD}^2 = 10\,\mathrm{fF} \times 0.04\,\mathrm{V^2} = 0.4\,\mathrm{fJ}$ per period. At $f = 1/(1\,\mathrm{ns}) = 1$ GHz: $P_{switch} = C_LV_{DD}^2f = 0.400\,\mu\mathrm{W}$0.400μW.
3. Crowbar. Because a square wave has instant edges, the two devices are never on together: none.
4. Leakage. Because in either state one device is off with $V_{DD}$ across it: $P_{leak} = V_{DD}I_{off} = 0.2\,\mathrm{V} \times 27.8\,\mathrm{nA} = 5.57\,\mathrm{nW}$5.57nW.
5. Add them. Because the three parts draw energy independently, the average power is their sum: $0.400\,\mu\mathrm{W} + 0.0056\,\mu\mathrm{W} = 0.406\,\mu\mathrm{W}$0.406μW; leakage is 1.4% of it.

Check. Count energy per period instead: 0.4 fJ of switching, plus $5.57\,\mathrm{nW} \times 1\,\mathrm{ns} = 0.0056$ fJ of leakage. A femtojoule per nanosecond is a microwatt, so the average is $0.406\,\mu\mathrm{W}$0.406μW. ✓

Answer: about 0.41 µW (0.400 µW switching plus 5.6 nW leakage). The full-swing assumption is tight: with a period shorter than about 0.86 ns (twice the 431 ps swing) the output would no longer reach the rails in this estimate, and the switching energy per cycle would shrink.

Remember. Average power = $C_LV_{DD}^2f$ + $V_{DD}I_{off}$ (+ crowbar for slow edges). Below threshold, first check that the output finishes its swing in half a period.

Check yourself For FN19-1’s devices, at what supply below threshold is I_on/I_off = 1000, and what is the 10 fF delay there?

Three decades at 90 mV/decade: $V_{DD} = 0.27$ V, still below $V_T = 0.32$ V. Then $I_{on} = 1000 \times 27.8\,\mathrm{nA} = 27.8\,\mu\mathrm{A}$27.8μA, and $t_p = 10\,\mathrm{fF} \times 0.27\,\mathrm{V}/(2 \times 27.8\,\mu\mathrm{A}) = 48.5$ ps. Another 70 mV of supply makes the inverter 4.4 times faster than at 0.2 V.

2. FN17-10: a subthreshold inverter chain

FN17-10, p21 (Fall 2017; the point values are overwritten and appear to be 8 per part). A chain of eight identical 10 µm/5 µm inverters, loaded at the end by 30 fF. “We are going to calculate the supply voltage at which this inverter chain will consume minimum energy. This will be subthreshold operation.” The gate capacitance is 2 fF/µm.

There is no figure. Each inverter’s input is $(10 + 5)\,\mu\mathrm{m} \times 2\,\mathrm{fF/\mu m} = 30\,\mathrm{fF}$30fF, so the 30 fF at the end is one more inverter: every stage drives 30 fF, and the eight stages are identical. Part (c), the supply for minimum energy, is left out (see the top of the page).

FN17-10a: the on-current against the supply

FN17-10a, p21. Assume the $I_{off}$ of each transistor is 10 nA. If the subthreshold slope is 80 mV/decade, what is the on-current of the devices of the inverter as a function of $V_{DD}$VDD​?

Hint

You know the current at $V_{GS} = 0$0. What happens to it, decade by decade, as the gate rises to $V_{DD}$VDD​?

What it asks. The on-current as a formula in $V_{DD}$VDD​, given the off-current (10 nA) and the slope (80 mV/decade). “This will be subthreshold operation” decides the law: the supply stays below threshold, so the on device is on the subthreshold line too.

The idea. The same subthreshold line as FN19-1, but calibrated at $V_{GS} = 0$ instead of at $V_T$VT​. Raising the gate from 0 to $V_{DD}$ climbs $V_{DD}/S$ decades, so $I_{on} = I_{off}\cdot10^{V_{DD}/S}$ (Chapter 4, Section 11). It needs no threshold, which is as well: the exam gives none. It holds only while $V_{DD}$ stays below $V_T$VT​.

FN17-10a

1. The calibration point. Because $I_{off}$ is defined at $V_{GS} = 0$0, it is the foot of the line: 10 nA at 0 V.
2. The climb. Because the on device has $V_{GS} = V_{DD}$VDD​, and the line rises one decade for every 80 mV, the current grows by $10^{V_{DD}/0.08\,\mathrm{V}}$10VDD​/0.08V.
3. The formula. Because the line starts at $I_{off}$ and gains $V_{DD}/S$ decades, multiply: $I_{on} = I_{off}\,10^{V_{DD}/S} = 10\,\mathrm{nA} \times 10^{V_{DD}/0.08\,\mathrm{V}}$10VDD​/0.08V, for both devices, which have the same numbers.

Check. At $V_{DD} = 0$ the formula gives back $I_{off} = 10$ nA, as it must. ✓ At 0.2 V it climbs $200/80 = 2.5$ decades to 3.16 µA, the same as FN10-2a, which shares the calibration and the slope.

Answer: $I_{on} = 10\,\mathrm{nA} \times 10^{V_{DD}/(0.08\,\mathrm{V})}$10VDD​/(0.08V); for example 3.16 µA at 0.2 V.

Remember. Below threshold, $I_{on} = I_{off}\cdot10^{V_{DD}/S}$10VDD​/S: a current calibrated at $V_{GS} = 0$ needs no $V_T$VT​.

The answer key agrees

FN17-10b: the chain’s delay against the supply

FN17-10b, p21. Estimate the delay of the inverter chain (as a function of $V_{DD}$VDD​).

Hint

What does each stage drive, and with what current? Then how do eight identical stages add?

What it asks. The delay of all eight stages, as a formula in $V_{DD}$VDD​. Both the charge to move ($C\cdot V_{DD}$C⋅VDD​) and the current ($I_{on}$Ion​ of (a)) depend on the supply, so both stay in the formula.

The idea. Each stage is FN19-1c’s constant-current estimate: it moves half the charge on its 30 fF load at the current $I_{on}$Ion​, so $t_p \approx CV_{DD}/(2I_{on})$ to the 50% point added (FN19-1c; Chapter 6, Section 10). The stages are identical and switch one after another, so the chain takes eight times as long. The full swing, $CV_{DD}/I_{on}$CVDD​/Ion​, would be twice as long; the course measures delay to 50%, and on an exam you say which you use.

FN17-10b

1. The load and the current per stage. Because every stage drives one 30 fF input (above) and both devices carry $I_{on}$ from (a), every stage, rising or falling, sees the same 30 fF and the same current.
2. One stage, to 50%. Because the delay ends when half the charge has moved: $t_p = \dfrac{30\,\mathrm{fF}\cdot V_{DD}}{2 \times 10\,\mathrm{nA} \times 10^{V_{DD}/0.08}}$2×10nA×10VDD​/0.0830fF⋅VDD​​.
3. Eight stages. Because the stages are identical and in series, their delays add: $t_{chain} = 8t_p = \dfrac{120\,\mathrm{fF}\cdot V_{DD}}{10\,\mathrm{nA} \times 10^{V_{DD}/0.08}}$10nA×10VDD​/0.08120fF⋅VDD​​.
4. Simplify. To read the formula, collect the constants: $120\,\mathrm{fF}/10\,\mathrm{nA} = 12\,\mu\mathrm{s/V}$12μs/V, so $t_{chain} = 12\,\mu\mathrm{s} \times \dfrac{V_{DD}}{1\,\mathrm{V}} \times 10^{-V_{DD}/0.08\,\mathrm{V}}$10−VDD​/0.08V.
5. Some values. To see the scale, put in three supplies: 67.5 ns at 0.1 V, 7.59 ns at 0.2 V, 640 ps at 0.3 V.

Check. The formula’s two parts should show up in the values. From 0.2 to 0.3 V the current grows by $10^{0.1/0.08} = 17.8$ and the charge by $0.3/0.2 = 1.5$1.5, so the delay should fall by $17.8/1.5 = 11.9$11.9; and $7.59\,\mathrm{ns}/640\,\mathrm{ps} = 11.9$11.9. ✓ Each 80 mV of supply makes the chain almost ten times faster, a little less because the charge grows too.

Answer: $t_{chain} = \dfrac{8 \times 30\,\mathrm{fF} \times V_{DD}}{2 \times 10\,\mathrm{nA} \times 10^{V_{DD}/0.08}} = 12\,\mu\mathrm{s} \times V_{DD}[\mathrm{V}] \times 10^{-V_{DD}/0.08}$10−VDD​/0.08, about 7.6 ns at 0.2 V.

Remember. A subthreshold chain’s delay goes as $V_{DD}\cdot10^{-V_{DD}/S}$10−VDD​/S: about one decade of speed per $S$ of supply.

The answer key differs

It takes each inverter as $(30\,\mathrm{fF})V_{DD}/I_{on}$(30fF)VDD​/Ion​, so the chain takes $8(30\,\mathrm{fF})V_{DD}/(10\,\mathrm{nA} \cdot 10^{V_{DD}/0.08})$10VDD​/0.08): twice the answer above. That is the time for a full swing at constant current, not the delay to the 50% point. Both are estimates, but the course measures delay from 50% to 50% (Chapter 6, Section 10), and the 2010 key uses $CV_{DD}/(2I_{on})$CVDD​/(2Ion​), “delay to 50% point”, in the same problem (FN10-2b). On an exam, say which you use.

3. FN10-2: an inverter at 0.2 V

FN10-2, p3 (source figure).

FN10-2, p3 (Fall 2010). An inverter with supply $V_{DD}$VDD​; logic swings between ground and $V_{DD}$VDD​. The key adds by hand: “(assume $V_T > 0.2$ V)”. $I_{off}$ and $I_{on}$ are defined as in FN19-1.

FN10-2a: the on/off ratio

FN10-2a, p3 (10 points). Let $V_{DD} = 0.2$ V. Assume that the $I_{off}$ of each transistor is 10 nA. If the subthreshold slope is 80 mV/decade, what is the $I_{on}/I_{off}$ ratio for each transistor?

Hint

With $V_T$ above 0.2 V, which current law holds for each state, and what does that leave of the calibration?

What it asks. The on/off ratio at 0.2 V, given the off-current and the slope. The key’s handwritten “$V_T > 0.2$VT​> V” decides the method: both states are below threshold.

The idea. This is FN19-1b’s shortcut. Both currents lie on the subthreshold line, one decade per $S$S, so their ratio is $10^{V_{DD}/S}$10VDD​/S, and neither $V_T$ nor the calibration current enters (the approach). The differences from FN19-1 are a smaller slope, 80 mV/decade, and a calibration at $V_{GS} = 0$0, as in FN17-10a; the shortcut needs neither the threshold nor the 10 nA.

FN10-2a

1. Place the on state. Because $V_T > 0.2$ V, the on device, at $V_{GS} = 0.2$ V, is below threshold too: both states are on the subthreshold line.
2. Count the decades. Because the line climbs one decade per 80 mV, between $V_{GS} = 0$ and $V_{GS} = 0.2$ V it climbs $200/80 = 2.5$ decades.
3. The ratio. Because each decade is a factor of ten, $I_{on}/I_{off} = 10^{2.5} = 316$316, for both devices, and so $I_{on} = 316 \times 10\,\mathrm{nA} = 3.16\,\mu\mathrm{A}$3.16μA.

Check. Compare with FN19-1b, at the same 0.2 V supply. A smaller slope packs more decades into the same voltage: 80 mV/decade gives $200/80 = 2.5$ decades where 90 mV/decade gave 2.22. So the ratio must be larger than FN19-1b’s 167, and 316 is. ✓

Answer: 316 for each transistor ($I_{on} = 3.16\,\mu\mathrm{A}$Ion​=3.16μA).

Remember. Below threshold the on/off ratio depends only on $V_{DD}/S$VDD​/S: divide the supply by the slope and raise ten to it.

The answer key agrees

FN10-2b: delay at 0.2 V

FN10-2b, p3 (5 points). If this inverter drives a load of 10 fF, estimate the delay of this inverter at $V_{DD} = 0.2$ V.

Hint

Which current drives the 10 fF, and how much of the load’s charge must move before the output crosses 50%?

What it asks. The delay of this inverter into 10 fF at 0.2 V: the same question as FN19-1c, with the devices of (a).

The idea. FN19-1c’s constant-current estimate: the switching device carries $I_{on}$ and must move half of $C_LV_{DD}$ to cross the 50% point, so $t_p \approx C_LV_{DD}/(2I_{on})$ added (Chapter 6, Section 10). Only the current differs from FN19-1c: (a) gives 3.16 µA where FN19-1 had 4.64 µA.

FN10-2b

1. The current. Because the switching device has $|V_{GS}| = V_{DD}$VDD​, it carries $I_{on} = 316 \times 10\,\mathrm{nA} = 3.16\,\mu\mathrm{A}$ from (a); the off device’s 10 nA against it is 0.3% of that, negligible.
2. The delay to 50%. Because the delay ends when half the charge has moved: $t_p \approx \dfrac{C_LV_{DD}}{2I_{on}} = \dfrac{10\,\mathrm{fF} \times 0.2\,\mathrm{V}}{2 \times 3.16\,\mu\mathrm{A}} = 316\,\mathrm{ps}$316ps.

Check. Same load, same supply as FN19-1c, so the delays should be in the inverse ratio of the currents: $4.64/3.16 = 1.47$1.47, and $215\,\mathrm{ps} \times 1.47 = 316$ ps. ✓

Answer: about 316 ps to the 50% point. FN19-1c is the same question with 90 mV/decade and a different calibration: 215 ps.

Remember. At a fixed load and supply, the delay is inversely proportional to the on-current: find $I_{on}$Ion​, and the rest is $C_LV_{DD}/(2I_{on})$CL​VDD​/(2Ion​).

The answer key agrees

It writes “delay to 50% point” beside the formula $C_LV_{DD}/(2I_{on})$CL​VDD​/(2Ion​).

Try it

Pick an exam’s device and move the supply. The solid curve is the delay to 50% (for FN17-10, the whole eight-stage chain); the dashed curve is one full swing; for FN19-1 the dotted line is the half period of the 1 GHz square wave of part (d). The supply slider stops at the threshold: 0.32 V for FN19-1, the key’s “$V_T > 0.2$VT​> V” for FN10-2, and an assumed 0.3 V for FN17-10, which gives no threshold.

FN19-1: 100 µA at V_T = 0.32 V, 90 mV/decadeFN17-10: eight stages, 10 nA, 80 mV/decadeFN10-2: 10 nA, 80 mV/decade

supply V_DD (below V_T)

0.200 V

load per stage C

10 fF

I_off (V_GS = 0)

27.8 nA

I_on (V_GS = V_DD, subthreshold)

4.64 µA

I_on/I_off = 10^V_DD/S

166.8

delay to 50%, C·V_DD/(2I_on)

215 ps

full swing, C·V_DD/I_on

431 ps

switching power C·V_DD²·f

0.400 µW

leakage power V_DD·I_off

5.57 nW

average power

0.406 µW (1.4% leakage)

swing done within half a period?

yes (constant-current estimate)

Below threshold the on-current grows tenfold for every 90 mV of supply, while the charge to move grows only in proportion to V_DD: the delay falls almost a decade per 90 mV. The off-current does not depend on V_DD here (DIBL and the drain-voltage factor of the subthreshold current are ignored). Delays are the constant-current estimates of Chapter 6; no 0.69 factor, no drain capacitance.

What to notice.

• The delay curve is almost a straight line on the log scale: one decade per 80 or 90 mV of supply, the subthreshold slope read sideways.
• FN19-1 at 0.2 V: the full-swing curve sits just below the half-period line, so the output finishes its swing in time (part d). Lower the supply below about 0.19 V and it no longer does.
• $I_{on}/I_{off}$ depends only on $V_{DD}/S$VDD​/S: compare FN10-2 and FN17-10, which share the slope but not the load.

4. FN19-3: a four-bit ripple-carry chain

FN19-3, p7 (source figure, with the PDF’s overlaid C_out label).

FN19-3, p7 (Fall 2019, 39 points). The carry chain of a four-bit static ripple-carry adder. $C_{load}$ models the loading of the sum circuit at each bit. Transistors provide $k_{gate} = 1$ fF/µm of loading. The fan-out-of-one (FO1) delay is $\tau_1 = 25$ ps.

Reading the circuit. Every part needs to know what one stage is, so read it once, device by device.

Reading FN19-3 device by device

1. The fixed inputs. In every bit the other two gates are tied to 1 and 0, so the bit propagates its carry. A PFET conducts when its gate is low, so in the pull-up the PFET with gate 0 is on and the one with gate 1 is off. An NFET conducts when its gate is high, so in the pull-down the NFET with gate 1 is on and the one with gate 0 is off.
2. What is left on each side. With the off devices gone, each side is the carry input’s device in series with one on device. Pull-up: the on 2W PFET in series with the carry input’s 2W PFET. Pull-down: the carry input’s W NFET in series with the on W NFET. So each stage is an inverter of its carry input with two devices in series on each side.
3. The polarity. Because each stage inverts, the carry alternates polarity along the chain, and four inversions bring $C_{out}$ back to $C_{in}$‘s polarity.
4. The node inside each stack. The node between a stack’s two devices is tied to its rail through the on device, so it stays there and does not switch: it adds no delay and no switching energy.
5. The load on each output. Each output drives the next stage’s carry pin, one 2W PFET and one W NFET, $3W\,k_{gate}$3Wkgate​, plus the sum circuit’s $C_{load}$Cload​. The last output’s $3W\,k_{gate}$ stands for the next bit, so all four nodes are alike.

Conventions. The 2W/W sizing says $R_{pfet} = 2R_{nfet}$ (the exam doesn’t state it). Then $\tau_1 = 3R_{nfet}k_{gate}$3Rnfet​kgate​, so $R_{nfet} = 25\,\mathrm{ps}/(3 \times 1\,\mathrm{fF/\mu m}) = 8.33\,\mathrm{k\Omega\cdot\mu m}$8.33kΩ⋅μm. Drain capacitance is ignored. $C_{load}$ has no value in the exam, so the answers keep it.

FN19-3a: delay with W = 1 µm

FN19-3a, p7 (10 points). If $W = 1\,\mu\mathrm{m}$1μm, what is the delay of the carry chain from $C_{in}$ to $C_{out}$Cout​?

Hint

Each side of a stage is two devices in series. How strong is that, compared with an inverter whose input is the same size?

What it asks. The time for a carry to ripple from $C_{in}$ to $C_{out}$ through four stages, with $W = 1\,\mu$m. $C_{load}$ has no value, so the answer is a formula in it.

The idea. This is the midterm’s inverter chain; M3’s inverter-chain section teaches its moves: find the node’s capacitance first, read the strengths, then one stage is $(R/W)\,C_{node}$ and the chain is $N$ stages. The new point is the stack. Devices in series act like one device of width $1/\sum(1/W_i)$1/∑(1/Wi​), so two equal ones act like one of half the width (Chapter 7, “Two devices in series”). A carry stage therefore drives like an inverter half as strong as its input suggests: its logical effort is $g = 2$2, and each stage costs $2\tau_1$ even with no sum load. In gain form a stage takes $g\cdot h\cdot\tau_1$τ1​, with $h$ its load over its input (Chapter 7, Section 9). The convention decides $\tau_1$τ1​: with $R_{pfet} = 2R_{nfet}$2Rnfet​, $\tau_1 = 3R_{nfet}k_{gate}$3Rnfet​kgate​.

FN19-3a

1. The stack rule. Because two equal devices in series act like one of half the width, two W NFETs are one NFET of width W/2, resistance $2R_{nfet}/W$2Rnfet​/W. Two 2W PFETs are one PFET of width W: $R_{pfet}/W = 2R_{nfet}/W$2Rnfet​/W. Both edges see the same $2R_{nfet}/W$2Rnfet​/W.
2. A stage’s input. Because the carry pin drives one 2W PFET and one W NFET, it presents $3W\,k_{gate}$3Wkgate​, the same as a 2W/W inverter’s.
3. The node. Because each output drives the next carry pin and the sum circuit (the reading block): $C = 3W\,k_{gate} + C_{load}$Cload​.
4. One stage. Because a stage’s delay is its resistance times its node’s capacitance, with $R_{nfet}$ written through $\tau_1 = 3R_{nfet}k_{gate}$3Rnfet​kgate​: $\dfrac{2R_{nfet}}{W}\left(3Wk_{gate} + C_{load}\right) = 2\tau_1\left(1 + \dfrac{C_{load}}{3Wk_{gate}}\right)$2τ1​(1+3Wkgate​Cload​​).
5. The same as a gain. Because an inverter as strong as this stage (a W/2 NFET, a W PFET) has input $1.5W\,k_{gate}$1.5Wkgate​, $g = 3W/1.5W = 2$2, and $h = (3Wk_{gate} + C_{load})/(3Wk_{gate})$Cload​)/(3Wkgate​). The same $2h\,\tau_1$2hτ1​.
6. Four stages. Because the four identical stages switch one after another, their delays add: $t = 8\tau_1\left(1 + \dfrac{C_{load}}{3Wk_{gate}}\right)$8τ1​(1+3Wkgate​Cload​​). With $W = 1\,\mu\mathrm{m}$1μm, $3Wk_{gate} = 3$ fF: $t = 200\,\mathrm{ps}\left(1 + \dfrac{C_{load}}{3\,\mathrm{fF}}\right) = 200\,\mathrm{ps} + 66.7\,\mathrm{ps/fF} \times C_{load}$Cload​.

Check. The limiting case $C_{load} = 0$0: each stage drives one copy of itself and takes $2\tau_1 = 50$ ps, where a chain of plain inverters would take $\tau_1$ per stage, 100 ps for four. The series pairs double it, as step 1 said. And the slope’s units: $8R_{nfet}/W = 8 \times 8.33\,\mathrm{k\Omega} = 66.7\,\mathrm{k\Omega}$66.7kΩ, and kΩ × fF = ps. ✓

Answer: $t = 200\,\mathrm{ps} \times (1 + C_{load}/3\,\mathrm{fF})$Cload​/3fF); for example 400 ps if $C_{load} = 3$ fF. The trap is to treat each stage as a plain inverter: the series pair doubles the resistance, so each stage costs $2\tau_1$ even with no sum load.

Remember. A stack of two equal devices drives like one of half the width. A stage with a series pair on each side is an inverter with $g = 2$2: $2h\,\tau_1$ per stage.

FN19-3b: energy of one propagated transition

FN19-3b, p7 (10 points). If $V_{DD} = 1.2$ V and $W = 1\,\mu\mathrm{m}$1μm, what is the energy dissipated by a single propagated transition through the carry chain?

Hint

One edge at $C_{in}$ ripples through: how many of the four outputs rise, and what does each one carry?

What it asks. The energy of one carry edge rippling through all four stages, at 1.2 V and $W = 1\,\mu$m. “A single propagated transition” decides the count: one edge, not a full cycle.

The idea. M3’s energy move (MT24-2a): a rising node draws $CV_{DD}^2$ from the supply, half stored and half burnt in the pull-up, and a falling node burns its stored half in the pull-down (Chapter 6, Section 6). So count the rising nodes and charge each $C_{node}V_{DD}^2$Cnode​VDD2​. Per transition, half the nodes rise. What is new here: only the four outputs switch. The stack nodes stay at their rails (the reading block), and $C_{in}$ is charged by whatever drives the chain.

FN19-3b

1. One node. Because at $W = 1\,\mu$m the next carry pin is $3W\,k_{gate} = 3$ fF: $C = 3\,\mathrm{fF} + C_{load}$Cload​.
2. Which nodes switch. Because the carry propagates and each stage inverts, all four outputs switch, alternately: two rise and two fall.
3. Price them. Because a rising node draws $CV_{DD}^2$ from the supply and a falling one draws nothing, the energy drawn is that of the two rising nodes, $2CV_{DD}^2$2CVDD2​. Dissipated: each switching node burns $\tfrac12 CV_{DD}^2$21​CVDD2​, so $4 \times \tfrac12 CV_{DD}^2 = 2CV_{DD}^2$2CVDD2​. The same (Chapter 6, “Energy in a chain of gates”).
4. The numbers. Because the question fixes $V_{DD} = 1.2$ V, $V_{DD}^2 = 1.44\,\mathrm{V^2}$1.44V2: $E = 2(3\,\mathrm{fF} + C_{load}) \times 1.44\,\mathrm{V^2} = 8.64\,\mathrm{fJ} + 2.88\,\mathrm{fJ/fF} \times C_{load}$Cload​.

Check. Units: fF × V² = fJ. ✓ And the trap: per cycle (an edge and its return) every output would rise once, $4CV_{DD}^2$4CVDD2​, twice as much. The question says a single transition.

Answer: $E = 2(3\,\mathrm{fF} + C_{load})V_{DD}^2 = 8.64\,\mathrm{fJ} + 2.88\,C_{load}$ (fJ, with $C_{load}$ in fF). Not counted: the $C_{in}$ node, charged by whatever drives the chain (as FN10-4b says outright), and the stack nodes, which stay at their rails.

Remember. Per transition, half the switching nodes rise: $E = \tfrac N2 CV_{DD}^2$2N​CVDD2​. A node held at a rail by an on device doesn’t count.

FN19-3c: the width that minimizes the delay

FN19-3c, p8 (9 points). What value of W will minimize the delay of this carry chain? What energy will be dissipated at this value of W for a single transition through the chain?

Hint

Split one stage’s delay into the part that comes from the next stage and the part that comes from $C_{load}$Cload​. What does each do as $W$ grows?

What it asks. The width that makes the chain fastest, and the energy per transition at that width. As in MT24-2e, the points are for saying what kind of answer there is, and why.

The idea. The same argument as MT24-2e; what differs is that each stage costs $2\tau_1$ and the side load is a symbol. Split one stage of (a): $2\tau_1 + 2\tau_1\,C_{load}/(3Wk_{gate})$2τ1​Cload​/(3Wkgate​). The first part is the stage driving the next stage: a wider stage is stronger by $W$W, but its load is larger by $W$ too, so this part is fixed. The second part is a fixed load driven by an ever stronger device: it shrinks as $1/W$ and never turns around. Setting a derivative to zero finds nothing.

FN19-3c

1. Split the chain’s delay. To see which part depends on $W$W, write (a) as two terms: $t = 8\tau_1 + 8\tau_1\,\dfrac{C_{load}}{3Wk_{gate}}$8τ1​3Wkgate​Cload​​.
2. Which part depends on W. Because only the $C_{load}$ term does, and it shrinks as $W$ grows, the delay falls every time $W$ grows: there is no finite minimum.
3. The floor. Because as $W \to \infty$ the sum load becomes negligible next to the gates, each stage drives only a copy of itself ($h = 1$h=1), and $t \to 8\tau_1 = 200$ ps. It approaches this floor but never reaches it.
4. The energy. Because the gate part of every node grows with $W$W, the energy of (b), for any $W$W, is $E = 2(3Wk_{gate} + C_{load})V_{DD}^2 = (8.64W + 2.88C_{load})$ fJ. It grows in proportion to $W$W, without bound.
5. The returns diminish fast. To see what a wider $W$ buys, compare the delay with the energy at two widths. With $x = 3Wk_{gate}$3Wkgate​, the gates’ own load: at $x = C_{load}$ the delay is $2 \times 200 = 400$ ps; at $x = 9C_{load}$ it is 222 ps, for five times the energy. So “minimize the delay” alone is not a design goal here. added Energy × delay, $\propto (x + C_{load})^2/x$Cload​)2/x, is least where its growing part $x$ balances its shrinking part $C_{load}^2/x$Cload2​/x, at $x = C_{load}$Cload​, as in MT24-2d and MT17-4d.

Check. The other end: as $W \to 0$ the delay grows without bound, because ever weaker devices drive a fixed $C_{load}$Cload​. From there the delay only falls toward its 200 ps floor, so there is nothing in between to minimize.

Answer: no finite W: the delay keeps falling toward $8\tau_1 = 200$ ps as $W \to \infty$∞, while the energy per transition, $2(3Wk_{gate} + C_{load})V_{DD}^2$Cload​)VDD2​, grows without limit. This is MT24-2e’s “think carefully” answer (M3). added Outside the exam’s model, the stage driving $C_{in}$ would slow down as $W$ grows; the question leaves it out.

Remember. With a fixed side load and nothing else fixed, minimizing the delay has no finite answer: say so, give the floor ($N\cdot g\cdot\tau_1$N⋅τ1​), and name the cost, the energy, that grows without limit.

FN19-3d: no sum load

FN19-3d, p8 (10 points). Repeat the calculation of (c) if $C_{load} = 0$0.

Hint

With no sum load, what does each stage drive, compared with itself? What happens to its strength and its load as $W$ grows?

What it asks. The delay-minimizing width and its energy again, now with no sum circuit on the outputs.

The idea. This is MT17-4a’s “does it depend on W?”. With no fixed load, each stage drives only a copy of the next stage. A wider stage is stronger by $W$ and its load is larger by $W$W, and the two cancel, so the delay is the same for every width (Chapter 7, Section 7). The energy still grows with $W$W, so the energy decides the width.

FN19-3d

1. One stage. Because with $C_{load} = 0$ each node is only the next stage’s $3W\,k_{gate}$3Wkgate​: $\dfrac{2R_{nfet}}{W} \times 3Wk_{gate} = 2\tau_1$2τ1​, for any $W$W.
2. The chain. Because the four stages are alike and add, four such stages: $8\tau_1 = 200$ ps, whatever $W$W.
3. The energy. Because each node is now gate capacitance only, (b)‘s count gives $E = 2 \times 3Wk_{gate} \times V_{DD}^2 = 8.64\,W$ fJ ($W$W in µm).
4. Choose W. Because every width gives the same delay and the energy grows with $W$W, take the smallest width the technology allows. At $W = 1\,\mu\mathrm{m}$1μm, 8.64 fJ.

Check. This is (c)‘s floor, reached: with no fixed load $h = 1$ at every width, so the 200 ps that (c) approached as $W \to \infty$ holds for every $W$W. And (b) with $C_{load} = 0$ gives the same 8.64 fJ at 1 µm. ✓

Answer: the delay is 200 ps for every W, so W does not matter for speed; choose the minimum W, where the energy $8.64\,W$ fJ is least (8.64 fJ at 1 µm). This is MT17-4a’s “does it depend on W?” (M3).

Remember. A chain that drives only copies of itself has the same delay at every size; then the smallest size wins, on energy.

Check yourself In FN19-3, let C_load = 3 fF. Which W minimizes energy × delay, and what are the delay and the energy per transition there?

Energy × delay $\propto (3Wk_{gate} + C_{load})^2/(3Wk_{gate})$Cload​)2/(3Wkgate​), least where the gates’ load equals the side load: $3W \times 1\,\mathrm{fF/\mu m} = 3$ fF, so $W = 1\,\mu\mathrm{m}$1μm. The delay is $200 \times (1 + 1) = 400$ ps, twice the floor, and the energy $2 \times 6\,\mathrm{fF} \times 1.44\,\mathrm{V^2} = 17.3$ fJ.

5. FN10-4: four inverters with a side load

FN10-4, p6 (source figure; the “= 10 µm” notes are handwritten on the key).

FN10-4, p6 (Fall 2010, 20 points). A chain of four identical inverters sized 2W/W “for a beta-ratio of one”, each loaded by $C_{load}$Cload​. $k_{gate} = 2$ fF/µm; the FO1 delay is $\tau_1 = 25$ ps. The last output also carries $3W\,k_{gate}$3Wkgate​.

A beta-ratio of one at 2W/W means equal rise and fall: $R_{pfet} = 2R_{nfet}$2Rnfet​, the balanced inverter, and $\tau_1 = 3R_{nfet}k_{gate}$3Rnfet​kgate​. This is the MT17-4 chain (M3) with a number for the side load, so M3’s inverter-chain moves apply as they are.

FN10-4a: delay

FN10-4a, p6 (10 points). If $C_{load} = 20$ fF and $W = 1\,\mu\mathrm{m}$1μm, what is the delay from A rising (falling) to B rising (falling)?

Hint

What does each node carry, counted in units of one inverter’s input?

What it asks. The delay through four inverters, each output loaded by 20 fF, at $W = 1\,\mu$m. “A rising to B rising” is right for four inversions, and with balanced inverters the falling case is the same.

The idea. This is MT17-4b with a number where MT17-4 had the symbol $C_x$Cx​, so the electrical effort is a number too. Each stage is an inverter, $g = 1$1, so its delay is $h\,\tau_1$hτ1​, where $h$ is the node’s capacitance over the inverter’s own input (Chapter 7, Section 9). The convention matters here: a beta ratio of one at 2W/W makes rise and fall equal, and $\tau_1 = 3R_{nfet}k_{gate}$ is the FO1 delay of exactly this inverter, so no $R$ is needed.

FN10-4a

1. The node. Because every output drives the next inverter’s input and the side load: $3W\,k_{gate} + C_{load} = 6 + 20 = 26$ fF. In µm of gate (÷ 2 fF/µm): $3 + 10 = 13\,\mu\mathrm{m}$13μm, where the 10 µm is the key’s handwritten “= 10 µm”.
2. One stage. Because an inverter has $g = 1$1, its gain is $h = 26/6 = 13/3$13/3, and it takes $\tau_1 \times 13/3 = 25 \times 4.33 = 108.3$ ps. Rising and falling are equal, because the inverter is balanced.
3. Four stages. Because the four identical stages switch one after another: $4 \times 108.3 = 433$ ps.

Check. MT17-4b’s formula, $4\tau_1(1 + C_x/3Wk_{gate})$Cx​/3Wkgate​), with $C_x = 20$ fF: $100\,\mathrm{ps} \times (1 + 20/6) = 433$ ps. ✓

Answer: 433 ps (each stage 108.3 ps).

Remember. Convert the side load to µm of gate (or keep both in fF), add the next input, and divide by one input: that is $h$h, and an inverter chain takes $N\,h\,\tau_1$Nhτ1​.

The answer key agrees

It prints 432 ps, from rounding each stage to 108 ps first; unrounded, $4 \times 108.3 = 433$ ps.

FN10-4b: energy of one transition

FN10-4b, p6 (10 points). If $C_{load} = 20$ fF and $W = 1\,\mu\mathrm{m}$1μm, what is the energy dissipated by a single transition through this inverter chain? Ignore leakage currents, crowbar currents and the energy introduced by the “source” at A. Consider only dynamic charging energy.

Hint

One input edge: how many of the four nodes rise? And which supply does the question give you?

What it asks. The energy of one input edge through the chain, counting only the charging of the four nodes. “A single transition” decides the count: half the nodes rise.

The idea. This is MT17-4c with numbers. A rising node draws $CV_{DD}^2$ from the supply and a falling one draws nothing, so the energy is (the rising nodes) × $C_{node}V_{DD}^2$ (Chapter 6, Section 6). What is new: the question gives no $V_{DD}$VDD​, so write the energy with $V_{DD}^2$ first and choose a value only at the end.

FN10-4b

1. The node. Because the loads are those of (a), each of the four outputs carries 26 fF.
2. Which nodes rise. Because each inverter inverts, one input edge makes two nodes rise and two fall.
3. Price them. Because only a rising node draws from the supply, $CV_{DD}^2$ each, the two rising nodes draw $2 \times 26\,\mathrm{fF} \times V_{DD}^2 = 52\,\mathrm{fF} \times V_{DD}^2$VDD2​; counting dissipation instead, $4 \times \tfrac12 \times 26\,\mathrm{fF} \times V_{DD}^2$ is the same.
4. A number. Because the question gives no $V_{DD}$VDD​, take the key’s 2.5 V (“although any $V_{DD}$ assumption is valid”): $52\,\mathrm{fF} \times 6.25\,\mathrm{V^2} = 325$ fJ.

Check. MT17-4c’s formula, $2(C_x + 3Wk_{gate})V_{DD}^2$3Wkgate​)VDD2​, with $C_x = 20$ fF and $3Wk_{gate} = 6$ fF gives $2 \times 26 = 52\,\mathrm{fF} \times V_{DD}^2$VDD2​. ✓ Units: fF × V² = fJ.

Answer: $E = 2(C_{load} + 3Wk_{gate})V_{DD}^2 = 52\,\mathrm{fF} \times V_{DD}^2$VDD2​, which is 325 fJ (0.325 pJ) at the key’s 2.5 V.

Remember. When the question gives no supply, answer with $V_{DD}^2$ and then pick a value, saying so. Per transition, half the nodes rise.

The answer key agrees

It writes in 2.5 V by hand, “although any $V_{DD}$ assumption is valid”.

What this means for the midterm

Which midterm family uses each method. The inverter below threshold has its own approach section; the chains follow M3’s.

• Off-current from a current at threshold (FN19-1a): $I_{off} = I(V_T)/10^{V_T/S}$ is MT23-1b and MT24-2b (M3), MT17-1c with the temperature (M3) and M7’s Question 1. Below threshold, $I_{on}/I_{off} = 10^{V_{DD}/S}$10VDD​/S.
• Delay as charge over current (FN19-1c, FN17-10b, FN10-2b): $t_p \approx CV_{DD}/(2I)$CVDD​/(2I). The midterms ask it in the RC form instead; the subthreshold version is the same idea with an exponential current.
• Chain delay with a fixed side load (FN19-3a, c, FN10-4a): $N \cdot g \cdot h \cdot \tau_{inv}$ with $h = (C_{gates} + C_{side})/C_{gates}$Cside​)/Cgates​; no finite delay optimum, energy × delay least where the gate load equals the side load. This is MT24-2c–e, MT23-1d, MT21-4a and MT17-4a–d (M3 §1–§4), and the formula sheet’s inverter-chain section.
• Energy per transition (FN19-3b, FN10-4b): $\tfrac N2 CV_{DD}^2$ for $N$ nodes, as MT21-4b and MT17-4c (M3); per cycle it is $NCV_{DD}^2$ (MT23-1a, MT24-2a).
• A gate with stacks as a gain (FN19-3a): the stack rule gives $g$g, as in MT17-3d’s NAND4 (M3) and every path in M4.

Traps.

• Using the above-threshold law at a supply below $V_T$ (FN19-1b): it gives a negative current. Below threshold every current is on the exponential line.
• Delay to 50% against the full swing: a factor of 2 (FN17-10b’s key). Say which you use.
• Forgetting the series pair in a carry stage: each stage is $2\tau_1$ with no load, not $\tau_1$τ1​.
• “Minimize the delay” with a fixed load has no finite answer; with no fixed load the delay doesn’t depend on $W$ at all. Both are the answer the question wants, with the reason.
• Per transition against per cycle; and a $V_{DD}$ the question never gave (FN10-4b): write the energy with $V_{DD}^2$ and then pick a value if you must.

Time. Each of these parts is 2–4 minutes once the node capacitance (or the current) is written down. FN19-1 as a whole, 40 points, is about 12 minutes; FN19-3, 39 points, about 10.

What the keys get wrong

Part	The key	Here
FN17-10b	each inverter $(30\,\mathrm{fF})V_{DD}/I_{on}$(30fF)VDD​/Ion​: the full-swing time	the delay to 50% is half of it, $8 \times 30\,\mathrm{fF} \times V_{DD}/(2I_{on})$ (the FN10 key uses the ½)
FN10-4a	432 ps	433 ps (the key rounds each stage to 108 ps first)

FN17-10a, FN10-2a–b and FN10-4b agree with their keys after re-solving. FN19 has no key; its answers here are this guide’s own. FN17-10c and FN10-2c are left out (see the top of the page).