24. Beyond bulk CMOS: SOI, FinFETs and gate-all-around

Lecture 23, the course’s last and shortest lecture, steps back from circuits to the transistor itself. For many generations, making chips better meant shrinking one structure: the planar bulk CMOS transistor, built in the top of a silicon wafer. Then, in the lecturer’s words, “the electrostatics of this device have gotten so poor that you simply can’t scale this geometry anymore, and you have to go to another kind of geometry” (01:24). The lecture walks through the structures that came instead, in roughly the order industry tried them. First silicon on insulator (SOI): an oxide under the device, first used to make chips resistant to radiation. Then partially depleted SOI, with its floating body. Then fully depleted SOI, with an ultra-thin body and a back gate. Then the problem that ended bulk scaling: a subthreshold slope that had grown from 60 to about 120 mV/decade. The FinFET fixed it by gating a thin fin of silicon from three sides, and gate-all-around nanowires take the same idea one step further. Every one of these structures, the lecturer stresses, was “actually done and sold by foundries”, and circuits were designed in it (01:50–02:00).

Background for the final. No past paper tests this lecture. Read it for the context of numbers the exam does use: the subthreshold slope, the body effect and device widths. Each section is short, with Checks and at most one light example built on the course’s own devices.

After this chapter you can:

1. draw planar bulk CMOS and say which part of it SOI replaces, and why an insulator under the device stops most soft errors;
2. tell a partially depleted from a fully depleted SOI device, and explain the floating body and its history effect;
3. name PD-SOI’s two benefits (less source/drain capacitance, less body effect in a stack) and its price;
4. explain how an FD-SOI back gate sets $V_T$VT​, and what a $V_T$ shift does to leakage;
5. use $S$ to say by how many decades a device turns off, and why 120 mV/decade ended bulk scaling;
6. explain why a FinFET restores the slope, and size a device in whole fins;
7. say which capacitances a compact model leaves to extraction, and why a schematic simulation is optimistic;
8. say what a gate-all-around transistor changes, and what limits scaling past it.

Boxes and equations marked board were written in the lecture. Parts marked added are explanations or examples this guide adds. Remarks about companies and nodes are the lecturer’s account at the time of the recording.

Symbols

Symbol	Meaning	Unit	First appears
$V_{DD}$	supply voltage	V	§1
$Q$Q, $C$	the charge on a storage node and the node’s capacitance added	fC, fF	§1
$q$	the electron charge, $1.602\times10^{-19}$ C	C	§1
$N_A$	acceptor doping of the p body	cm⁻³	§2
$\phi_F$	Fermi potential of the body, $(kT/q)\ln(N_A/n_i)$	V	§2
$kT/q$	thermal voltage, 25.85 mV at 300 K	mV	§2
$W_{dmax}$	the depletion depth under the gate at threshold	nm	§2
$t_{Si}$	the thickness of the silicon film over the buried oxide added	nm	§2
$V_B$	the body’s potential added	V	§2
$V_T$VT​, $V_{T0}$	threshold voltage, and its value at $V_{SB} = 0$	V	§3
$V_{GS}$VGS​, $V_{SB}$	gate-to-source and source-to-body voltages	V	§3
$V_{FB}$	flat-band voltage	V	§3
$C_{ox}$	gate-oxide capacitance per area	F/cm²	§3
$Q_{bulk}$	depletion charge per area under the gate	C/cm²	§3
$C_j$	junction (diffusion) capacitance of a source or drain	fF	§3
$I_{on}$Ion​, $I_{off}$	a device’s current at $V_{GS} = V_T$ (in this chapter’s plots) and at $V_{GS} = 0$	A	§4
$S$	subthreshold slope: the gate voltage for one decade of current	mV/decade	§4
$m$	the non-ideality factor in $S = m(kT/q)\ln 10$	—	§5
$n_{fin}$	number of fins in a FinFET	—	§6
$H$H, $T$T, $p$	a fin’s height, its thickness, and the fin pitch added	nm	§6
$W_{eff}$	effective width: the gated perimeter that carries current added	nm	§6
$L$	channel length	nm	§6
$F$F, $f$f, $\tau_{inv}$	path effort, stage gain and the inverter’s delay unit (Chapter 8)	—, —, ps	§6
$n_w$nw​, $a$	the number of nanowires in a stack, and the side of a square wire added	—, nm	§8

Notation trap. $T$ here is the fin’s thickness. This chapter writes temperature in words (“300 K”, “room temperature”), never as $T$T.

1. From bulk CMOS to silicon on insulator: radiation hardness and soft errors

You need

The planar NFET in cross-section (Chapter 9). Shallow trench isolation (STI), oxide-filled trenches, separates neighbouring devices. Between them sit the $n^+$ source and drain, and over the channel the gate on a thin oxide. The p body is the wafer itself, and a $p^+$ contact, the body tap, ties it to ground (Chapter 5).

A reverse-biased junction collects carriers (Chapter 3). The source and drain are $n^+$–p junctions with the body, held at zero or reverse bias. Each has a depletion region with an electric field across it; an electron that wanders into that field is swept to the $n^+$ side, a hole to the p side.

A memory bit is a small charge (Chapter 19). An SRAM cell holds its bit as a voltage on a small internal node; if that node is pulled far enough the wrong way, the cell’s cross-coupled inverters latch the wrong value.

The question. What is “bulk CMOS”, why did a layer of insulator under the transistor first appear, and what does it protect against?

From bulk CMOS to SOI (board, 00:32–04:33)

1. Bulk CMOS board. The board draws the planar device: STI, $n^+$n+, the gate, $n^+$n+, STI, then a $p^+$ region between two more STI boxes, all in a p substrate that is “plugged and tied elsewhere” (00:40). The transistor is built in the top of a thick, uniform wafer: the “bulk”. The figure below redraws it.
2. Scaling one structure. For many generations, technology development meant shrinking this one structure, with changes to its gate and dielectric materials along the way (01:09; the gate-dielectric story is Chapter 4 §13’s). Then the device’s electrostatics became too poor to keep shrinking it (01:24). Section 5 says what “poor electrostatics” means in numbers.
3. SOS and SOI board. The first departure was to grow the silicon on an insulator. SOS, silicon on sapphire, grows a thin silicon layer epitaxially on sapphire, a very good insulator whose crystal lattice is close to silicon’s (02:39). SOI, silicon on insulator, generalizes it; the insulator is silicon dioxide (03:04; the board’s “silicon dioxide” with an arrow to the I).
4. Rad-hard electronics board. Their first use was radiation-hard (“rad-hard”) electronics, for space, against soft errors (03:04–03:30).
5. How a soft error happens board. Outside the atmosphere, a cosmic ray crosses the chip and leaves a track of electron–hole pairs behind it (03:30). In bulk silicon the track runs deep into the substrate, and the reverse-biased junctions nearby collect the carriers: the board’s wavy track through the drain and its “e⁻ h⁺”. Enough collected charge on a storage node flips a memory cell (03:56).
6. Why an insulator helps. In SOI the device sits in a thin film over oxide. The track crosses very little silicon that is connected to the device, so little charge is generated where a junction can collect it, and few errors occur (04:05–04:33).

Planar bulk CMOS, redrawn from the board (Lecture23 @ 02:54). The transistor is built in the top of the p substrate (the bulk wafer); shallow-trench isolation (STI, grey) separates it from its neighbours, and the $p^+$ tap ties the body (B) to ground. The ground connection is added: the board says the substrate is “tied elsewhere”.

A soft error, after the board (Lecture23 @ 08:03) added. (a) In bulk, a particle’s track runs deep into the substrate and leaves electron–hole pairs all along it; the drain junction’s field collects the electrons onto the drain. (b) In SOI, the track crosses only the thin film; the pairs made under the buried oxide cannot reach the device. The board’s track is wavy; it is drawn straight here.

How much charge is a bit? added A storage node of capacitance $C$ at voltage $V$ holds $Q = CV$CV; dividing by $q$ counts the electrons. For example, a 1 fF node at 1.0 V holds 1.0 fC, about 6,242 electrons; a smaller node of 0.5 fF at 0.8 V holds 0.40 fC, about 2,497. A particle that frees a few thousand electrons near the node’s junction can be enough to upset it, if the junction collects a large share of them, and every new technology makes the node smaller. (Illustrative values, “for example”.)

Traps.

• “A soft error is a defect.” The cell is not damaged; it holds the wrong bit, and the next write fixes it. That is what “soft” means.
• “SOI has no junctions.” The source and drain junctions remain, at the sides of the film; what is gone is the deep collecting volume under them.

Check yourself Why is a cell less likely to flip in SOI than in bulk, for the same particle?

The particle frees charge all along its track, but only carriers in silicon connected to the device can be collected by its junctions. In bulk that is the whole depth of the track through the substrate; in SOI it is only the short stretch through the thin film, because the buried oxide cuts the device off from the substrate. Less collected charge, fewer flips.

Check yourself A storage node holds 0.8 fF at 0.9 V. How many electrons does it store, and would a particle that frees 2,000 electrons at its junction be a concern?

$Q = CV = 0.8\ \text{fF} \times 0.9\ \text{V} =$ 0.72 fC, and $0.72\ \text{fC}/q =$ 4,494 electrons. A particle that frees 2,000 electrons there is of the same order: if a large share is collected, it can pull the node far enough to flip the cell. Yes, a concern.

Check yourself What did SOS use as its insulator, and what does SOI use?

SOS grows the silicon on sapphire (an insulator whose lattice is close to silicon’s); SOI puts it on silicon dioxide.

2. Partially depleted SOI: the buried oxide and the floating body

You need

The depletion depth at threshold (Chapter 3). With a positive gate voltage, the p body under the gate is depleted of holes to a depth that grows until the channel forms. At threshold the surface has bent by $2\phi_F$2ϕF​, and the depth is at its maximum:

$$W_{dmax} = \sqrt{\frac{2\kappa_s\varepsilon_0\,(2\phi_F)}{qN_A}},$$$$\phi_F = \frac{kT}{q}\ln\frac{N_A}{n_i},$$

for a uniformly doped body, in the depletion approximation ($\kappa_s = 11.7$κs​= for silicon, $n_i = 10^{10}$ cm⁻³, $kT/q$ = 25.85 mV at 300 K).

The body tie in bulk. In bulk CMOS the $p^+$ tap holds the body at ground:

Planar bulk CMOS (Section 1): the $p^+$ tap ties the body to ground. Original figure ↑

A junction leaks in reverse and conducts forward (Chapter 2). A reverse-biased pn junction passes a tiny leakage current; forward-biased by more than a few tenths of a volt, it conducts strongly.

A floating node follows its capacitors (Chapter 21). A node with no DC path is moved by the capacitors joining it to its neighbours: when a neighbour steps, the node steps by a capacitive-divider share.

The question. What does a practical SOI transistor look like, how are its wafers made, and what happens to its body when there is no tap to tie it?

PD-SOI and its floating body (board, 04:42–08:55 and 11:40–12:46)

1. PD-SOI board. “PD-SOI ⇒ partially depleted” (04:42). IBM pushed this technology from the mid-to-late 1990s, as the lecturer recalls (05:01).
2. The buried oxide board. The device sits on a BOX, a buried oxide, over the silicon substrate: STI, $n^+$ source, the p body (hatched on the board), $n^+$ drain, STI, with oxide on all sides (05:21–06:00).
3. Making the BOX. Two ways (06:00–06:59). SIMOX board: implant oxygen deep into an ordinary wafer, then anneal out the damage. (The name stands for separation by implantation of oxygen added; the lecturer did not recall it.) Or bonded wafers: grow oxide on two wafers, bond them oxide to oxide, and etch one back down to a thin film, stopping at an etch stop. Bonding gives better silicon, and the lecturer saw it used for most SOI wafers.
4. The body floats. With oxide below and STI at the sides, there is nowhere to put a body tap: the body is “not connected to any known potential” (07:28). It is a floating body board. Compare the bulk device of Section 1, whose $p^+$ tap holds it at ground.
5. Why “partially depleted”. The depletion region under the gate does not reach the BOX, so a neutral p region remains between them (07:59). That neutral region has a potential: the body potential $V_B$VB​. It is real, but nothing sets it.
6. What does set it (11:40–12:45). Two things. Capacitive coupling to the gate, source and drain moves the body potential without changing its charge. Two diodes, body to source and body to drain (the board’s “S —⊳|— B —|⊲— D”, anodes at B), change the charge: in reverse bias they leak, slowly charging the body; forward-biased, they “would immediately turn on and drain any charge”. Hold the source and drain at $V_{DD}$ long enough, and the body rises toward $V_{DD}$ too.
7. The floating body effect board. So the body bias depends on what the transistor did before: “There’s an additional history dependence in the way this transistor operates. It has memory” (08:29). Designers were unwilling to accept that uncertainty, which is one reason PD-SOI never spread widely.

Partially depleted SOI, redrawn from the board (Lecture23 @ 09:15). The device sits on the buried oxide (BOX) over the silicon substrate (Si), with STI at its sides. The depletion region under the gate (dotted edge) stops short of the BOX, leaving a neutral body B (shaded, added) with no tap: the floating body.

The board (Lecture23 @ 08:48)

Lecture23 @ 08:48Bulk CMOS and its soft-error track; SOI and SOS; rad-hard; PD-SOI on its buried oxide; the floating body effect; SIMOX.

Fair copy of the board above (Lecture23 @ 08:48), mark for mark in its own layout, all in black. A white pen wrote the title and the two lines under it; a cyan pen drew the bulk device; a violet pen wrote everything from SOI on, and also the soft-error marks over the bulk drawing: the rings round both n⁺ regions, the particle track and “e⁻ h⁺”. The violet pen carries the lecture on to SOI rather than marking a separate layer, so it takes no accent. The “r” of “rad-hard”, washed out by the lecturer’s face, and the middle of the PD-SOI row, under his arm, are read from 09:15, where nothing has changed. The hand’s last “STI” ends in a hook that reads like “STJ”. The labels inside the PD-SOI row are set smaller than the hand.

What sets a floating body’s potential, from the board (Lecture23 @ 12:46) and the speech. The two body diodes (the board’s, anodes at B) change the body’s charge: their reverse leakage slowly charges it, and a forward bias drains it at once. The capacitors to G, S and D (grey, with dashed wires: spoken at 11:40, not drawn) move its potential without changing its charge.

The board (Lecture23 @ 12:46)

Lecture23 @ 12:46The PD-SOI trade: the history effect against reduced S/D capacitance; the stack with its body above ground; the body's two diodes.

Fair copy of the board above (Lecture23 @ 12:46), mark for mark in its own layout, all in black: one violet pen wrote everything new; the title and the two lines under it are the opening board’s white pen. The right half is 08:48’s, copied from the same marks; the bulk drawing and the bracket’s foot are wiped, and two tiny stroke ends left of the bulk drawing are left out. The middle of the PD-SOI row, under the lecturer’s hand, is read from 13:31; the tick above the gate is new by 12:18. The stack’s label, beside the hand, is read from 12:18: a short wavy line from the body, then $V_B$ ↑ and “> 0”: the body floats above ground (10:39–11:14). The hand’s “+” before “reduced” has a tail and looks like a “t”. The diodes, new at 12:46, are the body’s two junctions to the source and the drain.

PD or FD: compare the film with the depletion depth. added The depletion region can be no deeper than $W_{dmax}$Wdmax​. If the silicon film is thicker ($t_{Si} > W_{dmax}$tSi​>Wdmax​), a neutral body is left over it: partially depleted. If the film is thinner ($t_{Si} < W_{dmax}$tSi​<Wdmax​), the depletion reaches the BOX first and no neutral body is left: fully depleted (Section 4).

Partially or fully depletedadded

$$t_{Si} > W_{dmax}\ \Rightarrow\ \text{PD: a neutral, floating body}$$$$t_{Si} < W_{dmax}\ \Rightarrow\ \text{FD: no body}$$

Holds when: uniform body doping, depletion approximation; W_dmax as in Chapter 3 (the depth at threshold)

Derive it in one line: the depletion stops either at $W_{dmax}$ or at the BOX, whichever comes first.

A worked example: Chapter 3's body in a film (added; films for example)

1. The body. Chapter 3’s NFET, $N_A = 10^{17}$ cm⁻³: $2\phi_F = 2 \times 0.02585 \times \ln(10^7) =$ 0.833 V.
2. The depth. $W_{dmax} = \sqrt{2 \times 11.7 \times 8.854\times10^{-14} \times 0.833/(1.602\times10^{-19} \times 10^{17})}$ cm $=$ 103.8 nm.
3. A 150 nm film. It is thicker than 103.8 nm, so 46.2 nm of neutral body is left under the depletion: PD.
4. Heavier doping. At $N_A = 10^{18}$ cm⁻³, $2\phi_F =$ 0.952 V and $W_{dmax} =$ 35.1 nm: the depletion is ten times denser in charge and only about a third as deep.

Traps.

• “Floating” means “at zero”. It drifts with the history, and on average sits above ground (Section 3).
• “The body diodes act only when forward-biased.” Their reverse leakage is exactly what charges the body, slowly.

Check yourself Why does a PD-SOI body have a potential at all, and an FD-SOI body none?

In PD-SOI the depletion region stops above the BOX, so a neutral p region is left, and a neutral region has a well-defined potential: the body potential, set by coupling and the two diodes. In FD-SOI the film is depleted all the way through; there is no neutral region, so there is no body whose potential could float.

Check yourself A PD-SOI NFET's source and drain both sit at V_DD for a long time. Which diodes act, in which direction, and where does the body end up?

Both diodes (body to source, body to drain) are reverse-biased, since the body starts below $V_{DD}$VDD​; their reverse leakage carries charge into the body. Nothing drains it (a diode would only conduct if the body went above $V_{DD}$VDD​), so the body rises slowly toward $V_{DD}$VDD​, as the lecturer says (12:45).

Check yourself At N_A = 10¹⁸ cm⁻³, is a 50 nm film partially or fully depleted?

Partially: $W_{dmax}$ = 35.1 nm at that doping, and the 50 nm film is thicker, so 14.9 nm of neutral body is left.

3. What PD-SOI buys: less junction capacitance, less body effect

You need

Junction capacitance (Chapter 5). The source and drain are reverse-biased junctions with the body, so each is a capacitor, $C_j = \kappa_s\varepsilon_0/W$ per area of junction ($W$W the depletion width). In bulk the junction has a bottom (the area under the diffusion) and sidewalls (its perimeter); both count.

The body effect (Chapter 5). If the source sits $V_{SB}$ above the body (with $V_{SB} \ge 0$0, so the source junction stays off), the depletion under the gate must hold $2\phi_F + V_{SB}$VSB​, and

$$V_T = V_{FB} + 2\phi_F + \frac{\sqrt{2qN_A\kappa_s\varepsilon_0\,(2\phi_F + V_{SB})}}{C_{ox}} .$$

In a stack of two NFETs with grounded bodies, the upper device’s source is the middle node, above ground, so its $V_T$ rises and its overdrive $V_{GS} - V_T$ falls. Chapter 5’s example: source at 1 V, $V_{SB}$ = 1 V, $V_T$ rises from 0.500 V to 0.626 V.

PD-SOI (Section 2). The device sits on a buried oxide; its body floats.

Partially depleted SOI (Section 2): the source and drain sit on the BOX; the body floats. Original figure ↑

The question. PD-SOI’s floating body made designers uneasy. What did it offer in return?

Two benefits and a price (board, 12:18)

1. Reduced S/D capacitance board. The board’s “+ reduced S/D capacitance” (12:18). The source and drain diffusions are now “surrounded on these sides by oxide”, so their capacitance “decreases dramatically” (09:00–10:02). added They reach down to the BOX, so the bottom junction against the body, usually the larger part, is gone; the sidewall facing the body under the gate remains, so the junction capacitance falls a lot but not to zero.
2. The stack in bulk. In a stack, the upper NFET’s source is the middle node, above ground, while its body is tied to ground: it sees a positive $V_{SB}$VSB​, its threshold is pushed up, and it switches more slowly (10:09–10:39). The body effect is weaker in scaled devices, but “there still is a body effect”.
3. The stack in PD-SOI. The upper device’s body is not tied. It floats, and “tends to float up”, on average above ground (the board’s “$V_B$VB​ ↑ > 0” beside the boxed device). Its $V_{SB} = V_x - V_B$ is smaller, so its body effect is smaller and it switches better, “theoretically” (10:39–11:14).
4. The price board. “− history effect”: the body potential, and so $V_T$VT​, depends on what the device did before (Section 2).

Where the junction capacitance goes added (after the board’s “+ reduced S/D capacitance”, Lecture23 @ 12:18). (a) In bulk the drain meets the p body along its bottom and its channel-side wall (thick, with the dotted depletion edge); both carry $C_j$Cj​, while its STI side is oxide. (b) In PD-SOI the drain reaches the BOX, so the bottom is oxide; only the sidewall facing the body is left.

The stack’s upper device, redrawn from the board (Lecture23 @ 12:18). (a) In bulk both bodies are tied to ground, so the upper device sees $V_{SB} = V_x$Vx​, the middle node’s voltage. (b) In PD-SOI the bodies float; the upper body rises above ground ($V_B > 0$VB​>0), so $V_{SB} = V_x - V_B$ is smaller. $V_x$ is added.

A worked example: Chapter 5's stack with a floating body (added; body voltages for example)

1. The device. Chapter 5’s NFET ($N_A = 10^{17}$NA​= cm⁻³, $t_{ox}$ = 5.4 nm, $V_{T0}$ = 0.500 V) as the upper device of a stack, its source at 1 V and its gate at 2.5 V, so $V_{GS}$ = 1.5 V.
2. Bulk. The body is tied at 0 V: $V_{SB}$ = 1.0 V, so $V_T =$ 0.626 V and the overdrive is $1.5 - 0.626 =$ 0.874 V.
3. PD-SOI, body at 0.3 V. $V_{SB} = 1.0 - 0.3 = 0.7$ V, so $V_T =$ 0.593 V and the overdrive is 0.907 V.
4. PD-SOI, body at 0.5 V. $V_{SB}$ = 0.5 V, $V_T =$ 0.569 V, overdrive 0.931 V: 6.5 % more than in bulk.
5. The catch. The body’s 0.3 V or 0.5 V is not a design value: it depends on the history. That uncertainty is the history effect.

Traps.

• “The floating body always helps.” It varies with history, so the delay becomes uncertain; a timing check needs both ends of the range.
• “SOI has no junction capacitance.” The sidewall to the body remains.

Check yourself Which part of the drain's junction capacitance does the BOX remove, and which remains?

It removes the bottom junction: the drain now stands on oxide, not on p silicon. The sidewall facing the body under the gate is still a junction, so its capacitance remains.

Check yourself In the worked example's stack, the floating body of the upper device sits at 0.2 V. What is its V_SB, and is its V_T above or below the bulk device's 0.626 V?

$V_{SB} = 1.0 - 0.2 =$ 0.8 V. Then $V_T = V_{FB} + 2\phi_F + \sqrt{2qN_A\kappa_s\varepsilon_0(0.833 + 0.8)}/C_{ox} =$ 0.604 V, below the bulk device’s 0.626 V: the smaller $V_{SB}$ means less body effect.

Check yourself Why would a designer distrust a delay that depends on what the gate did a microsecond ago?

Static timing checks each path once, at its worst case. If a device’s $V_T$ moves with its switching history, the worst case depends on the input sequence, which no single analysis covers; the designer must margin for the whole range, and so loses part of the gain.

4. Fully depleted SOI: the ultra-thin body and the back gate

You need

PD or FD (Section 2). A film thicker than the depletion depth $W_{dmax}$ keeps a neutral, floating body (PD); a thinner one is depleted through (FD).

Partially depleted SOI (Section 2): a neutral body is left between the depletion edge and the BOX. Original figure ↑

The threshold (Chapter 3). $V_T = V_{FB} + 2\phi_F + Q_{bulk}/C_{ox}$Qbulk​/Cox​: the flat-band voltage $V_{FB}$VFB​, set mainly by the gate’s work function (Chapter 3); the band bending $2\phi_F$2ϕF​; and the depletion charge $Q_{bulk} = qN_AW_{dmax}$ over the oxide capacitance.

The subthreshold line (Chapter 4). Below threshold the current falls tenfold for every $S$ volts the gate goes below $V_T$VT​; $S$ is the subthreshold slope, about 60 mV/decade at best.

The question. What if the film is so thin that there is no body at all? What then sets the threshold, and what can a second gate under the film do?

FD-SOI (board, 12:53–15:52)

1. FD-SOI board. Fully depleted SOI: the same device on oxide, but its film is undoped or only lightly doped, and thin, so it is depleted all the way through (12:53–13:34). There is no neutral region and no body potential: the lecturer calls it “a three-terminal transistor” (07:59). So there is no floating body effect.
2. What sets $V_T$VT​. With no body, the threshold “is entirely determined by the electrostatics, the work function, and more importantly by the exact thickness” of the film (13:34–14:14).
3. Ultra-thin body board. These are ultra-thin-body devices (14:14). ST was making them at the time (the board’s “FD-SOI (ST)”).
4. The back gate board. Under the film, inside the buried oxide, a conducting back gate: heavily doped silicon, for example, though the lecturer did not recall the material (14:27). The back gate sets $V_T$ (the board’s “$V_T$VT​ control”); the top gate switches the device (14:53).
5. What it is for. Ultra-low-power chips: in standby, raise $V_T$ through the back gate and shut off the leakage (15:22).
6. The turn. These SOI variants offered “extra functionality”. Meanwhile scaling was running into a more fundamental problem (15:52): Section 5.

Fully depleted SOI with a back gate, redrawn from the board (Lecture23 @ 15:24). The film, of thickness $t_{Si}$tSi​, is depleted through: there is no neutral body. A back gate (BG, label added; the board’s label is unclear) buried in the oxide under the film sets the threshold (the board’s “$V_T$VT​ control”); the top gate switches.

The board (Lecture23 @ 16:05)

Lecture23 @ 16:05FD-SOI (ST): the ultra-thin body with its back gate and V_T control, beside the PD-SOI board.

Fair copy of the board above (Lecture23 @ 16:05), mark for mark in its own layout, all in black: one violet pen wrote everything new; the title and the two lines under it are the opening board’s white pen. The right half is 12:46’s, copied from the same marks. “History effect”, “reduced S/D capacitance” and the stack are wiped by 13:31. The “F” of “FD-SOI” is written over a “P”. The lecturer bends at the far left but covers no stroke (checked against 15:24). The back gate’s label is unclear, so it is copied as its strokes, two small loops and two ticks; the speech calls the back gate conducting, for example “heavily doped silicon”, and the lecturer is unsure what material is used (14:27–14:53).

Why the doping drops out added. In Chapter 3’s formula the depletion term is $Q_{bulk}/C_{ox}$Qbulk​/Cox​. In a fully depleted film the depletion charge can be no more than the film holds, $qN_At_{Si}$ per area. For a thin, lightly doped film that term is tiny, so the threshold rests on $V_{FB}$VFB​, that is, on the gate’s work function. The film’s thickness matters through the electrostatics of the thin body, which is the lecturer’s stronger claim; this chapter quotes it rather than deriving it.

How much a $V_T$ shift buys added. Below threshold, every $S$ volts of $V_T$ is a decade of leakage at $V_{GS} = 0$0, so raising $V_T$ by $\Delta V_T$ divides $I_{off}$ by $10^{\Delta V_T/S}$10ΔVT​/S. The same arithmetic sizes the high-$V_T$ header of Chapter 23 §12.

Leakage against a threshold shiftadded

$$\frac{I_{off,1}}{I_{off,2}} = 10^{\Delta V_T/S}$$

Holds when: below threshold, on the log-linear subthreshold line of slope S; the same device, only V_T moved

Derive it: $I_{off} \propto 10^{-V_T/S}$ (the subthreshold line evaluated at $V_{GS} = 0$0); divide the two.

A worked example: the film's charge and the back gate's knob (added; values for example)

1. The bulk device’s depletion term. Chapter 5’s NFET ($N_A = 10^{17}$NA​= cm⁻³, $C_{ox} = 6.39\times10^{-7}$ F/cm²): $Q_{bulk}/C_{ox} =$ 0.260 V of its 0.500 V threshold.
2. The same doping in a 10 nm film. The most the film can hold is $qN_At_{Si} = 1.602\times10^{-19} \times 10^{17} \times 10^{-6}$ C/cm², and over $C_{ox}$ that is 25.1 mV; a 7 nm film, 17.5 mV. The work function now carries the threshold.
3. A back gate that raises $V_T$ by 100 mV. The leakage falls by $10^{0.1/S}$100.1/S: ÷34.6 at 65 mV/decade, ÷12.9 at 90, ÷6.8 at 120. A steep slope makes the back gate a strong knob.

Traps.

• “Set an FD device’s $V_T$ by its doping, as in bulk.” With no body there is no $2\phi_F$-and-doping recipe: the work function and the film’s thickness set it.
• “The back gate is Chapter 5’s body bias.” There is no body to bias; the back gate acts through the oxide on the depleted film, as a second, weaker gate.

Check yourself Why is there no floating body effect in FD-SOI?

The film is depleted all the way to the BOX, so no neutral region is left. A floating body effect needs a neutral body whose potential can drift with history; here there is none.

Check yourself In standby, a back gate raises V_T by 150 mV on a device with S = 75 mV/decade. By what factor does the leakage fall, and how much V_T shift would the same factor need at 120 mV/decade?

$10^{150/75} = 10^2$102: the leakage falls 100 times. At 120 mV/decade, two decades need $2 \times 120 =$ 240 mV of shift: a poor slope makes every knob on $V_T$ weaker.

Check yourself Why does the lecture say the film's thickness matters more than its doping?

In a thin film the depletion charge is capped by what the film holds, $qN_At_{Si}$qNA​tSi​, a few tens of millivolts of threshold at most, so the doping hardly moves $V_T$VT​. What remains is the gate’s work function and the electrostatics of a thin body, which change with its exact thickness.

5. The subthreshold slope: why bulk CMOS ended

You need

The subthreshold current (Chapter 4). Below threshold a MOSFET still conducts: carriers cross the source’s barrier thermally, so $I_D \propto e^{qV_{GS}/(mkT)}$eqVGS​/(mkT). On a log scale that is a straight line in $V_{GS}$VGS​, and the gate voltage for one decade of current is the subthreshold slope

$$S = m\,\frac{kT}{q}\ln 10,$$

59.5 mV/decade at $m = 1$ and 300 K: about 60, the floor for a barrier crossed thermally. Real devices have $m > 1$1, because the gate does not control the barrier perfectly.

Short-channel effects (Chapter 4). In a short device the drain’s depletion region reaches under the gate and lowers the barrier (DIBL): the gate controls less of the barrier, the output conductance worsens, and the slope flattens.

The question. What happened to the subthreshold slope as bulk devices shrank, what does a slope of 120 mV/decade do to leakage and to the threshold a chip can use, and why did that force new structures?

From 60 to 120 mV/decade (board, 16:25–17:50)

1. Bad electrostatics, first sign. Short-channel effects: an output conductance “that gets terrible” (16:25).
2. The ideal board. “Ideally the subthreshold slope at room temperature would be 60 millivolts per decade” (16:41).
3. The end of bulk board. “At about the 32 nanometer node, which was the sort of the end of bulk CMOS, this had creeped up to about 120 millivolts per decade. So almost a factor of two worse” (16:47). The board writes “32 nm ⇒ 120 mV/decade” under the 60.
4. What it costs. “Horrendous subthreshold leakage”, and further scaling would only make it worse (17:17). The worked example below puts numbers on it.
5. The way out. So “people went back” to thin bodies gated on more than one side, like the FD-SOI device of Section 4 with its back gate, and looked for an area-efficient version of that idea (17:17–17:50): the FinFET, Section 6.

Other numbers in this guide added. Chapter 4, from Lecture 4’s board, says bulk reached about 100 mV/decade at the 22 nm node and calls 80–100 typical; the past papers state 80 (FN10-2, FN12-1, FN17-10) or 90 (FN19-1, MT23-1b). The two lectures give round numbers for the same story, and the chapter quotes each as said. In terms of $m$m, 120 mV/decade is $m \approx$ 2.0 (100 is 1.68).

What the slope does: decades of turn-off added. On the subthreshold line, going from $V_{GS} = V_T$ down to $V_{GS} = 0$ lowers the gate by $V_T$VT​, which is $V_T/S$ decades. So a device’s turn-off ratio, from its current at $V_T$ to its leakage at zero, is $10^{V_T/S}$10VT​/S. With the same $V_T$ and the same on-point, a flatter slope leaks more.

Turn-off in decadesadded

$$\frac{I_D(V_T)}{I_D(0)} = 10^{V_T/S}, \qquad \frac{I_{off}(S_2)}{I_{off}(S_1)} = 10^{\,V_T/S_1 - V_T/S_2}$$

Holds when: below threshold, on the log-linear subthreshold line of slope S; current at V_GS = V_T taken as the on-point; the region above threshold is not modelled

Derive it: $\log_{10}I_D$ falls by $1/S$ per volt of $V_{GS}$VGS​; over $V_T$ volts it falls $V_T/S$ decades. The second form divides two such lines that share the on-point.

The subthreshold slope sets the turn-off added, computed from $I_D/I_D(V_T) = 10^{(V_{GS} - V_T)/S}$ with $V_T$ = 0.3 V and $S$ = 60, 90 and 120 mV/decade. All three lines share the on-point at $V_T$VT​; at $V_{GS} = 0$ they are 5, 3.33 and 2.5 decades down, so the 120 mV/decade device leaks 316 times more than the ideal one. Only the region below threshold is drawn; the model does not hold above it.

A worked example: the same threshold at three slopes (added; V_T for example)

1. The device. For example, $V_T$ = 0.3 V, and the same current at $V_{GS} = V_T$ for all three slopes.
2. At 60 mV/decade. $0.3/0.060 =$ 5 decades of turn-off: $I_D(V_T)/I_D(0) = 10^5$105.
3. At 90. $0.3/0.090 =$ 3.33 decades, a ratio of about 2,154.
4. At 120. $0.3/0.120 =$ 2.5 decades, a ratio of about 316.
5. The leakage cost. At 120 mV/decade the device leaks $10^{5 - 2.5} =$ 316 times more than at 60, for the same $V_T$ and on-current.
6. Or keep the turn-off. To keep $10^5$105, $V_T$ must be $5S$5S: 0.30, 0.45 or 0.60 V. A higher $V_T$ needs a higher $V_{DD}$ to keep the overdrive $V_{DD} - V_T$VT​, and energy grows as $V_{DD}^2$ (Chapter 23 §13). How low $V_{DD}$ can go, and where energy is least, both depend on $S$ (Chapter 23 §15 and §16).

Check. Each 60 mV of $V_T$ at the ideal slope is one decade; 0.3 V is five of them, so $10^5$105. At 120 mV/decade each decade costs twice the voltage, so the same 0.3 V buys half as many decades: 2.5, consistent with the ratio $10^{2.5} \approx 316$316.

Numbers to keep (Memorize): 60 mV/decade, the ideal at room temperature; about 120 at 32 nm in bulk (this lecture); about 100 at 22 nm (Lecture 4); FinFETs back near 60 (Section 6).

Traps.

• “120 is bigger, so better.” A larger mV/decade is worse: more gate voltage for each decade of current.
• “A lower $V_T$ fixes a poor slope.” It slides the line left and leaks more; only better electrostatics steepen the line.
• “Process will reach 50 mV/decade.” 60 mV/decade is the floor at room temperature for a barrier crossed thermally.

Check yourself Why does 60 mV/decade not scale with the node?

It comes from $kT/q$kT/q: carriers cross the barrier thermally, and their energy spread is set by the temperature, not by any dimension. At room temperature $(kT/q)\ln 10$ = 59.5 mV, whatever the node; shrinking the device can only make $m$ worse.

Check yourself A device needs I_on/I_off = 10⁴ between V_GS = V_T and 0. What V_T does it need at 60 and at 120 mV/decade, and why does the second force a higher V_DD?

Four decades need $V_T = 4S$4S: 0.24 V at 60 mV/decade and 0.48 V at 120. The device’s drive depends on its overdrive $V_{DD} - V_T$VT​; to keep the same overdrive with a threshold 0.24 V higher, $V_{DD}$ must rise by 0.24 V too, and the switching energy with it.

Check yourself What is m for a 120 mV/decade device at 300 K?

$m = S/((kT/q)\ln 10) = 120/59.5 \approx$ 2.0: the gate moves the barrier only half as much as the ideal.

6. FinFETs: a fin gated on three sides, width in whole fins

You need

The problem (Section 5). Bulk devices at 32 nm had a slope of about 120 mV/decade: the gate, on one side of the channel, no longer controlled the barrier well.

A thin, fully depleted body (Section 4). A film thinner than the depletion depth has no neutral body; a gate on more than one side of it controls it well.

Fully depleted SOI (Section 4): a thin film gated from the top and, through the back gate, from below. Original figure ↑

Width sets drive (Chapter 7). In planar CMOS a device’s current is proportional to its width $W$W, chosen freely: its resistance is $R/W$ and its gate capacitance $C_gW$Cg​W.

Path sizing (Chapter 8). A path of $N$ stages with path effort $F$ is fastest with equal stage gains $f = F^{1/N}$F1/N; its delay is the sum of the gains, in units of $\tau_{inv}$τinv​.

The 6T cell’s ratios (Chapter 19). The access NFET must beat the cell’s PFET to write, and lose to the pull-down NFET to read (read stability).

The question. What is a FinFET, why does wrapping the gate round a thin fin bring the slope back toward 60 mV/decade, and what does it mean for a designer that width now comes in whole fins?

The FinFET (board, 17:50–20:41)

1. The structure board. A very narrow fin of silicon stands up between two contacts, source and drain; the gate wraps over it, on three sides: the top, “but most importantly on these two sides” (17:56–18:48). The figure below shows it from above and in cross-section.
2. Why it works. The fin is fully depleted and squeezed by the gate from both sides, so the electrostatics improve “dramatically” (18:48). The slope “that was about 120 millivolts per decade got squeezed down, almost slammed right all the way back to 60 millivolts per decade. And this is huge” (19:04).
3. Width in fins board. In bulk CMOS the designer changes W continuously; now “the width is effectively quantized in number of fins” (19:55).
4. A three-fin device. Three fins run between shared source and drain contacts, with one gate across all of them; it has three times the drive of one fin (20:01–20:27). The layout tools (Virtuoso, at the recording) manage the fin grid.

The FinFET, redrawn from the board (Lecture23 @ 20:14). (a) From above: the fin runs from the source contact to the drain contact, and the gate crosses it; $L$ is the channel length (added). (b) Across the fin: the gate wraps the fin’s top and both sidewalls (arrows, added), over a thin gate oxide.

A three-fin device, redrawn from the board (Lecture23 @ 24:20): three fins between shared source and drain contacts, one gate across them; the curved arrow is the board’s channel-length mark. Its drive is three times one fin’s. The label $n_{fin} = 3$ is added.

How wide is a fin? added The current flows along the fin’s surfaces under the gate, so a fin’s effective width is its gated perimeter: two sidewalls of height $H$ and the top of thickness $T$T.

FinFET effective widthadded

$$W_{eff} = n_{fin}\,(2H + T)$$

Holds when: a rectangular fin of height H and thickness T, gated on its two sidewalls and top; every fin alike; the lecture gives only drive ∝ number of fins

Derive it from the perimeter. Memorize the lecture’s part: drive is proportional to $n_{fin}$nfin​.

A fin’s width is its gated perimeter added. (a) One fin: two sidewalls of height $H$ and a top of thickness $T$T, so $2H + T$T. (b) Fins at pitch $p$ under one gate: $W_{eff} = n_{fin}(2H + T)$T). For example, $H$ = 40 nm, $T$ = 10 nm and $p$ = 50 nm (illustrative, of no real process) give 90 nm per fin, and 270 nm of width in 150 nm of layout for three fins.

A worked example: width and sizing in whole fins (added; dimensions for example)

1. One fin. For example, $H$ = 40 nm and $T$ = 10 nm: $2 \times 40 + 10 =$ 90 nm of width.
2. The steps. One to four fins give 90, 180, 270, 360 nm: the only widths available.
3. Width without area. At a 50 nm fin pitch, three fins put 270 nm of width into 150 nm of layout, 1.8×: the fin’s height buys width without area.
4. A sized path. Three inverters drive $F = C_{out}/C_{in} = 50$50. Equal gains give $f = 50^{1/3} =$ 3.684 and ideal sizes 1, 3.68, 13.57 fins; the delay is $3 \times 3.684 =$ 11.05 $\tau_{inv}$τinv​.
5. Rounded to whole fins. Sizes 1, 4, 14 give gains 4.00, 3.50, 3.57 and a delay of 11.07 $\tau_{inv}$τinv​: +0.17 %. Large stages barely notice the rounding.
6. Small devices do. A gate that wants 1.5 fins must take 1 (−33 % drive) or 2 (+33 %). Keepers and SRAM ratios, where one device must be a set fraction of another, feel the quantization most.

Check. The delay against the gains is flat near the optimum (Chapter 8), so gains of 3.5–4.0 around 3.684 should cost well under a percent; 0.17 % fits.

Traps.

• “A fin’s width is $T$T.” The current flows along the sidewalls too: the width is the gated perimeter, mostly $2H$2H.
• “Fins are a continuous W.” Not in a ratio that must be exact (SRAM, keepers): the nearest whole fins may be 33 % off.
• “The slope is back to exactly 60.” “Almost”: close to it, not at it.

Check yourself Why does gating a thin fin from both sides restore the slope?

The slope degrades when the gate controls only part of the barrier between source and drain, and the drain’s field controls the rest. A thin, fully depleted fin with the gate on both sidewalls (and the top) has no part of the channel far from a gate, so the gate controls the barrier almost completely and $m$ returns close to 1.

Check yourself A 6T cell in fins: the pull-down must be stronger than the access NFET for a safe read. With one fin each the ratio is 1. What is the smallest fin count for the pull-down that gives a ratio above 1, and what does it cost?

Two fins: a ratio of 2, since drive goes with the fin count; nothing between 1 and 2 exists. It costs one more fin pitch for each pull-down, so the cell grows, and the ratio is set by the fin grid rather than tuned.

Check yourself With H = 40 nm and T = 10 nm, how many fins match a planar device of 0.5 µm?

One fin is 90 nm, so $500/90 = 5.56$ fins: round up to 6 fins, 540 nm (5 fins, 450 nm, would be weaker).

7. Parasitic capacitance in 3-D devices: compact model against extraction

You need

Overlap capacitance (Chapter 5). The gate’s edge overlaps the source and drain, giving a capacitance from gate to source and from gate to drain that is there in every region of operation. In a modern device, the tall gate beside tall source/drain contacts adds more of the same kind; Lecture 5 already noted that splitting it between the device models and parasitic extraction “gets to be a little bit complicated”.

Compact models (Chapter 6). A simulator represents each transistor by a compact (SPICE) model: equations for its currents and the capacitances that belong to the device itself.

Extraction (Chapter 9). From the layout, extraction adds the resistances and capacitances of the wires and of the layout’s geometry to the netlist.

The FinFET (Section 6): the gate stands up over the fin.

The FinFET (Section 6): the gate wraps over a fin that runs between the contacts. Original figure ↑

The question. A FinFET is a tall, three-dimensional structure. Which capacitances surround it, which of them does the compact model include, and what does that mean for a simulation of the schematic?

Contact-to-gate capacitance (board, 20:56–23:53)

1. The side view board. Along the fin: the gate stands up over it, and from the source and drain big contacts rise beside it, up to metal 1 (20:56–21:57). Between each contact and the gate there is a capacitance: the board’s two capacitor marks, later ringed.
2. Two places for capacitance board. “compact model ⇒ capacitance; extraction ⇒ others” (24:20): the compact model holds some of the device’s capacitances, and extraction adds the others (22:26).
3. Which is which. “These capacitances between the contact and the gate, these are not included in the compact models and are almost always included as part of extraction” (22:52). They behave like overlap capacitance: they load the gate and couple it to the drain.
4. The consequence. So “your simulations with just the schematic level are not as accurate as they should be” (23:22). A schematic sees only the compact model, so it misses this capacitance and comes out optimistic. added It is the same lesson as HW4’s: extraction only adds capacitance (and resistance), so the extracted circuit is never faster than the schematic.
5. Getting worse. The problem grows as devices build up “more and more in the third dimension” (23:53).

Contact-to-gate capacitance, redrawn from the board (Lecture23 @ 24:20). The contacts rise from the source and drain, beside the gate, to metal 1 (M1, added from the speech). The capacitance between each contact and the gate ($C_{cg}$Ccg​) is left to extraction; the gate-to-channel capacitance ($C_{gc}$Cgc​, grey with dashed leads, added for contrast) is in the compact model.

Where is each capacitance? added A walk round the side view, in place of a numerical example. The lecture places only the contact-to-gate capacitance; the other rows follow the usual split.

Capacitance	Where	Seen by
gate to channel ($C_{gc}$Cgc​)	under the gate, through its oxide, to the fin	the compact model
junction, fin to substrate	at the source and drain	the compact model
contact to gate ($C_{cg}$Ccg​)	across the gap between each tall contact and the gate	extraction only
contact to contact, contact to metal 1	above the device	extraction

Traps.

• “The schematic’s delay is the layout’s.” It leaves the contact-to-gate capacitance out, so the real delay is longer.
• “Add every extracted capacitance on top of the model.” Some models lump part of the parasitics in already; adding them again counts them twice. “You’ve got to be very careful to know exactly … what’s being included” (22:26).

Check yourself Why does a contact-to-gate capacitance act like an overlap capacitance?

It joins the gate to the source or drain directly, through the gap beside the gate, whatever the channel is doing: a fixed capacitance from gate to source and from gate to drain, like the overlap at the gate’s edges. On the drain side it also couples the input to the output, so a switching output doubles its effect, as Chapter 21’s Miller factor does for coupling capacitance.

Check yourself An inverter's schematic simulation gives a delay of 10 ps; extraction adds contact-to-gate capacitance on its input and output. Will the extracted delay be larger or smaller, and why can't it go the other way?

Larger. Extraction only adds capacitance (and resistance) to what the compact model already has; more charge to move through the same devices means more delay. It cannot remove the model’s capacitance, so it cannot make the circuit faster.

Check yourself Which tool step would catch a capacitance the compact model leaves out?

Parasitic extraction from the layout, followed by a simulation of the extracted netlist (Chapter 9’s flow after LVS).

8. 7 nm, 5 nm and gate-all-around nanowires

You need

The node ladder (Chapter 1). Each node’s name was $1/\sqrt2$ of the last, so each step halved the area; after 22 nm the names became a “potpourri” that no longer measures a length. Only a few companies can still afford the leading edge (Chapter 1).

The FinFET (Section 6): a fin gated on three sides, width in whole fins.

The FinFET (Section 6): the gate covers the fin’s top and two sidewalls, not its bottom. Original figure ↑

A barrier stops carriers only if it is high and wide (Chapter 4). An off transistor’s barrier is crossed thermally (the subthreshold current); added a barrier that is thin enough is also crossed by tunnelling, as electrons tunnel through a thin gate oxide (Chapter 4 §13).

The question. Where do FinFETs end, what does a gate-all-around transistor change, and what limits scaling past it?

Past the FinFET (board, 24:12–29:12)

1. Nodes without a ruler. 16, 14, 12 nm, “and continuing to go down”; the names “don’t follow the strict square root of two anymore” (24:12–24:39). added The $1/\sqrt2$ ladder from 16 nm would give 11.3, 8.0 and 5.7 nm.
2. FinFETs to 7 nm board. “7 nm ⇑ 5 nm” (25:35): the general belief at the recording was that FinFETs would reach about 7 nm (“we’re now at seven nanometers with FinFETs”).
3. What stops them. At those lengths even the FinFET’s electrostatics are not enough: “the barrier heights aren’t high enough”, and carriers tunnel straight through the barrier from source to drain, direct source–drain tunnelling (24:59). Getting from 7 to 5 nm needs “even stronger barriers, even stronger electrostatics”: a gate that holds the barrier higher. added At these lengths the barrier is also very short, and a short barrier must be all the higher to stop tunnelling.
4. GAA board. “GAA transistors”, “gate all around”, “nanowire transistors” (25:25–25:41). Instead of a fin’s single sheet, the channel is broken into stacked wires, three for example, each gated on all four sides; a device has a fixed number of wires per stack, and stacks are arrayed like fins (26:10–26:52).
5. Who is left. Only Intel, Samsung and TSMC were still pushing the leading edge, at the recording (27:17). Chapter 1 §5’s board has the same three at about 10 nm, and only TSMC and Samsung at 5 nm.
6. The end of the line? The lecturer’s view at the time: probably nothing beyond 5 nm. A well-known earlier paper had said 10 nm was the limit, and FinFETs proved it wrong; but source–drain tunnelling is a fundamental limit, “the end of the line” (27:52–28:45). Students going into industry will very likely design in FinFETs (28:45), and gate-all-around structures are “what’s going to be coming next” (29:12).

From FinFET to gate-all-around, redrawn from the board (Lecture23 @ 27:44). (a) The FinFET’s gate covers three sides of one fin. (b) A GAA (nanowire) device: three stacked wires ($n_w = 3$nw​=3, added), each wholly surrounded by the gate. (c) One wire (added): its four gated faces, each of side $a$a, traced thick.

The board (Lecture23 @ 29:44)

Lecture23 @ 29:44The last board: the subthreshold slope from 60 to 120 mV/decade and back; the FinFET, its fins and its contact capacitance; compact model against extraction; 7 nm to 5 nm; gate-all-around nanowires.

Fair copy of the board above (Lecture23 @ 29:44), mark for mark in its own layout, all in black. Three pens wrote it, each the next topic, so none takes an accent: violet the slope lines, the FinFET views and the fins; pale cream the side view with its contact capacitors, “compact model ⇒ capacitance / extraction ⇒ others” and the nanowire stack; white “GAA transistors” down to “7 nm” and the fin at the upper left. The slope is typeset 120 mV/decade, as said twice (16:58, 19:04) and as “almost a factor of two worse” than 60 requires; the hand’s middle digit, a flat top with a hooked drop, looks like its 7. The side view’s right contact, under the lecturer’s arm, is read from 28:59, where the ink is the same. “Ultra” in “-thin-body devices” is wiped; the dot before it is what remains. “transistors” after “GAA” is cramped against “32nm”, the hand’s “model” in “compact model” is cramped and reads like “body”, and “capacitance” is pressed against the fin layout: all three are set small, and “⇒ capacitance” sits a little left of its place.

How wide is a nanowire device? added As for the fin, the width is the gated perimeter, now all the way round each wire: for square wires of side $a$a, $4a$ each.

Nanowire effective widthadded

$$W_{eff} = n_w \times 4a$$

Holds when: square wires of side a, each gated on all four sides; all wires alike

Derive it from the perimeter, as for the fin.

A worked example added (dimensions for example). Three square nanowires of 10 nm side give $W_{eff} = 3 \times 4 \times 10 =$ 120 nm, against 90 nm for Section 6’s example fin. More to the point, every wire is gated on four sides, not three: no part of the channel is left for the drain to control.

Traps.

• “5 nm is the gate length.” Node names are labels now (Chapter 1 §4); nothing in a “5 nm” device need measure 5 nm.
• “GAA is new transistor physics.” It is the same MOSFET with the gate on every side. The limit it meets, tunnelling from source to drain, is the same one.

Check yourself What does a gate-all-around transistor gain over a FinFET, in one sentence about the gate?

The gate surrounds each wire on all four sides, including the bottom the FinFET’s gate leaves open, so it controls the whole channel’s barrier.

Check yourself Follow the 1/√2 ladder from 14 nm for two steps. What would the next two nodes be called, and what names did the industry use?

$14/\sqrt2 =$ 9.90 nm, then $14/2 =$ 7.00 nm: about 10 and 7, and the industry did call them 10 nm and 7 nm. The names happen to fit here, but by then they no longer measured any feature of the device.

Check yourself Why do carriers get through a very short channel's barrier, and what does a stronger gate do about it?

Over the barrier, carriers pass thermally, and only its height matters. Through it, they can also tunnel, and the chance falls steeply as the barrier gets higher or wider. At 7 and 5 nm the source-to-drain barrier is only a few nanometres wide, so it leaks by tunnelling unless it is high. A stronger gate (the fin’s three sides, then GAA’s four) holds the barrier higher: that is how FinFETs got below the once-predicted 10 nm limit to 7 nm, and how GAA aims at 5 nm (28:18). Past 5 nm, in the lecturer’s view, no barrier the gate can make is high enough: “you’re just not going to be able to create a barrier that the carriers can’t get through” (28:45).

On the exam

No past paper tests Lecture 23.

Paper	Part on Lecture 23	Sections
FN10, FN12, FN17, FN19; the midterms; the homework	none (a search for FinFET, SOI, floating body, soft error, gate-all-around, nanowire and fin finds no part)	—

What this chapter gives the tested chapters:

Number or idea	Where the exam uses it	This chapter
the subthreshold slope $S$S, given as 80–90 mV/decade	FN10-2, FN12-1, FN17-10, FN19-1, MT23-1b (Chapter 4 §11, Chapter 23 §15–§16)	§5: why those numbers are not 60
the body effect in a stack	Chapter 5 §1	§3
the leakage step $10^{\Delta V_T/S}$	Chapter 23 §12	§4

Memorize.

• 60 mV/decade, the ideal at room temperature; about 120 at 32 nm in bulk (this lecture) and about 100 at 22 nm (Lecture 4); FinFETs near 60.
• PD-SOI: a floating body (the history effect), with less S/D capacitance and less body effect in a stack.
• FD-SOI: no body; $V_T$ from the work function and the film’s thickness, tuned by a back gate.
• FinFET width in whole fins; drive proportional to the fin count.
• Contact-to-gate capacitance appears only in extraction, so a schematic simulation is optimistic.
• GAA gates every wire on all sides; source–drain tunnelling is the limit past it.

Derive (with the path).

• Decades of turn-off $= V_T/S$VT​/S: $\log_{10}I_D$ is linear in $V_{GS}$ with slope $1/S$1/S.
• A threshold shift’s leakage change $10^{\Delta V_T/S}$10ΔVT​/S: the same line, two thresholds.
• PD or FD: compare $t_{Si}$ with $W_{dmax} = \sqrt{2\kappa_s\varepsilon_0(2\phi_F)/(qN_A)}$2κs​ε0​(2ϕF​)/(qNA​)​.
• Fin width $W_{eff} = n_{fin}(2H + T)$T): the gated perimeter.

Method card. None: no question family.

This was the course’s last lecture. The final-exam review pages draw on the earlier chapters; this one is context for them.

The lecture’s boards

The boards of Lecture 23 not shown above (29 frames)

Lecture23 @ 00:42 Transistors ⇒, Scaling transistor; the bulk device begun (STI, STI)

Lecture23 @ 01:27 bulk CMOS: STI, n⁺, gate, n⁺, STI, p⁺ tap, p-substrate

Lecture23 @ 02:09 bulk CMOS, finished

Lecture23 @ 02:54 SOI (silicon-on-insulator), SOS (silicon-on-sapphire)

Lecture23 @ 06:48 rad-hard, soft errors; the soft-error track; the PD-SOI row on its BOX; SIMOX

Lecture23 @ 08:03 floating body effect added

Lecture23 @ 09:15 the PD-SOI row unoccluded

Lecture23 @ 10:34 − history effect, + reduced S/D capacitance; the stack begun

Lecture23 @ 11:33 the stack with its bodies; V_B beside the upper device

Lecture23 @ 12:18 the upper device boxed, V_B above 0

Lecture23 @ 13:31 FD-SOI begun; the stack wiped

Lecture23 @ 13:37 FD-SOI: the BOX lines and the n⁺ regions

Lecture23 @ 14:22 FD-SOI: the thin hatched film; ultra-thin-body begun

Lecture23 @ 15:24 the back gate, V_T control; ultra-thin-body devices

Lecture23 @ 17:23 subthreshold slope: 60 mV/decade

Lecture23 @ 17:48 32 nm ⇒ 120 mV/decade

Lecture23 @ 19:08 the FinFET top view; ⇓ 60 mV/decade

Lecture23 @ 20:14 the fin cross-section; Width quantized in number of fins; the layout begun

Lecture23 @ 21:00 the three-fin layout

Lecture23 @ 21:45 the side view begun: contacts beside the gate

Lecture23 @ 22:09 the side view with the contact-to-gate capacitors

Lecture23 @ 22:54 compact model ⇒ capacitance, extraction ⇒ others

Lecture23 @ 23:35 the capacitors ringed

Lecture23 @ 24:20 the compact model and extraction lines underlined

Lecture23 @ 24:50 7 nm written under the thin-body note

Lecture23 @ 25:35 7 nm ⇑ 5 nm; GAA transistors

Lecture23 @ 26:31 gate all around, nanowire transistors; the fin with its arch

Lecture23 @ 27:44 three stacked nanowires, gated on all sides

Lecture23 @ 28:59 the last board, nearly complete