F3. Past finals: path sizing

Every past final has a path-sizing question, and it is the same family as the midterms’ Question 5 (M4) and the domino sizing of MT24-5 (M6). This page re-solves the finals’ versions. They add two moves the midterms use less often: a limit on the input capacitance (FN17-7) and a limit on how far a gate may be skewed (FN19-8, FN10-9). Every number is re-solved and checked; none is copied from a key. Where a key disagrees, the folded note on the key at the end of the part explains why.

Question	Parts	Points	Chapters	The midterm twin
FN17-7 (2017)	input limit, a 500 fF branch	20 or 22 (of 250)	8	MT21-5 (M4 §2)
FN19-8 (2019)	delay, sizing within a β limit, a side branch	35 (of 250)	8, 11, 12	MT24-5b–c (M6 §1), MT23-5c
FN12-8 (2012)	delay, sizing	30 (of 200)	8, 12	solved in M6
FN10-9 (2010)	delay, sizing within a β limit	24 (of 200)	8, 11, 12	as FN19-8

FN17-7 is first because it is a purely static path, the midterms’ own problem. FN19-8, FN12-8 and FN10-9 put a dynamic gate at the head of the path. Within that family the newest exam comes first. FN19 has no answer key, so its solution here was worked out independently, and its parts have no note on a key.

Before you start

How to use this page. Each section restates one exam question with its source page (FN19-8b, p19 is the Fall 2019 final, question 8b, physical PDF page 19) and its points, and shows the exam’s own figure. FN17-7 is the static path-sizing family that M4’s approach section teaches; its parts say what this question adds. The path with a dynamic first stage is taught in full here, in the How to approach section before Section 2. Every part is worked the same way: what it asks, the idea behind the method, the solution in steps (each step gives its reason first), a check on the result, the answer, and one thing to remember. Try each part on your own first; open the Hint if you are stuck, and step through the solution before you press “Show all”.

The methods are all in the chapters:

a gate’s gain $g \cdot h$ from its normalized inverter (Chapter 8 §1), and the stack rule (Chapter 7 §8);
path delay $= \tau_{inv}\sum g_ih_i$ and path effort $F$ (Chapter 8 §2); equal gains $F^{1/N}$ , sized back from the load (§3, §6);
branching and retuning around a side load (§8, §9);
the logical effort of a dynamic stage, counted on the one edge it makes, footer included (Chapter 12 §1, §2);
skewed inverters and skewed static gates (Chapter 12 §4).

The conventions of each exam. Only gate capacitance counts (each exam says so or gives no other). Loads are written as microns of gate, $C/C_g$ .

Exam	$\tau_{inv}$	$C_g$	Device strengths	Loads in µm of gate
FN17-7	100 ps (given)	2 fF/µm	“the nFET has twice the on current of the pFET”: $R_p = 2R_n$	$Y$ : 100 fF = 50 µm; $C_B$ : 500 fF = 250 µm; input limit 2 fF = 1 µm
FN19-8	25 ps (the given FO1 delay)	1 fF/µm	not stated; $R_p = 2R_n$ assumed (see §2)	$E$ : 700 fF = 700 µm; side branch 200 fF = 200 µm
FN10-9	$3R_nC_g = 3 \times 4 \times 2 = 24$ ps	2 fF/µm	$R_n = 4$ , $R_p = 8\,\mathrm{k\Omega\cdot\mu m}$	$E$ : 700 fF = 350 µm

With $R_p = 2R_n$ the balanced inverter is 2W/W with input $3W$ ; $g_{NAND2} = 4/3$ , $g_{NOR2} = 5/3$ , $g_{OAI22} = 2$ . The FO1 delay of that inverter is $\tau_{inv} = 3R_nC_g$ (Chapter 7 §7).

1. FN17-7: an input limit and a 500 fF branch

The question (FN17-7, p17). The fan-out-of-one delay is $\tau_{inv} = 100$ ps and the gate capacitance is 2 fF/µm. “As always, assume that the nFET has twice the on current of the pFET at the same channel width.” The path runs from A through stage I (an OAI gate on A, B, C, D), stage II (a NOR), stage III (an inverter) and stage IV (a NAND) to Y, which drives 100 fF. A capacitor $C_B$ hangs on the NOR’s output.

The source circuit. Stage I: PFETs W2 in two series pairs (B over A, D over C) in parallel; NFETs W1, A parallel B in series with C parallel D. Stage II: a NOR with series PFETs W4 and parallel NFETs W3, one input from stage I. Capacitor CB on the NOR output, the node marked Cin. Stage III: an inverter, PFET W6 and NFET W5. Stage IV: a NAND with parallel PFETs W8 and series NFETs W7, output Y driving 100 fF. Handwritten by the key: 0.66 µm on each W2, 0.33 µm on each W1, the labels stage I to IV, Cin, and (50 µm) under the load. — FN17-7, p17 (source figure). The handwriting (0.33 and 0.66 µm, stage labels, C_in, “50 µm”) is the key’s.

Reading the circuit

Every part needs two numbers for each gate: the capacitance of one of its inputs (the load it puts on the stage before it) and its logical effort $g$ . No width is given, so you also balance each gate yourself, and that ties its two widths together. The strengths are unequal: “the nFET has twice the on current of the pFET” means $R_p = 2R_n$ , so a PFET must be twice as wide as an NFET to pull as hard, and the balanced inverter is 2W/W, with input $3W$ .

Reading FN17-7 gate by gate

Stage I, the OAI22, $\overline{(A+B)(C+D)}$ . When one input switches, the output falls through two NFETs in series ( $W_1$ each: A or B, then C or D) and rises through two PFETs in series ( $W_2$ each). Two equal devices in series act like one of half the width, so the gate is balanced when its PFETs are twice its NFETs, $W_2 = 2W_1$ . It then drives like a $W_2/2$ over $W_1/2$ inverter, whose input is $1.5W_1$ . One input drives one NFET and one PFET, $W_1 + W_2 = 3W_1$ , so $g = 3W_1/1.5W_1 = 2$ .
Stage II, the NOR2. One NFET ( $W_3$ ) pulls down alone, because in the worst case only one input switches. The two PFETs ( $W_4$ ) are in series and act like $W_4/2$ , which must be twice $W_3$ to balance: $W_4 = 4W_3$ . The normalized inverter is $2W_3$ over $W_3$ , input $3W_3$ ; one input drives $W_3 + W_4 = 5W_3$ , so $g = 5/3$ .
Stage III, the inverter. Because $R_p = 2R_n$ , its PFET must be twice as wide as its NFET to pull as hard, so it is balanced at $W_6 = 2W_5$ : input $3W_5$ , $g = 1$ .
Stage IV, the NAND2. The two NFETs ( $W_7$ ) in series act like $W_7/2$ ; one PFET ( $W_8$ ) pulls up alone and must be twice that, so $W_8 = W_7$ . The normalized inverter’s input is $3 \times W_7/2 = 1.5W_7$ ; one input drives $W_7 + W_8 = 2W_7$ , so $g = 4/3$ .
The loads, in µm of gate, because every gain is a ratio of gate widths. At 2 fF/µm, Y’s 100 fF is 50 µm, the 2 fF input limit is 1 µm, and $C_B = 500$ fF is 250 µm. $C_B$ hangs on the wire from the NOR’s output to the inverter’s input: the load of stage II.

Stage	Gate	Balanced widths ( $R_p = 2R_n$ )	One input	$g$
I	OAI22, $\overline{(A+B)(C+D)}$	stacks of two both ways: NFETs act as $W_1/2$ , PFETs as $W_2/2$ ; balanced when $W_2 = 2W_1$	$W_1 + W_2 = 3W_1$	$3W_1/1.5W_1 = 2$
II	NOR2	NFETs $W_3$ alone (worst case); PFETs in series act as $W_4/2 = 2W_3$ , so $W_4 = 4W_3$	$5W_3$	5/3
III	inverter	$W_6 = 2W_5$	$3W_5$	1
IV	NAND2	NFETs in series act as $W_7/2$ ; one PFET $W_8 = 2(W_7/2) = W_7$	$2W_7$	4/3

The edges. Every gate inverts, so the edges alternate. With C or D at 1, B at 0, the NOR’s other input at 0 and the NAND’s other input at 1: A rises, the OAI output falls, the NOR output rises, the inverter output falls, and Y rises. “A falling to Y falling” is the mirror case; every gate is balanced, so its gains are the same and one sum serves both. This is MT21-5’s circuit, with $R_p = 2R_n$ in place of equal strengths (M4 §2).

FN17-7a: the input limit (8 or 10 points)

FN17-7a, p17. Let $C_B = 0$ , and let the input capacitance of each of A, B, C and D be limited to 2 fF. Find the sizing that gives minimum delay from A rising to Y rising (or A falling to Y falling). (The point value is overwritten in the source: 8 or 10.)

Hint

The first gate has no width, only a cap on its input. As that input grows, which way does the path effort move?

What it asks. Choose all eight widths for the fastest path from A to Y, with no branch yet ( $C_B = 0$ ), when each input may present at most 2 fF. The words “limited to 2 fF” take the place of a fixed first gate: they are what stops you making every gate huge and pushing the delay onto whatever drives A.

The idea. This is MT21-5a, which M4 works in full, with the moves of M4’s path-sizing section. The new point is the strength convention. With $R_p = 2R_n$ every PFET doubles, so the NOR’s $g$ is $5/3$ and the NAND’s $4/3$ , where MT21-5 has $3/2$ for both, and $G = 2 \cdot \tfrac53 \cdot 1 \cdot \tfrac43 = 40/9 = 4.44$ against MT21-5’s 4.5. The rest is the same. With nothing branching off the path, the product of the four gains is the path effort (Chapter 8, Section 2):

F = G \cdot H, \qquad G = \prod g_i, \qquad H = \frac{C_{load}}{C_{in}}

$G$ is the cost of the gate types and $H$ the load over the path’s input capacitance; $F$ doesn’t depend on the inner widths, because each one is the load of one stage and the size of the next, and cancels. A sum of factors with a fixed product is smallest when the factors are equal: making one stage faster forces another to be slower by a larger factor. So every stage takes $f = F^{1/4}$ (Chapter 8, Section 3).

FN17-7a

Use the whole input limit. $H = 50\,\mu\mathrm{m}/C_{in}$ falls as the input grows, so a larger input means a smaller $F$ and a faster path. Take A’s input at 2 fF = 1 µm: $W_1 + W_2 = 1$ with $W_2 = 2W_1$ , which gives $W_1 = 0.33\,\mu$ m and $W_2 = 0.67\,\mu$ m.
The path effort, because it sets the stage gain: $G = 2 \cdot \tfrac53 \cdot 1 \cdot \tfrac43 = \tfrac{40}{9} = 4.44$ , and $F = 4.44 \times 50/1 = 222.2$ .
Equal gains. Four stages share it equally: $f = \sqrt[4]{222.2} = 3.861$ .
Size back from the load (Chapter 8 §6), because the load is the one capacitance known at the end. Write each gain as $g \cdot C_{out}/C_{in}$ , with $C_{in}$ the stage’s one-input capacitance. NAND: $\tfrac43 \cdot 50/C_{IV} = f$ gives $C_{IV} = 17.27\,\mu$ m, so $W_7 = W_8 = 8.63\,\mu$ m.
Inverter. It drives the NAND’s input: $17.27/C_{III} = f$ gives $C_{III} = 4.47\,\mu$ m, so $W_5 = 1.49\,\mu$ m and $W_6 = 2.98\,\mu$ m.
NOR. It drives the inverter’s input: $\tfrac53 \cdot 4.47/C_{II} = f$ gives $C_{II} = 1.93\,\mu$ m, so $W_3 = 0.386\,\mu$ m and $W_4 = 1.54\,\mu$ m.
Stage I checks the work. Its gain isn’t chosen, but the four gains multiply to $F = f^4$ , so it must come out at $f$ : $2 \times 1.93/1 = 3.86$ . ✓
The delay. Four stages at $f$ each: $4f\,\tau_{inv} = 15.44 \times 100\,\mathrm{ps} = 1.54$ ns.

Check. Use only half the limit, 1 fF: $H$ and $F$ double, to 444.4, and the delay becomes $4\sqrt[4]{444.4} = 18.4\,\tau_{inv}$ , 19% slower. The delay grows as $H^{1/4}$ , so the whole limit is worth taking, and it is the only thing that sets the first gate’s size.

Answer: $W_1 = 0.33$ , $W_2 = 0.67$ , $W_3 = 0.39$ , $W_4 = 1.54$ , $W_5 = 1.49$ , $W_6 = 2.98$ , $W_7 = W_8 = 8.63\,\mu$ m; delay $15.4\,\tau_{inv} \approx 1.54$ ns. Using the whole input limit is the same step as MT21-5a.

Remember. A cap on the input makes $H$ smallest when you use all of it; then size back from the load. When the strength convention changes, rework every $g$ first: the method is MT21-5’s, the numbers are not.

The answer key agrees

It gives the same sizes ( $W_4 = 1.55$ from its rounded 4.5 µm), and no delay.

FN17-7b: a 500 fF branch (12 points)

FN17-7b, p18. Now $C_B = 500$ fF. Find a sizing that gives you close to the minimum delay for this path from A rising to Y rising (or A falling to Y falling).

Hint

At (a)‘s sizes, which stage does the 250 µm overload, and what stays fixed if only that stage and the one before it change?

What it asks. Hang 500 fF on the NOR’s output and resize for a delay close to the minimum. A’s input stays at the 2 fF limit, so $W_1$ and $W_2$ stay. “Close to the minimum” means that a sensible retuning, explained, is enough.

The idea. This is MT21-5b’s dominant branch (M4), with this exam’s gains. The branch is 250 µm of gate. It doesn’t grow when the gates after it grow, so the path effort is no longer fixed (Chapter 8 §8), and $F^{1/4}$ is no longer the answer. But equal gains still hold on any piece of the path with nothing branching off it. Retune by inspection, as the lecture does (Chapter 8 §9), in two moves:

Rebalance first. The branch is 98% of the NOR’s load, so at (a)‘s sizes the NOR’s gain jumps to 219.7 while the OAI’s stays at 3.86. The lecture’s example enlarges the gate after the branch first, but its branch driver was already sized for the branch. Here, enlarging the inverter first (to a 17.5 µm input) would add to that huge gain, and the delay would rise from $231.3$ to $239.7\,\tau_{inv}$ .
Then enlarge the gate after the branch: here it pays. Split the path at the branch added. Because the branch dominates, a larger inverter adds little to the NOR’s load and makes the last two stages much cheaper. The best size is where those two changes match.

FN17-7b

See what the branch does at (a)‘s sizes. A side load adds only to the stage that drives its node, so only the NOR’s gain changes. It now drives $4.47 + 250 = 254.47\,\mu$ m from its 1.93 µm input: gain $\tfrac53 \times 254.47/1.93 = 219.7$ . Delay $= 3(3.861) + 219.7 = 231.3\,\tau_{inv} = 23.1$ ns.
Rebalance the pair before the branch. A’s input is fixed and nothing branches between the OAI and the NOR, so while only the NOR moves, the product of their two gains stays at $2 \cdot \tfrac53 \cdot 254.47 = 848.2$ . Equal factors give the smallest sum: $\sqrt{848.2} = 29.12$ each. The NOR’s input becomes $\tfrac53 \times 254.47/29.12 = 14.56\,\mu$ m ( $W_3 = 2.91$ , $W_4 = 11.65\,\mu$ m).
The delay now: $2(29.12) + 2(3.861) = 65.97\,\tau_{inv} = 6.60$ ns, already a factor of 3.5 better.
Split the path at the branch, because each side then has nothing branching off it. Call the inverter’s input $C_{in}$ (µm), as the key does. Stages I and II share the product $\tfrac{10}{3}(250 + C_{in})$ ; stages III and IV share $\tfrac43 \cdot 50/C_{in} = \tfrac{200}{3C_{in}}$ .
The delay for a chosen $C_{in}$ . A balanced pair with product $P$ contributes $2\sqrt{P}$ , so the delay is $2\sqrt{\tfrac{10}{3}(250 + C_{in})} + 2\sqrt{\tfrac{200}{3C_{in}}}$ (in $\tau_{inv}$ ).
Try a few widths. Growing $C_{in}$ raises the first term slowly and lowers the second fast, until the two changes match. $C_{in} = 4.47$ : 65.97. $C_{in} = 10$ : 64.04. $C_{in} = 17.5$ : 63.63. $C_{in} = 30$ : 64.08. Take $C_{in} = 17.5\,\mu$ m.
Stages III and IV, balanced: $\sqrt{200/(3 \times 17.5)} = 1.952$ each. The NAND’s input is $\tfrac43 \times 50/1.952 = 34.15\,\mu$ m, so $W_7 = W_8 = 17.1\,\mu$ m. The inverter: $W_5 = 17.5/3 = 5.83$ , $W_6 = 11.66\,\mu$ m.
Stages I and II, balanced: $\sqrt{\tfrac{10}{3} \times 267.5} = 29.86$ each. The NOR’s input is $\tfrac53 \times 267.5/29.86 = 14.93\,\mu$ m, so $W_3 = 2.99$ and $W_4 = 11.94\,\mu$ m. $W_1$ and $W_2$ stay at 0.33 and 0.67 µm.
The delay: $2(29.86) + 2(1.952) = 63.63\,\tau_{inv} = 6.36$ ns.

The exact minimum added. Setting the derivative of step 5’s expression to zero gives $C_{in}^3 = 20(C_{in} + 250)$ , that is $C_{in}^3 - 20C_{in} - 5000 = 0$ , whose real root is $C_{in} = 17.49\,\mu$ m. That is the key’s method. It is added calculus: the lecture says the retuning can be done exactly, but usually “you just sort of look at it” (L08 52:20–53:19). Trying three or four widths, as in step 6, finds the same minimum to within 0.01%.

Check. A floor. Whatever the sizes, the pair before the branch must carry a product of at least $\tfrac{10}{3} \times 250 = 833.3$ , so it costs at least $2\sqrt{833.3} = 57.7\,\tau_{inv}$ . No sizing reaches that, because the stages after the branch would have to cost nothing; 63.63 is about 10% above it.

Answer: $W_3 \approx 3.0$ , $W_4 \approx 11.9$ , $W_5 \approx 5.8$ , $W_6 \approx 11.7$ , $W_7 = W_8 \approx 17.1\,\mu$ m (with $W_1$ , $W_2$ as in (a)); delay $63.6\,\tau_{inv} \approx 6.36$ ns. Step 2 alone (6.60 ns) is already close to the minimum. Most of what remains is the cost of driving 250 µm from a 1 µm input, which no sizing removes.

Remember. With a heavy branch, first share the overloaded stage’s gain with the stage before it; then enlarge the gate after the branch. The larger the branch’s share of the load, the more the first move does and the more the second one buys.

The answer key differs

It says that at (a)‘s sizes stage II’s gain is 212 and the delay $223\,\tau_{inv}$ . The gain is 219.7 and the delay $231.3\,\tau_{inv}$ (the key’s 212 is read from the transcription; the page scan is not in the sources). After that its minimization is right: $C_{in} = 17.5\,\mu$ m, gains 29.9 and 1.95, $W_7 = W_8 = 17.1$ , $W_5 = 5.8$ , $W_6 = 11.6$ , $W_3 = 3.0$ , $W_4 = 12\,\mu$ m and $63.7\,\tau_{inv}$ (63.6 unrounded). Two slips in its working don’t change the result: one line writes $\tfrac{10}{3}(250 - C_{in})$ where the lines around it have $+$ , and the $W_5$ line’s denominator reads $(.95)(3)$ , where its own 5.8 µm needs 1.95.

The widget below does steps 4–6 for any inverter size. Slide the input of the inverter after the branch; the red point is (a)‘s sizing with the branch added, and the green point the lowest delay.

input of the inverter after the branch4.5 µm

delay Σ gains: 65.97 τ_inv = 6.597 ns
gains, stage 1 to 4: 29.12 · 29.12 · 3.86 · 3.86
branching factor at stage 2: 56.90
(a) sizes with C_B: sizes of (a): 231.28 τ_inv (off the chart)
lowest point: 63.63 τ_inv at 17.5 µm
NOR2: W₃ (W₄ = 4W₃): 2.91 µm
inverter: W₅ (W₆ = 2W₅): 1.49 µm
NAND2: W₇ = W₈: 8.63 µm

How to approach a path with a dynamic first stage

Recognize it by a clocked gate at the head of a path: a PFET on $\phi$ from $V_{DD}$ to a node, an NFET network below it over a footer on $\phi$ , then an inverter and static NANDs (or a second dynamic stage), every width labelled $W_1, W_2, \dots$ , and a large capacitor at the end. The phrases: “in the evaluate phase ( $\phi = 1$ )”, “keeping $W_1$ fixed”, “do not let the beta ratio … become more than 4 or less than 0.25”, and sometimes a side branch. Three finals asked it: FN19-8 for 35 points (of 250), FN12-8 for 30 and FN10-9 for 24 (of 200). The parts come in a static path’s order (M4’s path-sizing section): the delay as drawn, then the sizes for the least delay, then a side load at fixed sizes.

The moves, in order.

Mark the edges in evaluate. The precharged node can only fall, and every stage after it inverts, so the edges alternate: X falls, C rises, D falls, E rises. Check that the edge pair the question names is one the path can make.
Take each stage’s $g$ on its own edge. For the dynamic stage, count every device from the node to ground, footer included, and ignore the precharge PFET: it is off during evaluate (M6’s dynamic-logic section). For a static gate, only the network that makes its edge counts.
State the strength convention, because it sets $\tau_{inv}$ and every $g$ . FN10 and FN12 give $R_p = 2R_n$ ; FN19 doesn’t, so write down the one you use and why.
Skew each static gate toward its edge, to the limit. Each makes only one edge in evaluate; its other network only resets the node in precharge. Shrink that network until the β limit stops you: the input gets smaller while the edge that matters keeps its strength, so $g$ falls.
Size for equal gains. With $W_1$ fixed and nothing branching off, $F = GH$ is fixed: take $f = F^{1/N}$ , size back from the load, and let stage I come out at $f$ as a check (M4’s path-sizing section).
A side branch at fixed sizes changes one gain: that of the stage that drives its node.

Why these formulas.

Gain and path delay. In the course’s $(R/W)\,C$ model, with gate capacitance only, each stage takes $\tau_{inv}$ times its gain $g \cdot h$ . Here $h$ is the gate it drives over its own input, and $g$ its input over the input of the balanced inverter that pulls as hard on the same edge. The path delay is $\tau_{inv}\sum g_ih_i$ (Chapter 8, Section 2). A static gate’s input drives an NFET and a PFET; that is the cost $g$ measures.
The dynamic stage. Its input drives one NFET and no PFET. Its evaluate path is the input and the footer in series: two 1 µm devices act as one of 0.5 µm. With $R_p = 2R_n$ the balanced inverter with that pull-down is 1 µm over 0.5 µm, input 1.5 µm, so $g = 1/1.5 = 2/3$ , the lecture’s board value (Chapter 12, Section 2). In general added a $k$ -high stack of equal devices has $g = k/3$ with $R_p = 2R_n$ and $k/2$ at equal strengths (the general rule).
A skewed gate added. The same definition, on the edge that matters: its input over the balanced inverter with the same strength on that edge (Chapter 12, Section 4). A NAND2 with NFETs $W$ and PFETs $W/4$ , falling: the stack acts as $W/2$ , the balanced inverter’s input is $1.5W$ , the NAND’s own input $1.25W$ , so $g = 0.833$ instead of $4/3$ .
The β ratio compares strengths, not widths. With $R_p = 2R_n$ a PFET is as strong as an NFET of half its width. So the $8W/W$ inverter is at $\beta = (8W/2)/W = 4$ , and a NAND2 with PFETs $W/4$ over two series NFETs $W$ is at $(W/8)/(W/2) = 1/4$ .

Decisions to make on the way. The strength convention, with a reason when the exam leaves it out. Which edge each static gate makes, and so which way to skew it. Which node a side load hangs on.

Traps. An edge pair the path can’t make (a dynamic node never rises in evaluate). Leaving out the footer, or counting the precharge PFET. Reading β as a width ratio, which puts the 8:1 inverter over the limit. Skewing a gate toward the edge it doesn’t make. The units of a load: 700 fF is 700 µm at 1 fF/µm but 350 µm at 2 fF/µm. Treating $F$ as fixed after a side load is added.

2. FN19-8: a dynamic gate, a skewed inverter and two NANDs

The question (FN19-8, p18). A path from a dynamic gate through, in the exam’s words, “two static gates”; the figure has three, a skewed inverter and two NAND2s. The gate capacitance is 1 fF/µm, and the FO1 delay of the technology is $\tau_1 = 25$ ps. Node E drives 700 fF, and a capacitor $C_{sidebranch}$ hangs on node D.

The source circuit. A dynamic gate: a PFET on phi from VDD to an unnamed dynamic node; NFETs A and B (W1) in parallel below it, over a footer NFET on phi (W1). The dynamic node drives an inverter with PFET 8W2 and NFET W2, output C. C drives one input of a NAND2 with parallel PFETs W4 and series NFETs W3, output D; the NAND's other input is an unconnected stub. D carries the capacitor Csidebranch to ground and drives one input of a second NAND2 with parallel PFETs W5 and series NFETs W6, output E, whose other input is also a stub. E drives 700 fF. — FN19-8, p18 (source figure). The dynamic node is unnamed; this page calls it X. C_sidebranch hangs on D.

Reading the circuit

Every part needs each stage’s edge and its $g$ on that edge, so find them once, in the order of the moves above. Start with the strengths, because every $g$ depends on them.

The strength convention. FN19 doesn’t say how strong a PFET is. Take $R_p = 2R_n$ , the course’s usual convention and the one FN10-9 states for this same circuit. Two things in the problem support it. The given inverter’s strength ratio is then $(8W_2/2)/W_2 = 4$ , exactly the limit part (b) sets. And the given FO1 delay is then $\tau_{inv} = 3R_nC_g = 25$ ps. With equal strengths the 8:1 inverter would already break (b)‘s limit.

Reading FN19-8 stage by stage

The inputs that hold the path open. B is at 0, so A’s NFET alone pulls X down; each NAND’s other input (drawn as a stub) is at 1, so each NAND passes the path’s signal on, inverted.
The edges, because each stage’s $g$ is taken on its edge. In evaluate ( $\phi = 1$ ) the precharged node can only fall, so A rising makes X fall. Each later stage inverts: C rises, D falls, E rises. These are exactly the edges the question asks about: “A rising to E rising” is an edge pair this path makes (Chapter 12 §1).
Stage I, the footed dynamic OR. X falls through A’s NFET and the footer in series, two $W_1$ devices that act as one of $W_1/2$ . The balanced inverter with that pull-down has a $W_1$ PFET, input $1.5W_1$ . A drives one NFET and no PFET, $W_1$ : $g = 1/1.5 = 2/3$ (Chapter 12 §2). The precharge PFET is off during evaluate and plays no part (its width isn’t even given).
Stage II, the inverter $8W_2/W_2$ , rising. Only its PFET makes C rise. The balanced inverter with an $8W_2$ PFET has a $4W_2$ NFET, input $12W_2$ ; the real input is $8W_2 + W_2 = 9W_2$ : $g = 9/12 = 3/4$ added.
Stage III, a NAND2, falling. D falls through the two $W_3$ NFETs in series, which act as $W_3/2$ ; the balanced inverter with that pull-down has input $1.5W_3$ . One input drives one NFET and one PFET, $W_3 + W_4$ . At 1 µm, $g = 2/1.5 = 4/3$ .
Stage IV, a NAND2, rising. E rises through one $W_5$ PFET, as strong as a $W_5/2$ NFET; the balanced inverter has input $1.5W_5$ . One input drives $W_5 + W_6$ . At 1 µm, $g = 4/3$ .
The loads, in µm of gate, because every gain is a ratio of gate widths: at 1 fF/µm, E’s 700 fF is 700 µm, and the side branch’s 200 fF is 200 µm, on D.

Stage	Gate	Edge	What pulls it	Balanced inverter with that strength	Input	$g$ (all 1 µm)
I	dynamic OR, footed	X falls	A’s NFET over the footer: like one $W_1/2$	NFET $W_1/2$ , PFET $W_1$ : $1.5W_1$	$W_1$	2/3
II	inverter $8W_2/W_2$	C rises	the $8W_2$ PFET	PFET $8W_2$ , NFET $4W_2$ : $12W_2$	$9W_2$	3/4
III	NAND2 (PFETs $W_4$ , NFETs $W_3$ )	D falls	two $W_3$ in series: $W_3/2$	$1.5W_3$	$W_3 + W_4$	4/3
IV	NAND2 (PFETs $W_5$ , NFETs $W_6$ )	E rises	one $W_5$	$1.5W_5$	$W_5 + W_6$	4/3

FN19-8a: the delay as drawn (10 points)

FN19-8a, p18. Estimate the delay from A rising to E rising in the evaluate phase ( $\phi = 1$ ) if $W_1 = \dots = W_6 = 1\,\mu$ m. Let $C_{sidebranch} = 0$ .

Hint

With the edges and the

g

s in the table, what does each stage drive, and what is its own input?

What it asks. The delay from A rising to E rising in evaluate, with every width at 1 µm and no side branch, in units of the 25 ps FO1 delay and then in ns. Nothing is sized yet: this is the path as drawn.

The idea. Each stage takes $\tau_{inv}$ times its gain $g \cdot h$ , with $g$ from the table, on the stage’s own edge, and $h$ the gate it drives over its own input. The stages switch one after another, so the delays add (Chapter 8, Section 2). What is new against a static path is only the $g$ s: a dynamic input that carries no PFET (2/3), and gates whose edge the clock fixes, so only the network that makes that edge counts. The tempting slip is to give the 8:1 inverter a balanced inverter’s $g = 1$ , or its falling edge’s 3: only C rising is on the path.

FN19-8a

Stage I. X drives the whole input of the inverter, both of its gates, $8 + 1 = 9\,\mu$ m, from A’s 1 µm: $h = 9$ , gain $\tfrac23 \times 9 = 6$ .
Stage II. C drives one NAND input, its NFET and its PFET, $1 + 1 = 2\,\mu$ m, from 9 µm: gain $\tfrac34 \times \tfrac29 = 0.167$ . A large gate driving a small one is fast, but its size is wasted.
Stage III. D drives the next NAND’s 2 µm from 2 µm: gain $\tfrac43 \times 1 = 1.333$ .
Stage IV. E drives the 700 µm load from 2 µm: gain $\tfrac43 \times 350 = 466.7$ .
Add the gains. Delay $= (6 + 0.167 + 1.333 + 466.7) \times 25\,\mathrm{ps} = 474.17 \times 25\,\mathrm{ps} = 11.85$ ns.

Check. The big term by $(R/W)C$ : the one 1 µm PFET has resistance $2R_n$ and drives 700 fF, and $2R_n \times 700\,\mathrm{fF}$ over $\tau_{inv} = 3R_n \times 1\,\mathrm{fF}$ is $1400/3 = 466.7$ . ✓ The two routes agree, because logical effort is the same model in other units.

Answer: $474.2\,\tau_{inv} \approx 11.9$ ns. The last NAND, driving 700 fF through one 1 µm PFET, is 98% of it.

Remember. Mark the edges, then take each $g$ on its own edge: a dynamic input carries no PFET, and a skewed inverter counts only its strong device. The rest is a static path’s sum of gains.

FN19-8b: sizing within the β limit (15 points)

FN19-8b, p19. Keeping $W_1$ fixed at 1 µm, resize the network to minimize the delay from A rising to E rising with $C_{sidebranch} = 0$ . Do not let the beta ratio (the ratio of pFET strength to nFET strength) of any gate become more than 4 or less than 0.25.

Hint

Each NAND makes only one edge in evaluate: what does its other network do for the delay, and what does it cost the stage before it?

What it asks. Choose $W_2$ to $W_6$ for the least delay from A rising to E rising, with no side branch, while every gate’s β (PFET strength over NFET strength) stays between 1/4 and 4. Two phrases decide the method. “Keeping $W_1$ fixed” fixes the path’s input, so the path effort is fixed. The β limit allows the gates to be skewed, and says how far.

The idea. Two moves, in this order.

Lower $G$ by skewing. Each static gate after the dynamic stage makes only one edge during evaluate; the network that makes the other edge only resets the node during precharge (Chapter 12 §4; L12 06:58 and 09:02). Shrinking that network lowers the gate’s input capacitance and leaves the edge that matters as strong as before, so its $g$ on that edge falls. Nothing in the model pays for it added: the model counts only gate capacitance, and the reset edge isn’t timed. So go to the limit.
Then size for equal gains. With $W_1$ fixed and nothing branching off, $F = GH$ doesn’t depend on the widths, and a sum with a fixed product is smallest when its factors are equal: every stage takes $f = F^{1/4}$ , and no stage can be made faster without slowing another by more (Chapter 8 §3).

FN19-8b

Read each gate’s β, because the limit is on strength, not width. With $R_p = 2R_n$ a PFET is as strong as an NFET of half its width. Stage II: $(8W_2/2)/W_2 = 4$ , already at the limit, so it stays 8:1. Stage III: PFET $W_4/2$ against the NFET stack’s $W_3/2$ , so $\beta = W_4/W_3$ . Stage IV: $\beta = W_5/W_6$ .
Skew III toward its NFETs, because D falls: the smallest allowed $\beta$ is 1/4, so $W_4 = W_3/4$ . Its input is $1.25W_3$ against the balanced inverter’s $1.5W_3$ : $g = 1.25/1.5 = 0.833$ , down from 4/3.
Skew IV toward its PFETs, because E rises: the largest allowed $\beta$ is 4, so $W_6 = W_5/4$ . Again $g = 1.25/1.5 = 0.833$ .
The path effort, because it sets the stage gain. With $W_1$ fixed, A’s input is 1 µm and the load 700 µm: $H = 700$ . $G = \tfrac23 \cdot \tfrac34 \cdot \tfrac56 \cdot \tfrac56 = 0.347$ , and $F = 0.347 \times 700 = 243.1$ . Nothing branches off and every gate keeps its proportions, so $F$ doesn’t depend on the widths and equal gains are the minimum.
Equal gains: $f = \sqrt[4]{243.1} = 3.948$ .
Size back from the load, because its equation has only one unknown. IV: $700/(1.5W_5) = f$ gives $W_5 = 118.2\,\mu$ m and $W_6 = 29.5\,\mu$ m (D drives $1.25W_5 = 147.7\,\mu$ m).
III drives that 147.7 µm: $147.7/(1.5W_3) = f$ gives $W_3 = 24.9\,\mu$ m and $W_4 = 6.24\,\mu$ m (C drives $1.25W_3 = 31.2\,\mu$ m).
II drives that 31.2 µm: $\tfrac34 \times 31.2/(9W_2) = f$ gives $W_2 = 0.658\,\mu$ m: the PFET is $8W_2 = 5.26\,\mu$ m and the NFET 0.658 µm.
Stage I checks the work. Its gain isn’t chosen, but the four gains multiply to $f^4$ : $\tfrac23 \times 9 \times 0.658 = 3.948 = f$ . ✓
The delay. Four stages at $f$ : $4f\,\tau_{inv} = 15.79 \times 25\,\mathrm{ps} = 395$ ps.

Check. The last stage by $(R/W)C$ : the 118.2 µm PFET has resistance $2R_n/118.2$ and drives 700 fF, which in units of $\tau_{inv} = 3R_nC_g$ is $1400/(3 \times 118.2) = 3.948$ , the same $f$ . ✓

Answer: $W_2 = 0.66$ (PFET 5.26), $W_3 = 24.9$ , $W_4 = 6.24$ , $W_5 = 118$ , $W_6 = 29.5\,\mu$ m; delay $15.8\,\tau_{inv} \approx 395$ ps, down from 11.9 ns. Without the skew (NANDs at $\beta = 1$ ), $F = 622$ and the best is $20.0\,\tau_{inv} = 499$ ps: the β limit is worth about a fifth of the delay.

Remember. After a dynamic stage, skew every static gate toward the edge it makes, to the β limit. Then the path is a static one with a smaller $G$ : equal gains, sized back from the load.

FN19-8c: the side branch (10 points)

FN19-8c, p20. Using the sizing of (b), what is the delay from A rising to E rising with $C_{sidebranch} = 200$ fF?

Hint

Which stage’s output is node D, and what changes for the other three stages?

What it asks. Keep the sizes of (b), hang 200 fF on D, and find the new delay. No retuning is asked.

The idea. A side load is extra capacitance on one node, and each node is driven by exactly one stage. So it raises that one stage’s load, and with it that stage’s gain. Every other stage drives what it drove before, at the same size, so its gain doesn’t change. This is MT23-5c’s move (M4); here the node is D, the output of the skewed NAND III.

FN19-8c

Find the node, because it names the one stage that changes. The capacitor hangs on D, the output of stage III. At 1 fF/µm it is 200 µm.
Add it to stage III’s load. Stage III now drives $147.7 + 200 = 347.7\,\mu$ m from the same pull-down, whose balanced inverter’s input is $1.5 \times 24.94 = 37.42\,\mu$ m: gain $347.7/37.42 = 9.29$ , up from 3.95.
The other three gains stay at 3.948, because their loads and their sizes haven’t changed.
The delay: $3(3.948) + 9.29 = 21.14\,\tau_{inv} = 528$ ps.

Check. The delay rose by $21.14 - 15.79 = 5.35\,\tau_{inv}$ , exactly the rise in stage III’s gain, from 3.95 to 9.29: nothing else moved.

Answer: $21.1\,\tau_{inv} \approx 528$ ps. The branching factor at D is $347.7/147.7 = 2.35$ . The question doesn’t ask for retuning. If it did, the moves of FN17-7b would apply. Resizing all three free widths reaches $19.4\,\tau_{inv} = 486$ ps, with the last NAND larger ( $W_5 \approx 166\,\mu$ m): try it in the widget of Section 5.

Remember. At fixed sizes, a side load changes one gain: that of the stage driving its node. Find the node first.

3. FN12-8: a domino path (solved in M6)

FN12-8 (Fall 2012 final, p12–13, 30 points) asks for the evaluation delay from A to G of a domino path (a footed dynamic OR, a $4W_2/W_2$ inverter, a three-high dynamic stage and a $4W_4/W_4$ inverter driving 500 fF, with $R_n = 4$ , $R_p = 8\,\mathrm{k\Omega\cdot\mu m}$ and 2 fF/µm) with all widths 1 µm, and for the sizes that minimize it with $W_1$ fixed. M6 §4 solves it in full, as an extra drill.

Answer: (a) $50.17\,\tau_{inv} = 1.20$ ns; (b) $F = 115.7$ , $f = 3.28$ , $W_2 \approx 1.0$ , $W_3 \approx 19.4$ , $W_4 \approx 12.7\,\mu$ m, about 315 ps.

The answer key differs

It adds its gains to 50.76 and multiplies them to 128.94; its method is right.

4. FN10-9: the same path in 2010

The question (FN10-9, p15). The same circuit as FN19-8, with no side branch. The gate capacitance is 2 fF/µm; the unit-width nFET resistance is 4 kΩ and the pFET’s 8 kΩ (that is, kΩ·µm). Ignore diffusion and overlap capacitance. E drives 700 fF.

The same dynamic-to-static path as FN19-8: a footed dynamic gate with inputs A and B (W1), an inverter 8W2/W2 to C, a NAND2 with PFETs W4 and NFETs W3 to D, a NAND2 with PFETs W5 and NFETs W6 to E, and 700 fF on E; no side branch. Handwritten by the key: tau_inv = 4000 times 3 times 2e-15 = 24 psec; g = 2/1.5 = 1.33 at stages III and IV; arrows down at stage I and III, up at II and IV; braces labelled I to IV. — FN10-9, p15 (source figure). The handwriting (τ_inv = 24 ps, the g values, the arrows and stage labels) is the key’s.

$\tau_{inv} = 3R_nC_g = 3 \times 4 \times 2 = 24$ ps, because the FO1 delay of the 2W/W inverter is its NFET’s $R_n/W$ driving its own $3W$ of gate. The load is $700/2 = 350\,\mu$ m, because gains are ratios of gate widths. Here $R_p = 2R_n$ is given, so nothing is assumed, and the edges and the logical efforts are those of the table in Section 2: X falls, C rises, D falls, E rises.

FN10-9a: the delay as drawn (10 points)

FN10-9a, p15. Estimate the delay from A rising to E rising in the evaluate phase ( $\phi = 1$ ) if $W_1 = \dots = W_6 = 1\,\mu$ m.

Hint

The circuit, the edges and the

g

s are FN19-8’s. Which numbers do the 2 fF/µm and the two resistances change?

What it asks. The delay from A rising to E rising in evaluate, with every width at 1 µm, in ns. It is FN19-8a in other units.

The idea. Same path and the same moves as FN19-8a: each stage takes $\tau_{inv}$ times its gain $g \cdot h$ , with $g$ on its own edge, and the gains add. What is different is the units. The strengths are given ( $R_p = 2R_n$ , so nothing is assumed), $\tau_{inv}$ is not given but follows from $3R_nC_g = 24$ ps, and at 2 fF/µm the 700 fF load is only 350 µm of gate, half of FN19-8’s.

FN10-9a

Stage IV. E drives the 350 µm load from one NAND input, 2 µm, with $g = 4/3$ on its rising edge: $\tfrac43 \times 350/2 = 233.3$ .
Stage III. D drives the next NAND’s 2 µm from 2 µm: $\tfrac43 \times 2/2 = 1.33$ .
Stage II. C drives 2 µm from the inverter’s 9 µm, with $g = 3/4$ on its rising edge: $\tfrac34 \times 2/9 = 0.167$ .
Stage I. X drives the inverter’s 9 µm from A’s 1 µm, with $g = 2/3$ : $\tfrac23 \times 9 = 6$ .
Add the gains. Delay $= (233.3 + 1.33 + 0.167 + 6) \times 24\,\mathrm{ps} = 240.83 \times 24\,\mathrm{ps} = 5.78$ ns.

Check. Both ends by $(R/W)C$ . Stage IV: one 1 µm PFET is 8 kΩ, and $8\,\mathrm{k\Omega} \times 700\,\mathrm{fF} = 5.6$ ns $= 233.3 \times 24$ ps. ✓ Stage I: the two 1 µm NFETs in series are 8 kΩ, driving 9 µm × 2 fF/µm = 18 fF: $8\,\mathrm{k\Omega} \times 18\,\mathrm{fF} = 144$ ps $= 6 \times 24$ ps. ✓

Answer: $240.8\,\tau_{inv} \approx 5.78$ ns.

Remember. Before anything else, convert the load to µm of gate at the exam’s $C_g$ , and find $\tau_{inv}$ from $3R_nC_g$ : the same circuit at 2 fF/µm has half the load in µm, and half the last stage’s gain.

The answer key agrees

FN10-9b: sizing within the β limit (14 points)

FN10-9b, p16. Keeping $W_1$ fixed at 1 µm, resize the network to minimize the delay from A rising to E rising. Do not let the beta ratio of any gate become more than 4 or less than 0.25.

Hint

Which of FN19-8b’s numbers change here, and which stay the same?

What it asks. As FN19-8b: with $W_1$ fixed and every gate’s β between 1/4 and 4, choose $W_2$ to $W_6$ for the least delay from A rising to E rising. There is no side branch.

The idea. FN19-8b’s two moves (Section 2): skew each NAND to its β limit toward the edge it makes, which lowers $G$ , then take equal gains with the fixed $F = GH$ : the product of the gains is fixed, so their sum is smallest when they are equal. What is different is only $H$ : the load is 350 µm of gate instead of 700. The gates and the skew are the same, so $G$ is the same 0.347, $F$ halves, and each stage’s gain is smaller.

FN10-9b

Skew to the limits, because each NAND makes only one edge in evaluate: $W_4 = W_3/4$ (III falls) and $W_6 = W_5/4$ (IV rises), so stages III and IV have $g = 0.833$ . Stage II is already at $\beta = 4$ .
The path effort, because it sets the stage gain: $F = G \cdot H = 0.347 \times 350 = 121.5$ ; $f = \sqrt[4]{121.5} = 3.320$ .
Size back from the load, because its equation has only one unknown. IV: $350/(1.5W_5) = f$ gives $W_5 = 70.3\,\mu$ m and $W_6 = 17.6\,\mu$ m (D drives 87.8 µm).
III drives that 87.8 µm: $87.8/(1.5W_3) = f$ gives $W_3 = 17.6\,\mu$ m and $W_4 = 4.41\,\mu$ m (C drives 22.0 µm).
II drives that 22.0 µm: $\tfrac34 \times 22.0/(9W_2) = f$ gives $W_2 = 0.553\,\mu$ m (PFET 4.43 µm).
Stage I checks the work: $\tfrac23 \times 9 \times 0.553 = 3.32 = f$ . ✓
The delay. Four stages at $f$ : $4f\,\tau_{inv} = 13.28 \times 24\,\mathrm{ps} = 319$ ps.

Check. Against FN19-8b: only $H$ halved, so $F$ halved, and each of the four gains is divided by $\sqrt[4]{2}$ : $3.948/3.320 = 1.189 = 2^{1/4}$ . ✓

Answer: $W_2 = 0.55$ , $W_3 = 17.6$ , $W_4 = 4.41$ , $W_5 = 70.3$ , $W_6 = 17.6\,\mu$ m; delay $13.3\,\tau_{inv} \approx 319$ ps, down from 5.78 ns. Unskewed, the best would be $16.8\,\tau_{inv} = 403$ ps.

Remember. With the same gates and the same skew, only $H$ moves the result, and the best delay grows only as $H^{1/4}$ .

The answer key differs

It skews the same way ( $g = 1.25/1.5 = 0.833$ ), gets $f = 3.32$ and the same widths. Its $W_6 = 17.5$ is $70.3/4 = 17.6$ cut short. It gives no delay for the resized path: 319 ps. Its fourth root multiplies (a)‘s rounded gains, which give 122 rather than 121.5; the root is 3.32 either way.

5. Resize it yourself

The widget holds FN19-8 and FN10-9 as written above, with $W_2$ , $W_3$ and $W_5$ on sliders; $W_4$ and $W_6$ follow from the reading you choose. “Balanced NANDs” keeps $W_4 = W_3$ and $W_6 = W_5$ , so it opens at part (a), every width 1 µm. “Skewed to the β limits” is part (b): $W_4 = W_3/4$ , $W_6 = W_5/4$ ; press “sizes of (b)” or “lowest delay”. For FN19-8, “skewed, 200 fF on D” with the sizes of (b) is part (c).

W₂1.00 µm

W₃1.00 µm

W₅1.00 µm

I (dynamic, X falls): gain 6.00
II (inverter, C rises): gain 0.17
III (NAND2, D falls): gain 1.33
IV (NAND2, E rises): gain 466.67
delay Σ gains: 474.17 τ_inv = 11.854 ns
path effort F = Π gains: 622.2
lowest delay: 19.98 τ_inv = 0.499 ns at W2 = 0.83, W3 = 24.9, W5 = 93.4 µm

What to notice.

With no side load, $F$ stays the same whatever you do with the sliders, and the lowest delay has four equal gains (FN19-8: 3.948 each).
Switching between “balanced” and “skewed” changes only $G$ : the best delay drops from 499 to 395 ps (FN19-8) and from 403 to 319 ps (FN10-9).
With 200 fF on D, $F$ moves as you resize, because the fixed 200 µm sits beside NAND IV’s input in stage III’s load. Equal gains are no longer the best. The lowest point (486 ps) has a larger $W_5$ than (b): the “enlarge the gate after the branch” move.

What this means for the midterm

Which midterm family uses each method.

FN17-7 is the static path family of M4: the input limit is MT21-5a, and the dominant branch is MT21-5b, where rebalancing the pair before the branch does most of the work. MT23-5 and MT17-5 have the smaller branches, where enlarging the gate after the branch first can even hurt.
FN19-8 and FN10-9 join a dynamic stage to the static method; the approach section has the moves and why they work. The dynamic logical effort ( $g = k/3$ for an n-type stack with $R_p = 2R_n$ , $k/2$ at equal strengths) is MT23-3b’s and MT24-5b’s (M6); equal-gain sizing with the first gate fixed is MT23-5b and MT17-5b; the side branch at fixed sizes is MT23-5c and MT17-5c. A strength-ratio limit has not appeared on a midterm, but MT23-3c’s skewed inverter is the same idea.
FN12-8 is the domino-sizing drill already in M6.

Traps (the approach section explains each).

State the edges first, and check that the named edge pair can happen (MT24-5b’s key and FN17-2c’s ask for edges that can’t).
Count the footer in the dynamic stack; ignore the precharge device.
Use the whole input limit (FN17-7a, MT21-5a): a bigger first gate always helps.
Skew toward the edge that matters, to the limit; β compares strengths, not widths.
A side load changes one gain only at fixed sizes: the stage that drives that node.
Read the units. A 700 fF load is 700 µm at 1 fF/µm but 350 µm at 2 fF/µm.

Time. On these finals a point was worth about 43 seconds (180 minutes for 250 points), so FN19-8 had about 25 minutes and FN17-7 about 15. On a midterm pace (22.5–30 seconds a point), an (a) part takes 3–4 minutes, a (b) sizing 6–8, and a retuning around a branch 8–10. Write the gains in a table first; the arithmetic then takes little time.