M4. Past midterms: path sizing

Question 5 of three of the four past midterms is the same kind of problem. You get a path of four static CMOS gates driving a large load, with every width given, and you estimate its delay. Then you size the path for minimum delay with the first gate fixed. Then a side load is added in the middle, and you retune around it. It is worth 40, 35 and 40 of 150 points (MT23, MT21, MT17), about a quarter of each exam. MT24 moved the sizing into a dynamic path; that question is on the dynamic-logic page of the midterm kit (M6).

The questions are in order from the most recent. Every part is re-solved from the source figure; the keys’ numbers are not copied. A short How to approach section below gives the model and the moves once. Then every part is worked the same way: what it asks, the idea behind the method, the solution in steps (each step gives its reason first), a check on the result, the answer, and one thing to remember. Try each part on your own first; open the Hint if you are stuck. The answer key’s verdict is folded at the end of each part.

Before you start. Everything here is taught in Chapter 7 and Chapter 8:

the gain of a gate, $g \cdot h$ , from its normalized inverter (Chapter 8 §1, Chapter 7 §9);
the stack rule (Chapter 7 §8);
path delay $= \tau_{inv}\sum g_ih_i$ and path effort $F$ (Chapter 8 §2);
equal gains $F^{1/N}$ and sizing back from the load (§3, §6);
branching effort and retuning (§8, §9).

Conventions in this family. The model and the moves are in the next section; these are the conventions to state at the top of your answer.

Units. The delay unit is the given FO1 delay $\tau_{inv}$ , in picoseconds, so no 0.69 factor appears. Only gate capacitance counts (each exam says so).
Device strength decides the normalized inverter.
- MT17: the PFET has half the NFET’s drive ( $R_p = 2R_n$ ). The inverter is 2W/W, its input $3W$ , $g_{NAND2} = 4/3$ and $g_{NOR2} = 5/3$ .
- MT21 and MT23: equal strengths. The inverter is W/W, its input $2W$ , and $g_{NAND2} = g_{NOR2} = 3/2$ .
- The AOI22 and OAI22 have $g = 2$ either way.

How to approach a path-sizing question

Recognize it by the picture: four static gates in a row, every transistor labelled with a width, and a large capacitor at the end. The parts always come in the same order: (a) the delay as drawn, (b) the sizes for minimum delay, (c) the delay after a side load is added, (d) a retuning. Each part reuses the numbers of the one before, so keep one table of the stages.

The model, and why it works. Delays are counted in units of $\tau_{inv}$ , the fan-out-of-one delay of the balanced inverter. An inverter that drives $k$ copies of itself takes $k\,\tau_{inv}$ : its delay grows with the load and falls with its strength, and its strength is measured by its own input capacitance. A gate, for its delay, behaves like its normalized inverter: the inverter with the same drive strength. So each stage’s delay is $\tau_{inv}$ times its gain (Chapter 8, Section 1):

\text{gain} = \frac{\text{the load the stage drives}}{\text{its normalized inverter's input}}

\text{path delay} = \tau_{inv} \sum \text{gains}

The gain is the logical effort times the electrical effort, $g \cdot h$ , without computing them separately (Chapter 8, Section 2).

Finding a normalized inverter. Ask how strongly the gate pulls down, and how strongly up, when a single input switches (the worst case). Transistors in series act like one transistor of width $1/\sum(1/W_i)$ : two equal ones like one of half the width. A transistor alone acts as itself (Chapter 7, Section 8). The normalized inverter’s input is the sum of the two equivalent widths. One input of the real gate drives one NFET and one PFET, and the ratio of the two inputs is the logical effort $g$ .

The moves.

Tabulate the stages: each one’s normalized-inverter input and the capacitance of one of its inputs, in µm of gate. Convert the load to µm: $C/C_g$ .
(a) Each gain is the next stage’s input (or the load) over this stage’s normalized input; the delay is $\tau_{inv}$ times their sum.
(b) Multiply the gains: the inner widths cancel and leave the path effort $F$ , a fixed number. With a fixed product, the sum is smallest when every gain is the same, $f = F^{1/N}$ . Size back from the load.
(c) A side load adds to the one stage that drives its node. Recompute that gain only.
(d) With a side load, $F$ is no longer fixed, so $F^{1/N}$ is only a guess. Rebalance the overloaded stage with the one before it; then try a larger gate after the branch.

Decide on the way: the strength convention (it sets the normalized inverter: W/W with equal strengths, 2W/W with $R_p = 2R_n$ ), and which node a side load hangs on.

Traps. Dividing by the gate’s own input instead of its normalized inverter’s (that gives $h$ , not the gain). A side load on the wrong node. Picoseconds against nanoseconds. Treating a recomputed $F$ as fixed after a branch.

1. MT23-5: a 25 fF side load (40 points)

You need

Delay in units of $\tau_{inv}$ . $\tau_{inv}$ is the fan-out-of-one (FO1) delay: a balanced inverter driving one copy of itself. This exam gives it, 50 ps. A stage of a path takes $\tau_{inv}$ times its gain: the capacitance the stage drives, divided by the input capacitance of its normalized inverter, the inverter that pulls down and up as strongly as the gate does. The gain is the logical effort times the electrical effort, $g \cdot h$ . Part (a) explains where this comes from.

Equal strengths. MT23-5 says the NFET and the PFET have the same drive, so a balanced inverter is W/W, with input $2W$ . (The lecture’s technology has $R_{pfet} = 2R_{nfet}$ and a 2W/W inverter instead.)

The stack rule. A conducting transistor of width $W$ acts like a resistance $R/W$ . Two equal ones in series add their resistances, so they act like one transistor of half the width; a transistor alone acts as itself. Reading the circuit below uses this for every gate.

Path delay and path effort. A path’s delay is $\tau_{inv}$ times the sum of its gains. When every gate drives only the next one and the path’s input and load are fixed, the product of the gains, the path effort $F$ , is fixed too, and equal gains $f = F^{1/N}$ make the sum smallest (part (b) shows why). A capacitor hanging off the path, a branch, adds to one stage’s load (part (c)) and makes $F$ depend on the sizes (part (d)).

Left: two NFETs of width W in series from node X to ground, beside two resistors R_n/W in series. Right: one NFET of width W/2, beside one resistor 2R_n/W. — The stack rule: two in series act like one of half the width. Original figure ↑

The question (MT23-5, p11, in the paper’s words). Consider the critical path shown below through a set of complementary static CMOS gates. In this technology, the nFET and pFET have the same drive strength and the circuit is sized for equal rising and falling delays. We are working in a technology in which the gate capacitance per unit width is 1 fF/µm. Assume that the FO1 delay is $\tau_{inv} = 50$ psec. A minimum width device 1.0 µm. Please ignore source-drain diffusion capacitances and overlap capacitances; that is, worry only about the gate input capacitances of the devices. Let $C_{load} = 1$ pF.

MT23-5's critical path: an inverter with PFET and NFET W1 from A to B; an AOI22 from B to C whose pull-up is two parallel pairs of PFETs W2 in series and whose pull-down is two parallel stacks of two NFETs W2, B driving the lower-left PFET and the upper-left NFET; a NAND2 from C to D with two parallel PFETs W3 and two series NFETs 2W3; an inverter with PFET and NFET W4 from D to E; C_load from E to ground. — MT23-5’s critical path (p11, redrawn). Nodes A to E as on the paper. Stage 1 is an inverter $W_1/W_1$ ; stage 2 an AOI22 with every device $W_2$ ; stage 3 a NAND2 with PFETs $W_3$ and series NFETs $2W_3$ ; stage 4 an inverter $W_4/W_4$ driving $C_{load}$ .

The exam’s own figure (MT23-5, p11)

Four stages from A to E: an inverter with PFET W1 and NFET W1; an AOI22 with two series pairs of PFETs W2 and two series pairs of NFETs W2, output C; a NAND2 with parallel PFETs W3 and series NFETs 2W3, output D; an inverter W4/W4 driving Cload at E. — MT23-5, p11 (source figure).

Reading the circuit

Every part needs the same two numbers for each gate, so find them once. The first is its normalized inverter’s input: that measures how strongly the gate drives. The second is the capacitance of one of its inputs: that is the load it puts on the stage before it. The NFET and PFET have equal strength, so an NFET and a PFET of the same width drive equally, and the balanced inverter is W/W.

Why the stack rule. added In the course’s model a conducting transistor is a resistor whose resistance falls as it gets wider: $R/W$ . Current through a stack of two must pass through both, so the resistances add: $R/W + R/W = 2R/W = R/(W/2)$ . Two in series therefore drive like one transistor of half the width. The rule assumes every device in the stack is fully on, which is the worst case of one input switching while the others already conduct. It ignores the extra delay of the node inside the stack (Chapter 8 §10’s bottom-device effect).

Reading MT23-5 gate by gate

Stage 1, an inverter W₁/W₁. An inverter is its own normalized inverter. Its input drives both devices: $2W_1$ . So $g = 1$ .
Stage 2, the AOI22, every device W₂. When one input switches, two NFETs in series pull down and two PFETs in series pull up. Two in series act like one of half the width, so the gate drives like a $W_2/2$ over $W_2/2$ inverter, whose input is $W_2$ . One real input drives one NFET and one PFET, $2W_2$ , so $g = 2W_2/W_2 = 2$ .
Stage 3, the NAND2. Its two NFETs, $2W_3$ each, are in series and act like one of $W_3$ ; a single PFET, $W_3$ , pulls up. So the normalized inverter is $W_3/W_3$ , input $2W_3$ . That is why the exam drew the NFETs twice as wide: a stack of two $2W_3$ devices pulls down as hard as the one $W_3$ PFET pulls up, which is what “equal rising and falling delays” asks for. One input drives $2W_3 + W_3 = 3W_3$ , so $g = 3/2$ .
Stage 4, an inverter W₄/W₄: input $2W_4$ , $g = 1$ .
The load: $1\,\mathrm{pF}/(1\,\mathrm{fF/\mu m}) = 1000\,\mu\mathrm{m}$ of gate. Converting every capacitance to microns of gate lets each gain be a ratio of widths.

Panel (a): the AOI22 with one input switching, two series PFETs W2 over two series NFETs W2, equivalent to an inverter W2/2 over W2/2 with input W2. Panel (b): the NAND2, one PFET W3 over two series NFETs 2W3, equivalent to an inverter W3/W3 with input 2W3. — The normalized inverters of stages 2 and 3 added: (a) the AOI22, a stack of two $W_2$ devices in each network, drives like a $W_2/2$ over $W_2/2$ inverter, input $W_2$ ; (b) the NAND2, two $2W_3$ NFETs in series and one $W_3$ PFET, drives like a $W_3/W_3$ inverter, input $2W_3$ .

Stage	Gate	Devices	Acts like (normalized inverter)	One input	$g$
1	inverter	W₁/W₁	W₁/W₁, input $2W_1$	$2W_1$	1
2	AOI22	every device W₂, stacks of two in both networks	W₂/2 over W₂/2, input $W_2$	$2W_2$	2
3	NAND2	NFETs 2W₃ in series, PFETs W₃ in parallel	W₃/W₃, input $2W_3$	$3W_3$	3/2
4	inverter	W₄/W₄	input $2W_4$	$2W_4$	1

Part (a): the delay as drawn (10 points)

MT23-5a, p11. Estimate the delay of the path from A to E, which is the same for a falling (rising) input at A propagating to a rising (falling) output at E. Let $W_1 = 10\,\mu$ m, $W_2 = 1.0\,\mu$ m, $W_3 = 1.0\,\mu$ m, and $W_4 = 1.0\,\mu$ m. (10 points)

Hint

Each stage’s gain is the next stage’s input (or the load) over its own normalized inverter’s input. The stage table under Reading the circuit lists both for every gate.

What it asks. The delay of the path exactly as drawn: a 10 µm first inverter and every other gate at the 1 µm minimum. Nothing is sized yet. The word “estimate” says the gain model is enough; no device equations are needed.

The idea. Each stage takes $\tau_{inv}$ times its gain, and its gain is the capacitance it drives over its normalized inverter’s input. A stage drives the next stage’s input; the last one drives the load. So read each gain off the table and add them.

Why this formula. added The gain rule is an RC estimate measured against the FO1 inverter.

Where it comes from. On the falling edge a stage’s output discharges through its pull-down network. In the course’s model a conducting NFET of width $W$ is a resistance $R_n/W$ , so the network acts like the normalized inverter’s NFET, $R_n/W_{eq}$ . The capacitance it discharges is everything on the output node, $C_{out}$ : $C_g$ times the gate width hanging there. The time is proportional to resistance times capacitance: $t \propto (R_n/W_{eq})\,C_{out}$ .
The same for the yardstick. $\tau_{inv}$ is a W/W inverter driving a copy of itself, $C_{out} = 2W\,C_g$ : $\tau_{inv} \propto (R_n/W)\,C_g\,2W$ , whatever $W$ is.
Divide. The proportionality constant cancels in the ratio, so $t/\tau_{inv} = (C_{out}/C_g)/(2W_{eq})$ : the load, in microns of gate, over the normalized inverter’s input $2W_{eq}$ . That is why no 0.69 appears anywhere in this question, and why the exam gives $\tau_{inv}$ instead of $R_n$ .
Conditions, and why they hold. Only gate capacitance counts: the exam says to ignore diffusion and overlap. The gates are balanced (the exam says so), so the rising edge, through the PFETs, gives the same gain as the falling one. One input switches through the full stack, the worst case, which is the normalized inverter of the table.
The tempting alternative. Dividing by the gate’s own input capacitance gives the electrical effort $h$ , not the gain. It leaves out the logical effort: for the AOI22 it would give $3/2 = 1.5$ instead of 3, half the true delay.

Left: a normalized inverter with NFET and PFET of width W, input 2W, driving C_out. Right: on the falling edge the NFET becomes a resistor R_n/W discharging C_out; the time is proportional to (R_n/W) C_out. — Where the gain comes from added: on the falling edge the normalized inverter’s NFET is a resistance $R_n/W$ discharging $C_{out}$ , so the time goes as $(R_n/W)\,C_{out}$ . With $C_{out} = 2W\,C_g$ , a copy of itself, that time is $\tau_{inv}$ .

MT23-5a

Stage 4 drives the 1000 µm load. It is an inverter, so its normalized input is its own, $2W_4 = 2\,\mu$ m: gain $1000/2 = 500$ .
Stage 3 drives stage 4’s input, $2W_4 = 2\,\mu$ m. Its normalized inverter is $W_3/W_3$ , input $2W_3 = 2\,\mu$ m: gain 1.
Stage 2 drives one NAND input, $3W_3 = 3\,\mu$ m. Its normalized inverter’s input is $W_2 = 1\,\mu$ m: gain 3.
Stage 1 drives one AOI input, $2W_2 = 2\,\mu$ m, from its own input $2W_1 = 20\,\mu$ m: gain 0.1. A big gate driving a small one has a gain below 1: it is fast, but its size is wasted here.
Add. Because each stage’s delay is its gain times $\tau_{inv}$ , the path’s delay is $(0.1 + 3 + 1 + 500)\,\tau_{inv} = 504.1 \times 50\,\mathrm{ps} = 25{,}205\,\mathrm{ps}$ .

Check. A second route to each gain is $g \cdot h$ : the logical effort from the table’s $g$ column times the electrical effort $h$ , the load over the gate’s own input (not its normalized inverter’s). For the two inverters $g = 1$ and the two routes coincide, so the complex gates are the real test. Stage 2, the AOI22: $g = 2$ and $h = 3W_3/2W_2 = 3/2 = 1.5$ , so $g \cdot h = 3$ ✓. Stage 3, the NAND: $g = 3/2$ and $h = 2W_4/3W_3 = 2/3$ , so $g \cdot h = 1$ ✓. Gains of 0.1 and 500 in one path are the sign of a badly sized path, which part (b) fixes.

Answer: $504.1\,\tau_{inv} \approx 25.2$ ns. The last stage’s gain of 500 is almost all of it.

Remember. Gain = load ÷ normalized inverter’s input; delay = $\tau_{inv}$ × the sum of the gains. Very unequal gains mean the sizes can be improved.

The answer key agrees

Its four gains (500, 1, 3 and 0.1) and its 25.20 ns match.

Part (b): equal-gain sizing (10 points)

MT23-5b, p12. Assume that $W_1$ is fixed at 1.0 µm but you are free to tune $W_2$ , $W_3$ , and $W_4$ . Find approximate values of $W_2$ , $W_3$ , and $W_4$ to minimize delay and estimate the new delay of your resized network. (10 points)

Hint

Write the four gains with

W_2

W_3

and

W_4

as unknowns and multiply them. What is left?

What it asks. Choose $W_2$ , $W_3$ and $W_4$ to make the delay as small as possible, with the first inverter fixed at 1 µm, and give the new delay. Fixing $W_1$ fixes the path’s input capacitance. Without that you could make every gate huge and push the problem onto whatever drives A. The words “minimize delay” with one gate fixed and nothing branching decide the method: equal gains.

The idea. Two facts from Chapter 8 do all the work. The product of the gains is fixed, and with a fixed product the sum is smallest when the factors are equal. So every stage gets the same gain, $f = F^{1/4}$ , and the widths follow from it, one stage at a time from the load back.

Why this formula. Part (b) uses four facts. Each is short to derive.

The gain of each stage is the load over the normalized inverter’s input, as part (a) explains: a stage discharges its load, $C_{out}$ , through a resistance $R_n/W_{eq}$ , where $W_{eq}$ is the width of its normalized inverter’s NFET; dividing by the FO1 inverter’s own RC product leaves $(C_{out}/C_g)/(2W_{eq})$ , the load in microns of gate over the normalized input. The stage table of Reading the circuit gives the normalized inputs, $2W_1$ , $W_2$ , $2W_3$ and $2W_4$ , and the capacitance of one input, $2W_1$ , $2W_2$ , $3W_3$ and $2W_4$ . Each stage drives the next stage’s one input, and the last drives the 1000 µm load, so with the widths as unknowns the four gains are $\dfrac{2W_2}{2W_1}$ , $\dfrac{3W_3}{W_2}$ , $\dfrac{2W_4}{2W_3}$ , $\dfrac{1000}{2W_4}$ .
The product of the gains is fixed (Chapter 8 §2). Each inner width appears in two gains: on top in the gain of the stage before it, because it is that stage’s load, and underneath in its own stage’s gain, because it is that stage’s strength. In the product it cancels. What is left depends only on the gate types, the fixed $W_1$ and the load: $F = G \cdot H$ , with $G = 1 \cdot 2 \cdot \tfrac32 \cdot 1 = 3$ (the four logical efforts) and $H = C_{load}/C_{in} = 1000/(2W_1) = 500$ , with $C_{in} = 2W_1$ the path’s input capacitance. This needs nothing to branch off the path, which is true here until part (c).
Equal gains minimize the sum added, and not only for the numbers tried. Change one inner width, say $W_3$ , and leave the others. Only two gains move: stage 2’s gain $3W_3/W_2$ rises in proportion to $W_3$ , because the NAND is stage 2’s load, and stage 3’s gain $2W_4/2W_3$ falls in the same proportion, because the NAND is stage 3’s driver. Their product, $3W_4/W_2$ , does not change. For two numbers $a$ and $b$ with a fixed product $P$ , $a + b - 2\sqrt P = (\sqrt a - \sqrt b)^2 \ge 0$ : the sum is smallest exactly when $a = b$ . So at the best $W_3$ , stages 2 and 3 have equal gains. The same holds for $W_2$ (stages 1 and 2) and for $W_4$ (stages 3 and 4). All four gains are then equal, and they multiply to $F$ , so each is $F^{1/4}$ . Chapter 8’s plot shows the two-stage curve.
The stack widths added. Translating a normalized inverter back into a gate uses the stack rule. Resistances in series add, $R/W + R/W = R/(W/2)$ , so the NAND’s two series NFETs must each be twice the normalized NFET. That is the $2W_3$ in the exam’s figure, and it is why one NAND input presents $2W_3 + W_3 = 3W_3$ to the AOI.
The tempting alternatives. Making every width equal, or every electrical effort $h$ equal, is not the rule: gates with a larger logical effort must get a smaller $h$ . And starting from the fixed $W_1$ instead of the load does not work: each stage’s load is not known until the next stage is sized.

Plot of Delay/τ_inv = 16/f_2 + f_2 against f_2 on a log axis from 0.5 to 32: a U-shaped curve with its minimum 8 at f_2 = 4, marked points 17 at f_2 = 1 and 16, and 10 at f_2 = 2 and 8. — Chapter 8’s two-stage curve for a fixed product of 16: the sum of the two gains is smallest, 8, at the equal split 4 and 4, and grows fast as the split becomes unequal. Original figure ↗

MT23-5b

The gains, with the widths unknown. We need them as functions of the widths before we can choose the widths. Each gain is what the stage drives over its normalized input: the inverter drives the AOI’s input $2W_2$ from $2W_1$ ; the AOI drives one NAND input, $3W_3$ , from its normalized input $W_2$ ; the NAND drives the inverter’s $2W_4$ from $2W_3$ ; the inverter drives 1000 µm from $2W_4$ . So the gains are $\dfrac{2W_2}{2W_1}$ , $\dfrac{3W_3}{W_2}$ , $\dfrac{2W_4}{2W_3}$ , $\dfrac{1000}{2W_4}$ .
Their product. Because $W_2$ , $W_3$ and $W_4$ each appear once on top and once underneath, they cancel: $F = \dfrac{1500}{W_1} = 1500$ . (Part (a)‘s gains multiply to $0.1 \times 3 \times 1 \times 500 = 150$ , which is $1500/W_1$ with its $W_1 = 10$ : a quick check.)
Equal gains. Because the product is fixed and the sum is smallest with equal factors, each of the four stages gets $f = \sqrt[4]{1500} = 6.223$ .
Size back from the load. Start at the end, because the load is known: the last stage’s equation has only one unknown, and each step back adds only one more. Stage 4 is an inverter, its own normalized inverter, so its gain is the load over its input: $\dfrac{1000}{2W_4} = f$ gives $W_4 = 80.3\,\mu$ m.
Stage 3, the NAND. Its normalized inverter’s input is $2W_3$ (the stack of two $2W_3$ NFETs acts like $W_3$ ), and it drives the inverter’s input $2W_4$ : $\dfrac{2W_4}{2W_3} = f$ gives $W_3 = 12.9\,\mu$ m.
Stage 2, the AOI. Its normalized inverter’s input is $W_2$ ( $W_2/2 + W_2/2$ ), and it drives one NAND input, the PFET $W_3$ plus one NFET $2W_3$ : $\dfrac{3W_3}{W_2} = f$ gives $W_2 = 6.22\,\mu$ m.
Stage 1 is not chosen; it checks the work. $W_2/W_1 = 6.22 = f$ ✓. It has to come out equal, because the four gains multiply to $F = f^4$ ; if it doesn’t, an earlier step has a slip.
The delay. Four stages at $f$ each: $4f\,\tau_{inv} = 24.89 \times 50\,\mathrm{ps} = 1245\,\mathrm{ps}$ .

Check. From 25.2 ns to 1.24 ns: twenty times faster, from resizing alone. A second check that this is a minimum: make the NAND 10% wider, $W_3 = 14.2\,\mu$ m, with the other widths kept. Stage 2’s gain rises to 6.85 and stage 3’s falls to 5.66, and the delay rises to $24.95\,\tau_{inv}$ , as it must just beside a flat minimum. A gain of 6.2 per stage is above the 3–4 that Chapter 8 aims for (Section 4), which says that more stages would help if you could add them (M7’s Question 5c asks exactly that). Here the four gates are fixed.

Answer: $W_2 = 6.22\,\mu$ m, $W_3 = 12.9\,\mu$ m, $W_4 = 80.3\,\mu$ m; delay $24.9\,\tau_{inv} \approx 1.24$ ns, down from 25.2 ns.

Remember. With nothing branching off the path, $F$ is fixed: take $f = F^{1/N}$ , size back from the load, and let the first stage check your arithmetic.

The answer key differs

It gives “1244.7 ns”. The number is right; the unit is ps (1.24 ns).

Part (c): the side load (10 points)

MT23-5c, p13. Now assume that the circuit is modified as shown below. What is the delay of the circuit now from A to E using your sizing from (b)? (10 points)

The MT23-5 path of part (b) with a 25 fF capacitor from node C to ground; node C is the wire from the AOI22's output to the NAND2's PFET and upper NFET gates. — MT23-5c’s modified path (p13, redrawn): the same four stages, with a 25 fF capacitor from node C, the AOI22’s output, to ground.

The exam’s own figure (MT23-5c, p13)

The same path with a 25 fF capacitor to ground hanging from node C, the wire from the AOI22's output to the NAND2's inputs. — MT23-5c, p13 (source figure). The 25 fF capacitor hangs from node C, the AOI’s output.

Hint

Which stage’s output is the node the capacitor hangs on? Only that stage’s load changes.

What it asks. A 25 fF capacitor is added to the path of (b). Keep the sizes of (b) ( $W_2 = 6.22$ , $W_3 = 12.9$ , $W_4 = 80.3\,\mu$ m) and find the new delay. The first job is to read the figure: which node carries the capacitor?

The idea. A side load is extra capacitance on one node, and each node is driven by exactly one stage. So it raises that one stage’s load, and with it that stage’s gain. Every other stage still drives what it drove before, at the same size, so their gains don’t change.

Why this formula. The gain of the stage driving the node is now its whole load over its normalized inverter’s input. For stage 2 that is $\dfrac{C_{on} + C_{off}}{W_2}$ , where $C_{on} = 3W_3$ is the NAND input it drives along the path, $C_{off}$ is the side load off the path, both in microns of gate, and $W_2$ is the AOI’s normalized input from the stage table. The reason is the same RC estimate as in part (a): the stage discharges every capacitance on its output node through the same resistance, whether that capacitance belongs to the next gate or to a wire. The 25 fF becomes $25\,\mathrm{fF}/(1\,\mathrm{fF/\mu m}) = 25\,\mu$ m of gate, because each gain is a ratio of capacitances, and expressing all of them in microns of gate at the same $C_g$ makes them ratios of widths. Only that one gain moves: a stage’s gain depends only on its own size and on what hangs on its own output. The tempting alternatives both fail. Recomputing $F^{1/4}$ answers a different question (resizing, which part (d) asks). Putting the capacitor on node D, the NAND’s output, misreads the figure.

MT23-5c

Find the node. The 25 fF hangs from the wire that runs from the AOI’s output to the NAND’s input (the gates of its $W_3$ PFET and its upper $2W_3$ NFET): node C, the output of stage 2.
Add it to stage 2’s load. At 1 fF/µm it is 25 µm of gate, so stage 2 now drives $3W_3 + 25 = 38.73 + 25 = 63.73\,\mu$ m.
Stage 2’s new gain. Its normalized inverter is unchanged, input $W_2 = 6.223\,\mu$ m: $63.73/6.223 = 10.24$ , up from 6.22.
The other three gains stay at 6.22: their loads and their sizes haven’t changed.
The delay. Because the delay is $\tau_{inv}$ times the sum of the gains: $(3 \times 6.223 + 10.24)\,\tau_{inv} = 28.91 \times 50\,\mathrm{ps} = 1446\,\mathrm{ps}$ .

Check. Chapter 8 gives a second route, through the path effort (Section 8). The path effort $F$ is the product of the gains. Without a branch it is $G \cdot H$ ; with one it becomes $F = G\,H\,B$ . Here $B$ is the product of the branching efforts $b = (C_{on} + C_{off})/C_{on}$ of the branched nodes: how many times the whole load on a node exceeds the part that stays on the path. It enters because the branched stage’s gain is $b$ times what it would be without the branch, while every inner width still cancels from the product. Only node C branches, so $B = b = 63.73/38.73 = 1.645$ , and with $G \cdot H = 1500$ from (b), the new $F = 1500 \times 63.73/38.73 = 2468$ . Step 5’s four gains must multiply to the same number: $6.223^3 \times 10.24 = 2468$ ✓.

Answer: $28.9\,\tau_{inv} \approx 1.45$ ns.

Remember. A side load changes one gain: that of the stage driving its node. Find the node first.

The answer key differs

It adds the 25 fF to stage 3’s load (node D), not stage 2’s, and it drops the $\tau_{inv}$ factor: 1293 “ns”. In the source figure the capacitor is on node C. With the capacitor on D the delay would be $25.86\,\tau_{inv} = 1.29$ ns, and the key’s number fits that reading.

Part (d): retuning (10 points)

MT23-5d, p14. How might this new circuit be resized to reduce the delay calculated in (c), again keeping $W_1$ fixed? Perform this retuning and calculate the new delay. You do not have to achieve a “minimum” delay here; just demonstrate how you would retune the circuit to improve the delay. (10 points)

Hint

Nothing branches between stages 1 and 2. If only

W_2

changes, what happens to the product of their two gains?

What it asks. Resize, with $W_1$ still fixed, to bring the delay of (c) down, and compute it. The exam doesn’t require the minimum, only a sensible retuning, explained. The gains now are 6.22, 10.24, 6.22 and 6.22: stage 2 is overloaded.

The idea. The equal-gain rule of (b) relied on a fixed product of gains. The 25 fF breaks that: it doesn’t grow when the NAND grows, so the path effort now depends on $W_3$ (Chapter 8, Section 8), and a recomputed $F^{1/4}$ is only a guess. But the rule still holds on any piece of the path with nothing branching off it. So retune piece by piece:

Rebalance around the overloaded stage. Stage 2’s gain jumped to 10.24 while stage 1’s stayed at 6.22. Nothing branches between them, so while only $W_2$ moves the product of their two gains is fixed, and the best split is equal.
Then try enlarging the gate after the branch (the NAND). It lowers stage 3’s gain, and it adds to stage 2’s load only through its own input; the 25 fF stays as it is.

The lecture does these two moves the other way round, enlarging first (Chapter 8, Section 9). That order pays off when the branch is most of the load. Here the 25 fF is only 39% of stage 2’s load, and enlarging the NAND alone (to $W_3 = 16\,\mu$ m) raises the delay to $29.20\,\tau_{inv}$ . So rebalance first.

Why this formula. added Two results do the work.

The pair rule, and where it breaks. As part (b) showed, resizing only the gate between two stages moves only their two gains, and when their product stays fixed, $a + b \ge 2\sqrt{ab}$ makes the equal split best. Here two of the three pairs still have a fixed product. Stages 1 and 2 share $W_2$ : their gains are $\dfrac{2W_2}{2}$ and $\dfrac{3W_3 + 25}{W_2}$ , whose product $3W_3 + 25$ does not contain $W_2$ . Stages 3 and 4 share $W_4$ : $\dfrac{W_4}{W_3}\cdot\dfrac{500}{W_4} = \dfrac{500}{W_3}$ . Stages 2 and 3 share $W_3$ , and their product $\dfrac{(3W_3 + 25)\,W_4}{W_2W_3}$ still contains $W_3$ . A wider NAND raises stage 2’s gain only through the NAND’s share of its load ( $3W_3$ of $3W_3 + 25$ ), while it lowers stage 3’s gain in full proportion. That is why the best gains end up unequal across the branch.
The split formula. Fix $W_3$ and balance each side. A balanced pair with product $P$ has two gains of $\sqrt P$ , so it contributes $2\sqrt P$ . The delay is then $D(W_3) = 2\sqrt{3W_3 + 25} + 2\sqrt{500/W_3}$ in $\tau_{inv}$ , a function of one width that you can tabulate.
The tempting alternative fails. Recomputing $F$ at the current sizes and taking $\sqrt[4]{F}$ treats $F$ as fixed, which a branch makes false; below, it makes the path slower.

MT23-5d

Rebalance stages 1 and 2. Because the product of their two gains is fixed while only $W_2$ moves, the equal split is best. Their gains are $\dfrac{2W_2}{2}$ and $\dfrac{63.73}{W_2}$ , whose product is 63.73 whatever $W_2$ is. Equal gains: $\sqrt{63.73} = 7.98$ each, so $W_2 = 7.98\,\mu$ m.
The delay now: $2(7.98) + 2(6.22) = 28.41\,\tau_{inv} = 1.42$ ns. This one change does most of the work.
Split the path at the branch added. Because each side of the branch is a branch-free piece, choose a NAND size $W_3$ and balance each side separately. Stages 3 and 4 share the product $\dfrac{W_4}{W_3} \cdot \dfrac{500}{W_4} = \dfrac{500}{W_3}$ , and stages 1 and 2 share $W_2 \cdot \dfrac{3W_3 + 25}{W_2} = 3W_3 + 25$ .
The delay for a chosen W₃. A balanced pair with product $P$ contributes $2\sqrt{P}$ , so the delay is $2\sqrt{3W_3 + 25} + 2\sqrt{500/W_3}$ .
Try a few widths. $W_3 = 12.9$ : 28.41. $W_3 = 15$ : 28.28. $W_3 = 16$ : 28.27. $W_3 = 20$ : 28.44. Take $W_3 = 16\,\mu$ m. The curve is flat near its bottom, so a rough choice is enough.
The widths. Stages 1 and 2 take $\sqrt{73} = 8.54$ each, so $W_2 = 8.54\,\mu$ m. Stages 3 and 4 take $\sqrt{500/16} = 5.59$ each, so $W_4 = 500/5.59 = 89.4\,\mu$ m.
The delay: $2(8.54) + 2(5.59) = 28.27\,\tau_{inv} = 1.41$ ns.

Check. At $W_3 = 12.9$ , the size from (b), the split formula gives 28.41, the same as step 2: the formula contains the first move as a special case. And 28.27 is within 0.01% of the exact minimum with $W_1$ fixed. That minimum comes from imposing all three pair conditions at once: stages 1 and 2 equal, $W_2^2 = 3W_3 + 25$ ; stages 3 and 4 equal, $W_4^2 = 500W_3$ ; and the trade across the branch balanced, the NAND’s share of stage 2’s gain equal to stage 3’s gain, $3W_3/W_2 = W_4/W_3$ , that is $3W_3^2 = W_2W_4$ . Solved together they give $W_2 = 8.53$ , $W_3 = 15.9$ , $W_4 = 89.3\,\mu$ m and $28.268\,\tau_{inv}$ . Retune it yourself plots the whole curve.

Answer: first $W_2 = 8.0\,\mu$ m (1.42 ns); then $W_2 = 8.5$ , $W_3 = 16$ , $W_4 = 89\,\mu$ m, which gives $28.3\,\tau_{inv} \approx 1.41$ ns. That is the minimum to within 0.01%. The best gains are not equal: the two stages before the branch share one value (8.54), the two after it a smaller one (5.59).

Remember. With a branch, balance pieces, not the whole path: equal gains still hold on each piece with nothing branching off it. The safe first move is to rebalance the overloaded stage with the one before it.

The answer key differs

It treats the 25 fF as a perturbation: it recomputes $F$ at the current sizes, takes $\sqrt[4]{F}$ and sizes back from the load again, ending at 1292.1 “ns”, with the capacitor on D as in its (c). That method assumes $F$ is fixed, and with a branch it is not. Applied to the capacitor where the figure puts it, on C, the method sets $F = 2468$ and $f = 7.05$ , and it shrinks the gates after the branch. The delay rises to $28.98\,\tau_{inv}$ , worse than not retuning (28.91).

2. MT21-5: an input limit and a 500 fF branch (35 points)

The question (MT21-5, p8). $\tau_{inv} = 100$ ps and $C_g = 1$ fF/µm. Only gate capacitance counts. The NFET and PFET have equivalent drive strengths. The path runs from A through an OAI gate, a NOR, an inverter and a NAND to Y, which drives 100 fF. A capacitor $C_B$ hangs on the NOR’s output.

The source circuit: an OAI gate with series PFET pairs W2 (B over A, D over C) and NFETs W1 (A parallel B, in series with C parallel D); a NOR with series PFETs W4 and parallel NFETs W3; capacitor CB on the NOR output; an inverter W6/W5; a NAND with parallel PFETs W8 and series NFETs W7, output Y driving 100 fF. Handwritten by the key: the function (A+B)(C+D) overlined, the labels OAI, NOR, INV, NAND, g1 = 2, g2 = 3/2, g3 = 1, g4 = 3/2, and a block sketch. — MT21-5, p8 (source figure). The handwriting (function, gate names, g values and the block sketch) is the key’s.

Reading the circuit

The same kind of path as MT23-5, with two differences. No gate is given a width: the first gate is limited by its input capacitance instead. And every gate must be balanced by you, so each gate’s two widths are tied together and one width per gate is free. Find the ties and the gains once.

Reading MT21-5 gate by gate

Stage 1, the OAI22, $\overline{(A+B)(C+D)}$ . When one input switches, the output pulls down through two NFETs in series ( $W_1$ each: A or B, then C or D) and pulls up through two PFETs in series ( $W_2$ each). Both networks act like one transistor of half the width, and the strengths are equal, so the gate is balanced at $W_1 = W_2$ . It drives like a $W_1/2$ over $W_1/2$ inverter, input $W_1$ . One input drives one NFET and one PFET, $W_1 + W_2 = 2W_1$ , so $g = 2$ .
Stage 2, the NOR2. Its two PFETs ( $W_4$ ) are in series and act like $W_4/2$ ; one NFET ( $W_3$ ) pulls down alone. Balanced means $W_4/2 = W_3$ , so $W_4 = 2W_3$ . The normalized inverter is $W_3/W_3$ , input $2W_3$ ; one input drives $W_3 + W_4 = 3W_3$ , so $g = 3/2$ .
Stage 3, the inverter. Equal strengths balance it at $W_5 = W_6$ : input $2W_5$ , $g = 1$ .
Stage 4, the NAND2. Its two NFETs ( $W_7$ ) are in series and act like $W_7/2$ ; one PFET ( $W_8$ ) pulls up alone. Balanced means $W_8 = W_7/2$ . The normalized inverter’s input is $W_7$ ; one input drives $W_7 + W_8 = 1.5W_7$ , so $g = 3/2$ .
The load and the branch. 100 fF at 1 fF/µm is 100 µm of gate. $C_B$ hangs on the wire from the NOR’s output to the inverter’s input: the output of stage 2, the same position as MT23-5’s 25 fF.

Stage	Gate	Balanced widths	One input	$g$
1	OAI22, $\overline{(A+B)(C+D)}$	stacks of two in both networks: $W_1 = W_2$	$W_1 + W_2$	2
2	NOR2	PFETs in series: $W_4 = 2W_3$	$W_3 + W_4 = 3W_3$	3/2
3	inverter	$W_5 = W_6$	$2W_5$	1
4	NAND2	NFETs in series: $W_7 = 2W_8$	$W_7 + W_8 = 1.5W_7$	3/2

Which edge? A rising A gives a falling OAI output, then a rising NOR output, a falling inverter output and a rising Y. Every gate is balanced, so the falling case has the same gains, and one sum serves both edges.

Part (a): the input limit (15 points)

MT21-5a, p8. With $C_B = 0$ , and the input capacitance of each of A, B, C and D limited to 1 fF, find the sizing for minimum delay from A rising to Y rising (or falling to falling).

Hint

No width is given for the first gate, only a cap on its input. Does a larger input make the path’s job easier or harder?

What it asks. Choose all eight widths for the fastest A-to-Y path, with no branch yet ( $C_B = 0$ ), when each input may present at most 1 fF. The words “limited to 1 fF” decide the method: the cap takes the place of MT23-5’s fixed $W_1$ .

The idea. Same method as MT23-5b (Part (b)): with nothing branching off the path, the product of the gains is fixed, so equal gains make their sum smallest. What is new is that you must choose the first gate’s size. The fixed product is the path effort (Chapter 8, Section 2):

F = G \cdot H, \qquad G = \prod g_i, \qquad H = \frac{C_{load}}{C_{in}}

$G$ is the cost of the gate types, and $H$ , the path’s electrical effort, is the load over the path’s input capacitance. It holds when nothing branches off the path. Here $H = 100\,\mathrm{fF}/C_{in}$ , so a larger input means a smaller $F$ and a faster path. The cap exists because the input is the load on whatever drives A, outside the path: without it you would make every gate huge and push the delay onto that driver.

MT21-5a

Use the whole input limit. Because $F$ falls as $C_{in}$ grows, take $C_{in} = 1$ fF, which is $W_1 + W_2 = 1\,\mu$ m. The balance $W_1 = W_2$ gives $W_1 = W_2 = 0.5\,\mu$ m.
The path effort. $G = 2 \cdot \tfrac32 \cdot 1 \cdot \tfrac32 = 4.5$ and $H = 100/1$ , so $F = 4.5 \times 100 = 450$ .
Equal gains. Four stages share it equally: $f = \sqrt[4]{450} = 4.606$ .
Size back from the load, because the load is the one capacitance known at the end. Write each gain as $g \cdot C_{out}/C_{in}$ , with $C_{in}$ the stage’s one-input capacitance: that is the same number as the load over the normalized inverter’s input, because one input is $g$ times that. NAND: $\tfrac32 \cdot 100/C_{NAND} = f$ gives $C_{NAND} = 32.57\,\mu$ m, so $W_7 = 21.7\,\mu$ m and $W_8 = 10.9\,\mu$ m.
Inverter: $1 \cdot 32.57/C_{inv} = f$ gives $C_{inv} = 7.07\,\mu$ m, so $W_5 = W_6 = 3.54\,\mu$ m.
NOR: $\tfrac32 \cdot 7.07/C_{NOR} = f$ gives $C_{NOR} = 2.30\,\mu$ m, so $W_3 = 0.77\,\mu$ m and $W_4 = 1.54\,\mu$ m.
The OAI checks the work. Its gain is $2 \cdot 2.30/1 = 4.61 = f$ . ✓ It has to be, because the four gains multiply to $F = f^4$ .
The delay. $4f\,\tau_{inv} = 18.42 \times 100\,\mathrm{ps} = 1.84$ ns.

Check. Use only half the limit, 0.5 fF, and $F$ doubles to 900: the delay becomes $4\sqrt[4]{900} = 21.9\,\tau_{inv}$ , 19% slower. The delay grows as $H^{1/4}$ , so the whole limit is worth taking, and it is the only thing that sets the first gate’s size.

Answer: $W_1 = W_2 = 0.5$ , $W_3 = 0.77$ , $W_4 = 1.54$ , $W_5 = W_6 = 3.54$ , $W_7 = 21.7$ , $W_8 = 10.9\,\mu$ m; delay $18.4\,\tau_{inv} \approx 1.84$ ns. Using the whole input limit is the lecture’s point that $C_{in}$ is set from outside the path (Chapter 8 §2).

Remember. When a question caps the input instead of fixing a width, $H = C_{load}/C_{in}$ is smallest at the cap: use all of it, then size back from the load as with a fixed first gate.

The answer key agrees

It gives the same sizes; it doesn’t state the delay.

Part (b): a 500 fF branch (20 points)

MT21-5b, p9. Now $C_B = 500$ fF. Find a sizing close to the minimum delay from A rising to Y rising (or falling to falling).

Hint

Nothing branches between the OAI and the NOR, and the OAI’s input is fixed. If only the NOR changes size, what stays fixed about their two gains?

What it asks. Hang 500 fF on the NOR’s output and resize for a delay close to the minimum. The OAI’s input stays at the 1 fF limit. “Close to the minimum” means that a sensible retuning, explained, is enough.

The idea. Same retuning as MT23-5d (Part (d)): the branch makes $F$ depend on the sizes, so $F^{1/4}$ is no longer the answer, but equal gains still hold on any piece of the path with nothing branching off it. What is different is the branch’s size: 500 µm against the inverter’s 7 µm, 99% of the NOR’s load. That decides which move pays (Chapter 8, Section 9).

Rebalance first. At (a)‘s sizes the NOR, sized for 7 µm, now drives 507 µm: its gain is 330. The lecture’s example enlarges the gate after the branch first, but its branch driver was already sized for the branch. Here enlarging the inverter first (to $W_5 = 15$ ) would add to that huge gain, to 345, and the delay would rise to $355.5\,\tau_{inv}$ , worse than doing nothing.
Then enlarge the gate after the branch: here it pays. Split the path at the branch (the split of step 4) added. The pair before it shares the product $3(2W_5 + 500)$ , the pair after it $75/W_5$ . Because the branch dominates, quadrupling the inverter raises the first product by only 4.5% (1521 to 1590) and divides the second by 4.2 (21.2 to 5). That is the lecture’s “drop this gain far more than I increase this gain” in its strongest form. In MT23-5d, where the branch was 39% of the load, the same move saved $0.14\,\tau_{inv}$ ; here it saves $3.0\,\tau_{inv}$ .

MT21-5b

See what the branch does at (a)‘s sizes. A side load adds only to the stage that drives its node, so only the NOR’s gain changes. It drives $7.07 + 500 = 507.07\,\mu$ m from its 2.30 µm input: gain $\tfrac32 \times 507.07/2.30 = 330$ . The delay is $3(4.61) + 330 = 344\,\tau_{inv} = 34.4$ ns. The branch is 99% of the NOR’s load.
Rebalance the pair before the branch. The OAI’s input is fixed and nothing branches between the OAI and the NOR, so while only the NOR moves, the product of their two gains stays at $2 \cdot \tfrac32 \cdot 507.07 = 1521$ . Equal factors give the smallest sum: $\sqrt{1521} = 39.0$ each. The OAI’s gain is $2C_{NOR}/1$ , so the NOR’s input is $39.0/2 = 19.5\,\mu$ m: $W_3 = 6.50\,\mu$ m and $W_4 = 13.0\,\mu$ m.
The delay now: $2(39.0) + 2(4.61) = 87.2\,\tau_{inv} = 8.72$ ns, already a factor of four better.
Split the path at the branch added. Because the inverter’s input is under 2% of the NOR’s load, enlarging it costs the NOR little and makes the last two stages cheap. With the inverter’s input $2W_5$ , the pair before the branch shares $3(2W_5 + 500)$ and the pair after it shares $\tfrac32 \cdot 100/2W_5 = 75/W_5$ .
The delay for a chosen W₅. A balanced pair with product $P$ contributes $2\sqrt{P}$ , so the delay is $2\sqrt{3(2W_5 + 500)} + 2\sqrt{75/W_5}$ .
Try a few widths. Growing the inverter raises the cost of the pair before the branch (its input adds to the NOR’s load) and lowers the cost of the pair after it; the best $W_5$ is where those two changes match. $W_5 = 3.54$ : 87.2. $W_5 = 7.5$ : 84.9. $W_5 = 15$ : 84.2. $W_5 = 30$ : 85.1. Take $W_5 = W_6 = 15\,\mu$ m.
The pair before the branch: $\sqrt{3 \times 530} = 39.9$ each. The NOR’s input is $39.9/2 = 19.9\,\mu$ m, so $W_3 = 6.65\,\mu$ m and $W_4 = 13.3\,\mu$ m.
The pair after it: $\sqrt{75/15} = 2.24$ each. The NAND’s input is $\tfrac32 \times 100/2.24 = 67.1\,\mu$ m, so $W_7 = 44.7\,\mu$ m and $W_8 = 22.4\,\mu$ m.
The delay: $2(39.9) + 2(2.24) = 84.2\,\tau_{inv} = 8.42$ ns.

Check. A floor. Whatever the sizes, the pair before the branch must carry a product of at least $2 \cdot \tfrac32 \cdot 500 = 1500$ , so it costs at least $2\sqrt{1500} = 77.5\,\tau_{inv}$ . No sizing reaches that, because the stages after the branch would have to cost nothing; 84.2 is within 9% of it.

Answer: $W_1 = W_2 = 0.5$ , $W_3 = 6.65$ , $W_4 = 13.3$ , $W_5 = W_6 = 15$ , $W_7 = 44.7$ , $W_8 = 22.4\,\mu$ m; delay $84.2\,\tau_{inv} \approx 8.42$ ns. That is the exact minimum to three figures. The rebalance of step 2 alone (8.72 ns, step 3) is already “close to the minimum”. Most of the delay is the cost of driving 500 fF from a 1 fF input, which no sizing removes.

Remember. With a heavy branch, first share the overloaded stage’s gain with the stage before it. Then enlarge the gate after the branch: the larger the branch’s share of the load, the more that move buys.

The answer key differs

It gives 9.16 ns, with $W_7 \approx 106$ , $W_5 = 84.27$ and $W_3 = 7.46\,\mu$ m. It minimizes its delay expression with partial derivatives. That is added calculus: the lecture says the retuning can be done exactly but usually “you just sort of look at it” (L08 52:20–53:19). Its algebra slips in two places.

Its final polynomial has 12 where $12 \times 12^2 = 1728$ belongs. With 1728 the root is $W_7 = 44.6\,\mu$ m, not 106.
Its $z = W_3 = 7.46$ balances only the first two stages. It does not satisfy its own $z = 12x^3/400^2$ , which gives about 89 at $x = 106$ .

Its sizes give $91.5\,\tau_{inv} = 9.15$ ns, 9% above the minimum. The method would earn credit; the numbers are off.

3. MT17-5: unequal strengths and a branch inverter (40 points)

The question (MT17-5, p10). A critical path through complementary static CMOS gates. Each gate is sized for balanced rise and fall, with the PFET having half the drive strength of the NFET. $C_g = 2$ fF/µm, $\tau_{inv} = 100$ ps, a minimum device is 1.0 µm, and $C_{load} = 1.2$ pF. Only gate capacitance counts.

Four stages from A to E: an inverter 2W1/W1; an AOI22 with PFETs 2W2 (two parallel pairs in series) and NFETs W2 (two series pairs in parallel), output C; a NAND2 with parallel PFETs W3 and series NFETs W3, output D; an inverter 2W4/W4 driving Cload at E. — MT17-5, p10 (source figure).

Reading the circuit

The same four gate types as MT23-5. What is different is the strength convention: the PFET has half the NFET’s drive ( $R_p = 2R_n$ ), so a PFET must be twice as wide to pull as hard, and every normalized inverter has the 2:1 shape.

Reading MT17-5 gate by gate

The reference inverter. With $R_p = 2R_n$ , an inverter pulls up as hard as it pulls down when its PFET is twice its NFET: 2W/W, input $3W$ . Its FO1 delay is the $\tau_{inv}$ the exam gives.
Stage 1, an inverter 2W₁/W₁. It is its own normalized inverter: input $3W_1$ , $g = 1$ .
Stage 2, the AOI22: NFETs $W_2$ , PFETs $2W_2$ . When one input switches, two NFETs in series pull down, like one NFET of $W_2/2$ , and two PFETs in series pull up, like one PFET of $W_2$ (half of $2W_2$ ). So it drives like a $W_2$ over $W_2/2$ inverter, 2:1 as required, input $1.5W_2$ . One input drives one NFET and one PFET, $W_2 + 2W_2 = 3W_2$ , so $g = 3W_2/1.5W_2 = 2$ .
Stage 3, the NAND2: every device $W_3$ . Its NFETs are in series and act like $W_3/2$ ; one PFET, $W_3$ , pulls up alone. $W_3$ over $W_3/2$ is again 2:1, so the gate is balanced, and its normalized inverter’s input is $1.5W_3$ . One input drives $W_3 + W_3 = 2W_3$ , so $g = 2/1.5 = 4/3$ . That is less than the 3/2 of equal strengths, because the NAND’s stacked devices are now the strong ones.
Stage 4, an inverter 2W₄/W₄: input $3W_4$ , $g = 1$ .
The load. $C_g$ is 2 fF/µm here, not 1: $1.2\,\mathrm{pF}/(2\,\mathrm{fF/\mu m}) = 600\,\mu$ m of gate.

Stage	Gate	Devices	Normalized inverter	One input	$g$
1	inverter	2W₁/W₁	input $3W_1$	$3W_1$	1
2	AOI22	NFETs W₂, PFETs 2W₂, stacks of two in both	W₂ over W₂/2, input $1.5W_2$	$3W_2$	2
3	NAND2	NFETs W₃ in series, PFETs W₃ in parallel	W₃ over W₃/2, input $1.5W_3$	$2W_3$	4/3
4	inverter	2W₄/W₄	input $3W_4$	$3W_4$	1

The AOI22 is the gate of Chapter 8’s check (§1).

Part (a): the delay as drawn (10 points)

MT17-5a, p10. Estimate the A-to-E delay with every $W_i = 1.0\,\mu$ m.

Hint

The table gives each stage’s normalized input and the input it presents to the stage before. Which stage drives the 600 µm?

What it asks. The delay of the path exactly as drawn, with every $W_i$ at 1 µm. The drawn factors still apply: the inverters’ PFETs are 2 µm.

The idea. Same method as MT23-5a (Part (a)): each stage takes $\tau_{inv}$ times its gain, the capacitance it drives over its normalized inverter’s input, and the path delay is $\tau_{inv}$ times their sum. Only the table changes with the 2:1 convention: an inverter’s input is $3W$ , and a gate’s one input is larger than its normalized input by its $g$ .

MT17-5a

Stage 4 drives the 600 µm load from its normalized input $3W_4 = 3\,\mu$ m: gain $600/3 = 200$ .
Stage 3 drives stage 4’s input, $3W_4 = 3\,\mu$ m, from $1.5W_3 = 1.5\,\mu$ m: gain $2$ .
Stage 2 drives one NAND input, $2W_3 = 2\,\mu$ m, from $1.5W_2 = 1.5\,\mu$ m: gain $1.33$ .
Stage 1 drives one AOI input, $3W_2 = 3\,\mu$ m, from $3W_1 = 3\,\mu$ m: gain $1$ .
Add. Delay $= (1 + 1.33 + 2 + 200) \times 100\,\mathrm{ps} = 204.3 \times 100\,\mathrm{ps}$ .

Check. The last stage is 200 of the 204.3, 98% of the delay: a 3 µm-input inverter driving 600 µm is driving 200 copies of itself. In units, $204.3 \times 100$ ps is 20.4 ns.

Answer: $204.3\,\tau_{inv} \approx 20.4$ ns.

Remember. With $R_p = 2R_n$ , the inverter’s input is $3W$ and every normalized inverter is 2:1. After that, the gains are read exactly as with equal strengths.

The answer key agrees

It writes “Stage 1: gain = 3/2 = 1”. The fraction should be 3/3; its result, 1, is right.

Part (b): equal-gain sizing (10 points)

MT17-5b, p11. $W_1$ is fixed at 1.0 µm; tune $W_2$ , $W_3$ and $W_4$ for minimum delay, and estimate the new delay.

Hint

Write the four gains with

W_2

W_3

and

W_4

as unknowns and multiply them. What is left?

What it asks. Choose $W_2$ , $W_3$ and $W_4$ for the smallest delay, with the first inverter fixed at 1 µm, and give the new delay.

The idea. Same method as MT23-5b (Part (b)): the inner widths cancel in the product of the gains, which leaves a fixed path effort $F = G \cdot H$ ; with a fixed product, equal gains $f = F^{1/4}$ give the smallest sum; size back from the load. New here: $G = 1 \cdot 2 \cdot \tfrac43 \cdot 1 = 8/3$ and $H = 600/3W_1 = 200$ . Keep $4/3$ as a fraction until the end.

MT17-5b

The gains, with the widths unknown: $\dfrac{3W_2}{3W_1}$ , $\dfrac{2W_3}{1.5W_2}$ , $\dfrac{3W_4}{1.5W_3}$ , $\dfrac{600}{3W_4}$ .
Their product. Each inner width appears once on top and once underneath, and cancels: $F = \dfrac{1600}{3W_1} = 533.3$ . That is $G \cdot H = \tfrac83 \times 200$ , and also (a)‘s gains multiplied: $1 \times \tfrac43 \times 2 \times 200$ .
Equal gains: $f = \sqrt[4]{533.3} = 4.806$ .
Size back from the load, because the last equation has only one unknown: $600/3W_4 = f$ gives $W_4 = 41.6\,\mu$ m.
$3W_4/1.5W_3 = f$ gives $W_3 = 17.3\,\mu$ m.
$2W_3/1.5W_2 = f$ gives $W_2 = 4.81\,\mu$ m.
Stage 1 checks the work: $W_2/W_1 = 4.81 = f$ . ✓
The delay: $4f\,\tau_{inv} = 19.22 \times 100\,\mathrm{ps} = 1.92$ ns.

Check. From 20.4 ns to 1.92 ns: about 10.6 times faster, from resizing alone. A gain of 4.8 per stage is a little above the 3–4 that Chapter 8 aims for (Section 4), so four stages are about right for this load.

Answer: $W_2 = 4.81$ , $W_3 = 17.3$ , $W_4 = 41.6\,\mu$ m; delay $19.2\,\tau_{inv} \approx 1.92$ ns.

Remember. The strength convention changes only the table; the recipe ( $F$ , $f = F^{1/4}$ , back from the load, stage 1 checks) is the same.

The answer key agrees

It gives $F = 532$ , because it multiplies by 1.33 instead of $4/3$ ; the exact value is 533.3. Its rounded widths (41.7, 17.4, 4.8 µm) and its 1.92 ns are fine. Its stage-1 line writes “3W₃/2W₁” for $3W_2/3W_1$ .

Part (c): a branch inverter (10 points)

MT17-5c, p12. The circuit is modified as shown. What is the delay with the sizes of (b)?

The same path with an extra inverter, PFET 16 um and NFET 8 um, whose input hangs on node C and whose output drives 400 fF. — MT17-5c, p12 (source figure). A 16 µm/8 µm inverter, driving 400 fF, hangs on node C.

Hint

The new inverter brings two capacitances: its own input, on node C, and the 400 fF it drives. Which one does the signal from A to E have to charge?

What it asks. An inverter (PFET 16 µm, NFET 8 µm) driving 400 fF is hung on node C. Keep (b)‘s sizes and find the new delay. Two readings decide it: which node, and which part of the new inverter loads the path.

The idea. Same rule as MT23-5c (Part (c)): a side load raises only the gain of the stage that drives its node. What is new is that the side load is a gate, not a capacitor. Node C sees only that gate’s input, $16 + 8 = 24\,\mu$ m of gate. The 400 fF sits on the branch inverter’s own output. Charging it is that inverter’s job, on the path from C to its output; the A-to-E signal passes C into the NAND and never waits for it. Counting the 400 fF on node C is the trap.

MT17-5c

Find the node. The new inverter’s input is wired to C, the output of stage 2 (the AOI).
Count its input only. Its gates are $16 + 8 = 24\,\mu$ m. Its own 400 fF load is behind it, off the A-to-E path, so it doesn’t count here.
Stage 2’s new gain. It now drives $2W_3 + 24 = 34.6 + 24 = 58.6\,\mu$ m from $1.5W_2 = 7.21\,\mu$ m: gain $8.14$ , up from 4.81.
The other three gains stay at 4.81, because their loads and their sizes haven’t changed.
The delay: $(3 \times 4.806 + 8.14) \times 100\,\mathrm{ps} = 22.55 \times 100\,\mathrm{ps}$ .

Check. The delay rose by $22.55 - 19.22 = 3.33\,\tau_{inv}$ , exactly the rise in stage 2’s gain ( $8.14 - 4.81$ ): nothing else moved. The branch is 41% of stage 2’s load, and the branching effort at C is $b = 58.6/34.6 = 1.69$ (Chapter 8, Section 8).

Answer: $22.6\,\tau_{inv} \approx 2.26$ ns.

Remember. A gate hung on a node loads it with its input only; whatever that gate drives is off the path.

The answer key agrees

It gets 8.17 for stage 2’s gain, from its rounded widths (17.4 and 4.8 µm), and the same 2.26 ns.

Part (d): retuning (10 points)

MT17-5d, p13. Keeping $W_1$ fixed, resize to reduce the delay of (c) and compute the new delay. The minimum isn’t required.

Hint

Suppose you make the AOI bigger until its own gain is back to 4.81. What happens to the gain of the inverter that drives it?

What it asks. With $W_1$ still fixed, resize to bring the delay of (c) down, and compute it. A sensible retuning, explained, is enough.

The idea. Same retuning as MT23-5d (Part (d)): the branch makes $F$ depend on the sizes, but equal gains still hold on each piece with nothing branching off it. The branch is 41% of stage 2’s load, close to MT23-5’s 39%, so as there, rebalance first: enlarging the NAND alone (to $W_3 = 21.6\,\mu$ m) would raise the delay to $22.79\,\tau_{inv}$ . The new thing here is the trap the key falls into: resizing only the stage that drives the branch. That stage’s input is stage 1’s load. While only $W_2$ moves, the product of the two gains is fixed, so a larger $W_2$ only shifts gain from stage 2 to stage 1; the best split is the equal one (Chapter 8, Section 9).

MT17-5d

The trap, worked out. Resizing only stage 2 so that its own gain is back to 4.81 needs $W_2 = 58.6/(1.5 \times 4.806) = 8.14\,\mu$ m. But stage 1 drives $3W_2$ , so its gain becomes $8.14$ . The delay is still $22.55\,\tau_{inv}$ : the excess gain just moved one stage back (Chapter 8 §9).
Rebalance instead. Because $W_1$ and $W_3$ are fixed and nothing branches between stages 1 and 2, their product is fixed: $W_2 \cdot \dfrac{58.6}{1.5W_2} = 39.1$ . Split it equally: $\sqrt{39.1} = 6.25$ each, so $W_2 = 6.25\,\mu$ m.
The delay now: $2(6.25) + 2(4.81) = 22.12\,\tau_{inv} = 2.21$ ns.
Then enlarge the gate after the branch added. Split the path at the branch, as in MT23-5d. Stages 3 and 4 share $\dfrac{2W_4}{W_3} \cdot \dfrac{200}{W_4} = \dfrac{400}{W_3}$ ; stages 1 and 2 share $(2W_3 + 24)/1.5$ . Balancing each pair gives a delay of $2\sqrt{(2W_3 + 24)/1.5} + 2\sqrt{400/W_3}$ .
Try a few widths. $W_3 = 17.3$ : 22.12. $W_3 = 20$ : 22.01. $W_3 = 21.6$ : 21.99. $W_3 = 25$ : 22.05. Take $W_3 = 21.6\,\mu$ m.
The widths. $W_2 = \sqrt{(43.2 + 24)/1.5} = 6.69\,\mu$ m, and stage 4’s gain is $\sqrt{400/21.6} = 4.30$ , so $W_4 = 200/4.30 = 46.5\,\mu$ m.
The delay: $2(6.69) + 2(4.30) = 21.99\,\tau_{inv} = 2.20$ ns.

Check. The trap’s two gains, 8.14 and 4.81, multiply to 39.1, the same product as 6.25 × 6.25. With the product fixed, the unequal pair sums to 12.9 and the equal pair to 12.5: that difference is all that step 2 gains, and the trap gains nothing.

Answer: $W_2 = 6.25\,\mu$ m gives 2.21 ns; with $W_3 = 21.6$ and $W_4 = 46.5\,\mu$ m as well, $W_2 = 6.69\,\mu$ m and the delay is $22.0\,\tau_{inv} \approx 2.20$ ns, the minimum. The branch is only 41% of stage 2’s load, so the gain is small: the 1.92 ns of (b) cannot come back.

Remember. Never fix a branch by resizing only the stage that drives it: its input is the load of the stage before. Rebalance that pair, then try a larger gate after the branch.

The answer key differs

It resizes stage 2 to a gain of 4.8 ( $W_2 = 8.17\,\mu$ m) and says that the “delay is now back to 1.92 nsec”. That is the trap of step 1: stage 1’s gain becomes 8.17, so the delay stays at 2.26 ns. Its closing remark, that more can come from sizing up stages 3 and 4, points the right way.

4. Retune it yourself

The widget sizes each of the three paths the way the steps above do. Pick the size of the gate just after the branch; the stages before the branch then share one equal gain, and the stages after it share another. The curve is the delay for every such choice. Its lowest point is the exact minimum with the first gate fixed.

input of the NAND2 after the branch38.7 µm

delay Σ gains: 28.41 τ_inv = 1.421 ns
gains, stage 1 to 4: 7.98 · 7.98 · 6.22 · 6.22
branching factor at stage 2: 1.65
part (c): sizes of (b): 28.91 τ_inv
lowest point: 28.27 τ_inv at 47.8 µm
AOI22: W₂: 7.98 µm
NAND2: W₃: 12.91 µm
inverter: W₄: 80.34 µm

What to notice.

At the (b) or (a) sizes, the curve already gives the “rebalance the pair” delay. For MT21-5 that single move removes 75% of the delay.
The curves are flat near their minima: an approximate size is enough, as the exam asks.
MT21-5’s best inverter is several times its (a) size, because the branch dominates the NOR’s load. MT17-5’s and MT23-5’s branches are smaller (41% and 39% of the load), and the best gate after the branch grows only by about 25%.

added Splitting a path at its branch is this guide’s way of organizing the lecture’s two moves (enlarge the gate after the branch, then rebalance). Each piece is an ordinary path with nothing branching off it, so Chapter 8’s equal-gain rule applies to it.

Patterns

Path sizing in one box. The reasons are in How to approach a path-sizing question.

Read the circuit first: the strength convention (W/W or 2W/W), each gate’s normalized input and one-input capacitance, the load in µm of gate, and the node a side load hangs on.
(a) Gains as drawn, delay $= \tau_{inv}\sum$ gains. (b) $F$ , $f = F^{1/4}$ , size back from the load, and let stage 1 check the arithmetic. (c) Recompute only the gain of the stage that drives the branch.
(d) Rebalance the overloaded stage with the one before it, then try a larger gate after the branch. That second move pays most when the branch is most of the load (MT21-5b).
Traps: the branch on the wrong node (MT23-5c’s key); ps against ns (MT23-5b–d’s keys); resizing only the stage that drives the branch (MT17-5d’s key); treating a recomputed $F$ as fixed (MT23-5d’s key); counting what a branch gate drives instead of its input (MT17-5c).
No exact minimum is needed. The lecture retunes by inspection; three or four widths in the two-pair formula are enough.
Time. About 15–20 minutes for 35–40 points. Parts (a)–(c) are mechanical (3–4 minutes each). Spend the rest on (d), and explain the move in words: the exams give partial credit for the reasoning.