M2. Formula sheet

Every past midterm is closed book and closed notes: five questions in 75 minutes. Nothing on this page will be in front of you in the exam; it is what to have in your head when you walk in. It collects the “formulas to remember” boxes of Chapters 3–12, and the few results from Chapters 0–2 that the midterms use, and arranges them by the question families of the four past midterms. Each formula comes with what it means, when it holds, and the chapter section that derives it and works examples. Every number on the page is recomputed in the guide’s checks.

After this page you can:

1. state the conventions an answer must declare (device strength, the 0.69 factor, energy per cycle or per transition) and convert the exams’ units without slips;
2. tell from what a question gives you which model it wants: square law, velocity saturation, transit time, RC with $R$ in kΩ·µm, logical effort or dynamic logical effort;
3. write the formulas of each exam family from memory, with the conditions under which they hold;
4. recognize the mistakes that cost points, including the ones in the past answer keys.

Before you start

How to use this page. Read the conventions first: most of the answer keys’ errors come from mixing them. Section 1 has the units and numbers, Section 2 the choice of model. Sections 3–9 are the formula tables, one per exam family, roughly in order of their weight on the past exams (page M1 has the counts). Section 10 collects the common mistakes. A row marked added is the guide’s addition, not something the lecture wrote on the board.

Practise recall. The button covers the formula column of every table (the value column in Section 1). Read the meaning, write the formula on scrap paper, then tap the cell to check.

Cover every formula

The formula cells are visible. Cover them to practise recall.

Where the problems are worked. Inverter chains, noise margins, gate delays and the device short answers: M3. Path sizing: M4. Pass transistors and stick layouts: M5. Dynamic and domino logic: page M6. A practice exam: page M7. What to expect and a study plan: page M1.

Scope. The midterm covers historical Lectures 1–11 and Lecture 12 up to 23:15 (Chapters 1–12): domino precharge and evaluate and delayed-reset clocks are in; latches, flip-flops and sequential timing are out.

Conventions the exams use

State the ones that apply at the top of your answer. The questions mix them, and so do the keys.

Convention	The choices	Where the exams use each
Device strength	$R_{pfet} = 2R_{nfet}$2Rnfet​: balanced inverter 2W/W, input $3W$3W, $\tau_{inv} = 3R_{nfet}C_g$3Rnfet​Cg​, $g_{NAND2} = 4/3$4/3, $g_{NOR2} = 5/3$5/3. Equal strengths: W/W, input $2W$2W, $\tau_{inv} = 2R_{nfet}C_g$2Rnfet​Cg​, $g_{NAND2} = g_{NOR2} = 3/2$	equal: MT17-3, MT21-2, MT21-5, MT23-5, MT24-2, MT24-5. $R_{pfet} = 2R_{nfet}$2Rnfet​: MT17-5, MT21-4, MT23-1, MT23-3
A device’s delay	$(R/W)\,C$(R/W)C, with no $\ln 2$ln2: $R$ is defined from the measured 50% delay. Use $0.69RC$ only when a question asks for it	MT23-3b’s key uses 0.69; MT24-2c’s key accepted both
Energy	per cycle: every node rises once. Per transition: only the nodes that rise on that input edge	per cycle: MT23-1a, MT24-2a. Per transition: MT17-4c, MT21-4b
Currents	per µm of width; leakage only through the device that is off, with $V_{DD}$ across it	MT23-1b, MT24-2b
Delay unit	$\tau_{inv}$τinv​, the FO1 delay: given in ps in path problems, built from $R$ and $C_g$ in chain problems	25 ps MT21-4; 50 ps MT23-5, MT24-5; 100 ps MT17-5, MT21-5
Loads	microns of gate, $C/C_g$	1 fF/µm MT21-5, MT23, MT24; 2 fF/µm MT17-3, MT17-5, MT21-4 and the lecture’s examples
Logic levels	symbolic: $V_{DD} - V_{Tn}$VTn​, $2\lvert V_{Tp}\rvert$2∣VTp​∣, not numbers	MT21-1b, MT23-2c

1. Units and constants

The exams work in µm, fF, kΩ·µm, ps and V; device physics works in cm (Chapter 0, Section 1). Three products do most of the work: kΩ × fF is ps, fF × V² is fJ, and a load in fF divided by $C_g$ is microns of gate.

Product	Value	Use
$1\,\mathrm{k\Omega} \times 1\,\mathrm{fF}$	1 ps	every RC delay: $(R/W)\,C$ with $R$ in kΩ·µm, $W$ in µm, $C$ in fF
$1\,\mathrm{fF} \times (1\,\mathrm{V})^2$	1 fJ	switching energy $CV_{DD}^2$
$1\,\mathrm{nA} \times 1\,\mathrm{V} \times 1\,\mathrm{ps}$	$10^{-21}$ J $= 10^{-6}$ fJ	leakage energy $V_{DD}I_{off}T$
$1\,\mu\mathrm{A} \times 1\,\mathrm{V} \times 1\,\mathrm{ns}$	1 fJ	the same in larger units
$1\,\mathrm{mA} \times 1\,\mathrm{V}$	1 mW	static power $V_{DD}I$
$C/C_g$	µm of gate	1 pF is 1000 µm at 1 fF/µm; at 2 fF/µm, 1.2 pF is 600 µm and 50 fF is 25 µm
$f = 1/T$	2 ns ↔ 500 MHz	a clock period and its frequency
1 µm, 1 nm	$10^{-4}$ cm, $10^{-7}$ cm	device physics in cm

Constant	Value	Notes
$kT/q$	25.9 mV at 300 K (about 26 mV)	proportional to the absolute temperature
$\frac{kT}{q}\ln 10$	59.5 mV at 300 K (the “60 mV per decade”); 79.4 mV at 400 K	the best subthreshold slope; the diode’s mV per decade
$E_g$Eg​, $n_i$	1.1 eV; $10^{10}\,\mathrm{cm^{-3}}$	silicon at 300 K
$q$q, $\varepsilon_0$	$1.6\times10^{-19}$ C; $8.85\times10^{-14}$ F/cm
$\kappa_s$κs​, $\kappa_{ox}$	11.7, 3.9	silicon, oxide
$v_{sat}$	about $10^7$ cm/s (electrons), $5\times10^6$ cm/s (holes)
$\mathcal{E}_{crit}$	about $10^4$ V/cm	the velocity-saturation fit
$\ln 2$	0.69	an RC’s 50% point; only if asked
$e$	2.72	the best gain per stage of an inverter chain

The exams’ technology numbers. The questions give these, but recognizing them saves time and catches slips.

Quantity	Typical value	Exams
$C_g$	1 fF/µm (2 fF/µm in the older exams and the lecture)	MT21-5, MT23, MT24 (MT17, MT21-4)
$R_{nfet}$Rnfet​, $R_{pfet}$	1 kΩ·µm; $R_{pfet}$ = 2 kΩ·µm or equal	MT23-1, MT23-3, MT24-2
$V_{DD}$	1.2 V (2.5 V in MT17 and MT21-4)	MT23-1, MT24-2
Subthreshold	10 µA/µm at $\lvert V_T\rvert$ = 200 mV, 90 mV/decade, so 59.9 nA/µm at $V_{GS} = 0$	MT23-1b, MT24-2b
Side load	4 fF on every node of the chain	MT23-1, MT24-2
$\tau_{inv}$τinv​, $C_{load}$Cload​, minimum width	50 ps, 1 pF, 1.0 µm	MT23-5, MT24-5 (MT17-5: 100 ps, 1.2 pF)
The lecture’s illustrations	$V_{DD}$ = 5 V, $V_{Tn} = \lvert V_{Tp}\rvert$ = 1 V	Chapters 6 and 10, and page M5’s levels
Transit time	$\tau_{tr}$ = 2.5 ps at $L$ = 0.25 µm ($f_T$fT​ = 63.7 GHz); $\eta = C_g/C_d$ about 1.5–2	Chapter 5

2. Which model applies when

The course has several models for the same transistor. Each question is built for one of them, and what it gives you says which.

The question gives	Use	Taught in
$R$ in kΩ·µm, $C_g$ in fF/µm and widths	RC: $(R/W)\,C$	Ch 7 §2
$\tau_{inv}$ in ps and a path of static gates	logical effort: $\tau_{inv}\sum g_ih_i$	Ch 8 §2
a dynamic or domino path and $\tau_{inv}$	dynamic logical effort	Ch 12 §2
$\tau_{tr}$ (or $L$ and $v_{sat}$vsat​) and $\eta = C_g/C_d$	transit-time estimates	Ch 5 §13
a current at threshold and a slope in mV/decade	the subthreshold exponential	Ch 4 §11
$\mu$μ, $C_{ox}$Cox​, $W/L$ and a long channel; or a transfer curve to sketch	the square law	Ch 4 §4, Ch 6 §2
$v_{sat}$ and a short channel	the velocity-saturated current	Ch 4 §7

Square law (long channel)board

$$I_{DSAT} = \frac{\mu C_{ox}}{2}\,\frac{W}{L}\,(V_{GS} - V_T)^2$$$$V_{DSAT} = V_{GS} - V_T$$

Use it for the transfer curve’s shape and regions, the noise-margin reasoning, and the pseudo-NMOS low level. Doubling the overdrive quadruples the current; halving $L$ doubles it. Ch 4 §4, Ch 6 §2, Ch 10 §10.

Holds when: v_drift = μℰ along the whole channel: long channels, (V_GS − V_T)/L ≪ ℰ_crit/2; V_GS > V_T

Velocity saturationboard

$$I_{DSAT} = C_{ox}Wv_{sat}(V_{GS} - V_T)\,\frac{s - 1}{s + 1}$$$$s = \sqrt{1 + \frac{2\mu(V_{GS} - V_T)}{v_{sat}L}}$$$$V_{DSAT} = \frac{2(V_{GS} - V_T)}{1 + s}$$$$\text{limit: } I_{DSAT} = C_{ox}Wv_{sat}(V_{GS} - V_T)$$

Saturation comes earlier and lower than in the square law. Use it for short-channel currents, $g_m = WC_{ox}v_{sat}$ and $f_T = v_{sat}/(2\pi L)$vsat​/(2πL). In the limit the current is linear in the overdrive and independent of $L$ and $\mu$μ. It approaches the limit slowly: $(s - 1)/(s + 1)$ is only 0.46 at 6.4 times the critical field. Ch 4 §7, Ch 5 §10.

Holds when: the drift velocity follows μℰ/(1 + ℰ/ℰ_crit); the limit holds when (V_GS − V_T)/L ≫ ℰ_crit/2, which the lecture says is true from 0.25 µm down

Transit timeboard

$$\tau_{tr} = \frac{L}{v_{sat}}$$$$t = \frac{V_{DD}(C_g + C_d)}{I_{DSAT}} = \tau_{tr}\Bigl(1 + \frac{1}{\eta}\Bigr)$$$$\mathrm{FO1} = 3\tau_{tr}\Bigl(1 + \frac{1}{\eta}\Bigr)$$$$\mathrm{FO4} = 3\tau_{tr}\Bigl(4 + \frac{1}{\eta}\Bigr)$$

Use it for FO1 and FO4 from device numbers (MT21-2). The driver’s own drain capacitance does not grow with the fan-out, so FO4 is $\frac{1 + 4\eta}{1 + \eta}$ FO1, not 4 FO1. At $\tau_{tr}$ = 2.5 ps and $\eta = 2$2: 11.25 and 33.75 ps (2W/W), 7.5 and 22.5 ps (W/W). Ch 5 §11–13.

Holds when: fully velocity-saturated devices with V_DD ≫ V_T; η = C_g/C_d; wires ignored; PFET 2W for equal drive (factor 3), or W/W at equal strengths (factor 2)

RC with R in kΩ·µmboard

$$t = \frac{R}{W}\,C_{load}$$$$C_{load} = C_g \times (\mu\mathrm{m\ of\ gate}) + C_{side}$$

Use it for inverter chains (MT24-2, MT23-1, MT21-4, MT17-4), a dynamic gate’s evaluate delay (MT17-3c, MT23-3b), a pass transistor with its driver (Ch 11 §2), and the level of a fight in ratioed logic as a divider (Ch 10 §9, MT21-3). Series devices add their $R/W$R/W: $k$ equal devices act like one $k$ times narrower. Ch 7 §1–2.

Holds when: R is a fitted constant (measured delay over load), so no ln 2; gate loading only, unless the question adds drain or wire capacitance

Logical effortboard

$$\text{Delay} = \tau_{inv}\sum_i g_ih_i$$$$F = GHB, \qquad f = F^{1/N}$$

Use it for paths (MT23-5, MT21-5, MT17-5) and single gates in units of $\tau_{inv}$ (MT17-3). It is the RC model counted in $\tau_{inv}$τinv​: a stage’s $g \cdot h \cdot \tau_{inv}$ equals $(R_{nfet}/W_{eq})\,C_{out}$(Rnfet​/Weq​)Cout​, with $W_{eq}$ the NFET of its normalized inverter. Ch 7 §9, Ch 8 §2–3.

Holds when: complementary static gates sized for balanced edges; τ_inv given; gate loading only; the first input and the load fixed

Dynamic logical effortadded

With $R_{pfet} = 2R_{nfet}$2Rnfet​:

$$\text{n-type: } g = \frac{k}{3}$$$$\text{p-type: } g = \frac{2k}{3}$$

At equal strengths, both types:

$$g = \frac{k}{2}$$

Use it for domino and NP-domino paths (MT24-5, MT23-3b as a cross-check, MT17-3c), together with the skewed inverter’s rising-edge effort (3/4 for an 8:1 inverter). The board has the n-type cases $k = 2$ (2/3) and $k = 1$ (1/3). Ch 12 §2, §6.

Holds when: only the edge that carries the logic (an n node falls, the domino output rises); k counts the footer or header; the precharge device never counts; drain capacitance ignored

Subthreshold exponential

$$I_D = I(V_T)\cdot 10^{(V_{GS} - V_T)/S}$$$$S = m\,\frac{kT}{q}\ln 10$$

Use it for the leakage per µm at $V_{GS} = 0$ (MT23-1b, MT24-2b: 59.9 nA/µm) and its change with temperature (MT17-1c: $2.15\times10^{-22}$ A at 300 K, $3.16\times10^{-18}$ A at 400 K). Ch 4 §11.

Holds when: V_GS below V_T; the slope S scales with the absolute temperature (60 mV/decade at 300 K for the ideal m = 1)

Check yourself One question gives R_nfet = 1 kΩ·µm, C_g = 1 fF/µm and a chain of W/W inverters with 4 fF side loads; another gives τ_inv = 50 ps and four static gates. Which model does each want, and how are they related?

The first is the RC model: each stage takes $(R_{nfet}/W)(2W \cdot 1\,\mathrm{fF/\mu m} + 4\,\mathrm{fF})$ ps. The second is logical effort: $50\,\mathrm{ps} \times \sum g_ih_i$∑gi​hi​. They are the same model in different units: with equal strengths $\tau_{inv} = 2R_{nfet}C_g = 2$ ps for the first technology, and a stage’s $g \cdot h \cdot \tau_{inv}$ is its $(R/W_{eq})\,C_{out}$(R/Weq​)Cout​.

Check yourself FO4 is 4τ_inv in one of the course's models and 3 FO1 in another (at η = 2). Which is which, and why do they differ?

With gate loading only (the RC model of Chapter 7), the load and so the delay scale with the fan-out: FO4 $= 4\tau_{inv}$4τinv​. The transit-time model of Chapter 5 also counts the driver’s own drain capacitance, which does not grow with the fan-out: FO4 $= \frac{1 + 4\eta}{1 + \eta}$ FO1, which is 3 FO1 at $\eta = 2$ (33.75 ps against 11.25 ps at $\tau_{tr}$ = 2.5 ps).

3. Inverter chains: energy, leakage and delay

Every past midterm has this question: MT24-2, MT23-1, MT21-4 and MT17-4, worked in M3, Sections 1–4. Write the node capacitance first; every part uses it.

Formula	Meaning, and when it holds	Taught in
$C_{node} = C_g(W_n + W_p) + C_{side}$	the next inverter’s input plus any side load or wire; drain capacitance only if the question includes it	Ch 7 §2
$t_{pHL} = \dfrac{R_{nfet}}{W_n}C_{node}$Wn​Rnfet​​Cnode​, $t_{pLH} = \dfrac{R_{pfet}}{W_p}C_{node}$	each stage’s delay; a chain alternates falling and rising edges, and a balanced inverter makes them equal	Ch 7 §2
$\tau_{inv} = 3R_{nfet}C_g$ (2W/W); $2R_{nfet}C_g$ (W/W)	the FO1 delay; the same for every $W$W; FO4 = $4\tau_{inv}$ in this model	Ch 7 §7
$E = CV_{DD}^2$ per rising node	drawn from the supply: half stored, half heat; a falling node draws nothing	Ch 6 §6
$E_{cycle} = N\,C_{node}V_{DD}^2$	every node rises once per cycle; per transition only the nodes that rise on that edge count (about half)	Ch 6 §6
$P = CV_{DD}^2 f$	dynamic power; $f$ counts full cycles, not edges	Ch 6 §6
$I_{off} = I(V_T)/10^{V_T/S}$	leakage per µm at $V_{GS} = 0$0: 10 µA/µm, 200 mV and 90 mV/decade give 59.9 nA/µm	Ch 4 §11
$E_{leak} = N\,V_{DD}\,I_{off}\,\bar W_{off}\,T$	only the off device leaks, with $V_{DD}$ across it; at a 50% duty cycle the average off width $\bar W_{off}$ is $1.5W$ (2W/W) or $W$ (W/W)	Ch 6 §6, M3 §1
$\dfrac{E_{leak}}{E_{dyn}} = \dfrac{\bar W_{off}}{W}\cdot\dfrac{N\,I_{off}R_{nfet}}{V_{DD}}$	with $T$ equal to the chain delay of balanced inverters; $W$ and the side load cancel: $5.0\times10^{-5}N$ (W/W), $7.5\times10^{-5}N$ (2W/W) at the exam numbers. The share of the total is $x/(1 + x)$ added	M3 §1–2
$(1 + p)\,W^*C_g = C_{side}$	energy × delay is least where the gates’ load equals the fixed load: $W^*$ = 2 µm (W/W) and 4/3 µm (2W/W) with 4 fF at 1 fF/µm added	M3 §1
delay $\to N\tau_{inv}$ as $W \to \infty$	the delay alone has no finite optimum; at $W^*$ it is twice that floor	M3 §1
$W_p/W_n = \sqrt{R_{pfet}/R_{nfet}}$	the PFET ratio that minimizes a chain’s rise plus fall delay, each inverter driving a copy: $\sqrt2$ for $R_{pfet} = 2R_{nfet}$2Rnfet​, 1 at equal strengths added	M3 §3

4. Gate delays and path sizing

Paths: MT23-5, MT21-5 and MT17-5, worked in M4. Single gates in units of $\tau_{inv}$τinv​: MT17-3, worked in M3 §7. MT24 moved its sizing into a dynamic path (Section 6).

Formula	Meaning, and when it holds	Taught in
$C_g/W = L\kappa_{ox}\varepsilon_0/t_{ox} \approx 2$ fF/µm	gate capacitance per micron of width; roughly constant from one generation to the next	Ch 7 §2
bench 1: $C_g = C_L/(8(16 + 8)\,\mu\mathrm{m})$8)μm); bench 2: $R_{nfet} = \dfrac{t_{pHL}}{C_L}4(8\,\mu\mathrm{m})$CL​tpHL​​4(8μm), $R_{pfet} = \dfrac{t_{pLH}}{C_L}4(16\,\mu\mathrm{m})$	extracting $C_g$ and $R$ in simulation: $C_L$ that matches an 8(16/8) input; then $C_L = C_g \cdot 16(16 + 8)$ µm with AS = AD = PS = PD = 0	Ch 7 §3
$\overline{A + B}$A+B​, $\overline{AB}$AB, $\overline{AB + CD}$	NOR, NAND, AOI22: complementary static gates, the PUN the dual of the PDN	Ch 7 §4–5
stack of $n$n: each device $n\times$ wider	the same drive as the inverter; parallel devices are sized for one of them on alone	Ch 7 §8
$g = C_{in,\,gate}/C_{in,\,inv}$	logical effort: one input’s capacitance over the input of the inverter with the same drive	Ch 7 §8
$g_{NAND2} = 4/3$4/3, $g_{NOR2} = 5/3$	$R_{pfet} = 2R_{nfet}$2Rnfet​: NAND NFETs $2W$ and PFETs $2W$2W; NOR NFETs $W$ and PFETs $4W$4W; inverter input $3W$	Ch 7 §8
$g_{NAND2} = g_{NOR2} = 3/2$	equal strengths: inverter W/W, input $2W$	M4
$g_{AOI22} = g_{OAI22} = 2$	either convention	M4
$g_{NANDn} = \frac{n + 2}{3}$3n+2​, $g_{NORn} = \frac{2n + 1}{3}$32n+1​; equal strengths $\frac{n + 1}{2}$	$n$ inputs, from the stack rule added	Ch 7 §8
gain $= g \cdot h = \dfrac{C_{out}}{C_{in,\,\text{norm. inv.}}}$	one stage’s delay in $\tau_{inv}$τinv​; $h = C_{out}/C_{in}$ uses the gate’s own input, the quick way divides by its normalized inverter’s input	Ch 7 §9, Ch 8 §1
$t = \dfrac{C_{load}}{C_{ref}}\,\tau_{inv}$	one gate on one edge: $C_{ref}$ is the input of the balanced inverter with the same drive on that edge, $(1 + r)W_{n,eq}C_g$ falling or $(1 + 1/r)W_{p,eq}C_g$ rising, $r = R_{pfet}/R_{nfet}$Rpfet​/Rnfet​; MT17-3d: 12.5 and 3.125 $\tau_{inv}$ added	M3 §7
$\text{Delay} = \tau_{inv}\sum_i g_ih_i$	a path’s delay is the sum of its gains	Ch 8 §2
$F = \prod_i g_ih_i = GHB$GHB, $H = C_L/C_{in}$	path effort; $H$ uses the first gate’s input; $F$ is fixed only if nothing branches	Ch 8 §2
$f = F^{1/N}$F1/N, $\text{Delay}_{min} = NF^{1/N}\tau_{inv}$	equal gains minimize the delay when $F$ is fixed	Ch 8 §3
best gain per stage $e$ (3–4 in practice), $N \approx \ln F$	how many stages; add inverters in pairs, next to the load	Ch 8 §4, §7
$W_n = C_{out}/(3f)$Cout​/(3f), or $C_{out}/(2f)$ at equal strengths	sizing back from the load, $C_{out}$ in µm of gate; then multiply stacked devices; the first gate stays fixed	Ch 8 §6
$b = (C_{on} + C_{off})/C_{on}$	branching effort; it changes with the sizes	Ch 8 §8
two neighbours with a fixed product $P$P: each $\sqrt P$	the pair rule for retuning, when only the gate between them changes; then enlarge the gate after a heavy branch and rebalance	Ch 8 §9, M4 §4
bottom of a stack: delay $\sim n^2$	its internal nodes, at about $V_{DD} - V_T$VT​, discharge first; put the late signal nearest the output	Ch 8 §10, Ch 7 §5

5. Pass-transistor and ratioed logic

MT24-3, MT23-2, MT21-1 and MT21-3, worked in M5, Sections 1–4. The questions come in a fixed order: is it static, what does it compute, what are the worst levels or what do the restoring devices do, and what is the static CMOS equivalent.

Formula	Meaning, and when it holds	Taught in
exactly one path to $V_{DD}$ or ground, for every allowed input	static: correct for any sizing, however slow	Ch 7 §4, Ch 10 §9
both networks connected: ratioed; neither: dynamic	ratioed means correct only for some sizings (a fight); dynamic means the node holds its charge	Ch 10 §9, Ch 11 §1
NFET: 0 and $V_{DD} - V_{Tn}$VTn​; PFET: $V_{DD}$ and $\lvert V_{Tp}\rvert$	the levels a fully-on pass transistor passes; each device stops when its own $V_{GS}$ reaches threshold	Ch 10 §5
series NFETs, gates at $V_{DD}$VDD​: still $V_{DD} - V_{Tn}$	drops add only through a gate: a degraded node driving a gate gives $V_{DD} - 2V_{Tn}$2VTn​, and $2\lvert V_{Tp}\rvert$ for lows	Ch 10 §5, M5
NFET ∥ PFET on complementary gates	complementary pass transistor: full rail both ways, more area	Ch 10 §5
inverter plus weak PFET feedback	half latch: restores the high, slows the fall, and makes the circuit ratioed	Ch 10 §6
selects one-hot	a pass-transistor multiplexer is static only with exactly one select on: none floats, two fight	Ch 10 §7
delay of a channel-connected component	a pass transistor’s delay includes the gate that drives it	Ch 10 §8
equal widths: $R \parallel 4R = 0.8R$ down, $2R \parallel 2R = R$ up	the lecture’s pass-transistor model: size the pass PFET equal to the pass NFET	Ch 11 §2
$V = V_{DD}\dfrac{R_{down}}{R_{up} + R_{down}}$	the level of a fight, each device $R/W$ (a PFET $2R/W$2R/W); the 6T XOR fails once its inverter NFET is narrower than 1/3 µm added	Ch 10 §9
$V_{OL} = (V_{DD} - V_T)\bigl(1 - \sqrt{1 - r/n}\bigr)$	pseudo-NMOS low with $n$ NFETs on, $r = \beta_p/\beta_n$βp​/βn​; square law, load PFET saturated; 0.536 V at 5 V, 1 V and $r = 1/4$ added	Ch 10 §10
$I = \frac{\beta_p}{2}(V_{DD} - V_T)^2$	pseudo-NMOS static current while the output is low (0.5 mA, 2.5 mW in Chapter 10’s example); IDDQ testing turns the load off added	Ch 10 §10, Ch 11 §1
PUN = dual of PDN (series ↔ parallel)	the complementary static CMOS equivalent; keep stacks to 2, at most 3	Ch 7 §4–5

6. Dynamic and domino logic

MT17-3c, MT23-3 and MT24-5, worked on page M6. Chapters 11 and 12 teach the method.

Formula	Meaning, and when it holds	Taught in
clk = 0 precharge, clk = 1 evaluate	the dynamic gate; the node is precharged to $V_{DD}$VDD​, and a floating 1 is held only by charge	Ch 11 §4
footer: a clocked NFET in series at the foot	prevents collisions during precharge; it counts in the evaluate stack	Ch 11 §4
node $= \overline f$f​, domino output $= f$f; a p-type node $= f$	$f$ is the evaluate network’s conduction function; domino is non-inverting	Ch 11 §4, Ch 12 §6
$t = \dfrac{R_{nfet}}{W_{eq}}\,C_{load}$Weq​Rnfet​​Cload​, footer included	the evaluate delay; the precharge device is off and doesn’t count	Ch 11 §4
dynamic into dynamic on one clock: a race	the domino inverter removes it (precharged outputs are 0); NP domino alternates n and p stages instead	Ch 11 §5, Ch 12 §5
NP domino: n stage on clk; p stage with header and pre-discharge NFET on $\overline{\text{clk}}$	a resting 1 turns PFETs off and a resting 0 turns NFETs off, so alternating stages need no inverters and have no race; both evaluate while clk is high	Ch 12 §5
skewed inverter (strong PFET)	switches at a higher input: a faster rising output, a smaller $NM_H$ for the dynamic node	Ch 11 §7
half latch ≈ 1/10 of the pull-down’s strength	a PFET of $2 \times 0.1\,W_{eq}$ for $R_{pfet} = 2R_{nfet}$2Rnfet​: 0.2 µm for three 3 µm NFETs in series; weaken it with a series device and keep the output-driven one at minimum size	Ch 11 §8–9
$V = V_{DD}\dfrac{C_X}{C_X + C_{int}}$	charge sharing; internal nodes rise at most to $V_{DD} - V_T$VT​; 1.2 V × 40/64 = 0.75 V added	Ch 11 §10
noise $= V_{DD} - V_{DD}'$	supply noise: precharged at $V_{DD}'$VDD′​, read against $V_{DD}$VDD​; the half latch makes the node track the supply	Ch 11 §12
n-type: $g = k/3$k/3; equal strengths $k/2$	dynamic logical effort of a $k$-high evaluate path, footer counted: footed 2-high 2/3, footless 1/3	Ch 12 §2
p-type: $g = 2k/3$2k/3; equal strengths $k/2$	header counted; twice the n-type’s with $R_{pfet} = 2R_{nfet}$	Ch 12 §6
skewed 8:1 inverter: $g = 3/4$ rising, 3 falling	logical effort on each edge, $R_{pfet} = 2R_{nfet}$	Ch 12 §3
inverter PFET $= \dfrac{2\,C_L/C_g}{3f}$3f2CL​/Cg​​, NFET = PFET/8	domino sizing from the load, $R_{pfet} = 2R_{nfet}$2Rnfet​, PFET four times stronger: 5.56 and 0.69 µm for 50 fF at 2 fF/µm and $f = 3$	Ch 12 §3
stack device $= \dfrac{k(W_p + W_n)}{3f}$	each device of the $k$-high stack: 2.08 µm for the lecture’s footed AND (board 2.1)	Ch 12 §3
domino AND $6\,\tau_{inv}$6τinv​, static $8\,\tau_{inv}$	the same 25 µm load and input capacitance; $F$ = 9 against 16	Ch 12 §4
clk′ falls at least $t_p$ after clk; $k\Delta + t_p \le T_P$	delayed reset: footless stages without collisions, only behind a domino inverter; about three, then a footed stage	Ch 12 §7

7. Noise margins and the transfer curve

MT24-1, MT17-2 and MT17-1a, worked in M3, Sections 5, 6 and 9. These are explanation questions: two or three sentences and a sketch per part.

Formula	Meaning, and when it holds	Taught in
$I_{D,n} = I_{D,p}$ID,p​, $V_{DS,n} = V_{out}$Vout​, $V_{SD,p} = V_{DD} - V_{out}$	the transfer curve (VTC) is where the two I–V curves cross; no load current	Ch 6 §2
cutoff/triode → sat/triode → sat/sat → triode/sat → triode/cutoff	NFET/PFET regions as $V_{in}$ rises; the gain is high where both are saturated	Ch 6 §2
slope $-1$ at $(V_{IL}, V_{OH})$ and $(V_{IH}, V_{OL})$	the edges of the high-gain region	Ch 6 §4
$NM_L = V_{IL} - V_{OL}$VOL​, $NM_H = V_{OH} - V_{IH}$	DC noise on every node, each at its largest	Ch 6 §4
one noisy node: low up to $V_{IL}$VIL​, high down by $V_{DD} - V_{IH}$	the gate driving it has a clean input, so its output is at the rail	Ch 6 §5
stronger PFET: $V_{IL}$VIL​, $V_{IH}$ up; $NM_L$ up, $NM_H$ down	the switching point moves right; $V_{OH}$ and $V_{OL}$ barely move. Chapter 6’s model with the PFET doubled: $NM_L$ 1.672 → 2.094 V, $NM_H$ 1.672 → 1.305 V	Ch 6 §4, M3 §5
lower peak gain: $V_{IL}$ down, $V_{IH}$ up, both margins down	$V_{OH}$ and $V_{OL}$ move little, in a direction that depends on the model	M3 §5
fanout: no change in a DC margin	a CMOS input draws no DC current; fanout only slows the edges	M3 §9
delay 50% to 50%; slews 10–90 or 20–80 (extrapolated ÷0.8, ÷0.6)	the conventions; always ask which slew; a delay can be negative	Ch 6 §10
crowbar ≈ 10–20% of dynamic power	worse with slow slews	Ch 6 §7
TT, SS, FF, SF, FS at $3\sigma$3σ; PVT	process corners; for timing, SS with low $V_{DD}$ and hot	Ch 6 §8

8. Device physics and the short answers

MT21-2 and MT17-1b–c, worked in M3, Sections 8–9. Since 2021, device physics appears mainly inside the inverter-chain question, as the subthreshold leakage. Chapter 3’s junction and threshold formulas have not been asked on a past midterm, but they are in scope.

Formula	Meaning, and when it holds	Taught in
$V_{bi} = \dfrac{kT}{q}\ln\dfrac{N_AN_D}{n_i^2}$	built-in voltage of a pn junction, at most about $E_g/q$	Ch 3 §2
$qN_Ax_p = qN_Dx_n$qND​xn​; $\tfrac12 W\lvert\mathcal{E}_{max}\rvert = V_{bi} + V_R$	charge balance across the junction; the field triangle’s area is the voltage across it	Ch 3 §1
$W = \sqrt{\dfrac{2\kappa_s\varepsilon_0(V_{bi} + V_R)}{qN}}$qN2κs​ε0​(Vbi​+VR​)​​, $N = \dfrac{N_AN_D}{N_A + N_D}$	depletion width; it grows with reverse bias $V_R$	Ch 3 §3
$C_j = \kappa_s\varepsilon_0/W$	junction capacitance per area; it falls with reverse bias	Ch 3 §5
$\phi_F = \dfrac{kT}{q}\ln\dfrac{N_A}{n_i}$qkT​lnni​NA​​; threshold at $\phi_s = 2\phi_F$	the band bending that inverts the surface	Ch 3 §7
$V_T = V_{FB} + 2\phi_F + Q_{bulk}/C_{ox}$Qbulk​/Cox​, $C_{ox} = \kappa_{ox}\varepsilon_0/t_{ox}$	threshold voltage	Ch 3 §8
$Q_{bulk} = \sqrt{2qN_A\kappa_s\varepsilon_0(2\phi_F + V_{SB})}$	body effect: $V_T$ rises with $V_{SB} \ge 0$	Ch 5 §1
$I \propto e^{qV_A/kT}$	forward diode current: 60 mV per decade at 300 K	Ch 2 §10
n well to $V_{DD}$VDD​, substrate to ground	otherwise a junction is forward-biased: a PFET’s well at 0 V under its source at $V_{DD}$ draws a large static current (MT17-1b)	Ch 5 §8
$v_{drift} = \mu\mathcal{E}$μE, or $\dfrac{\mu\mathcal{E}}{1 + \mathcal{E}/\mathcal{E}_{crit}}$ with $v_{sat} = \mu\mathcal{E}_{crit}$	low-field drift; the velocity-saturation fit (a curve fit, not physics)	Ch 4 §1, §6
$I_D = WQ_i(x)\,v_{drift}$WQi​(x)vdrift​, $Q_i(x) = C_{ox}\bigl(V_{GS} - V_T - V(x)\bigr)$	current = charge × velocity, the same at every point of the channel; strong inversion	Ch 4 §2–3
$I_D = \mu C_{ox}\frac{W}{L}\bigl[(V_{GS} - V_T)V_{DS} - V_{DS}^2/2\bigr]$	long-channel triode, for $V_{DS}$ below $V_{DSAT} = V_{GS} - V_T$	Ch 4 §4
$I_D = I_{D,long}/(1 + \mu V_{DS}/v_{sat}L)$	velocity-saturated triode	Ch 4 §7
PMOS: $V_{DS} \to V_{SD}$VSD​, $V_{GS} \to V_{SG}$VSG​, $V_T < 0$	the signs	Ch 4 §9
$W, L, t_{ox}, V \to 1/\kappa$1/κ, $N \to \kappa N$	constant-field (Dennard) scaling: delay $1/\kappa$1/κ, power $1/\kappa^2$1/κ2, power density unchanged	Ch 4 §10
$S = m\frac{kT}{q}\ln 10 \ge 60$ mV/decade	subthreshold slope at 300 K; smaller is better; it scales with $T$	Ch 4 §11
cutoff $C_{gb} = C_{ox}WL$Cox​WL; triode $C_{gs} = C_{gd} = \tfrac12C_{ox}WL$21​Cox​WL; saturation $C_{gs} = \tfrac23C_{ox}WL$	intrinsic capacitance by region (rules of thumb; the lecture’s $f_T$ uses $C_{ox}WL$Cox​WL)	Ch 5 §3
$C_{wire} \approx 0.1$ fF/µm	a minimum-width wire	Ch 5 §2
$g_m = WC_{ox}v_{sat}$	transconductance of a velocity-saturated device	Ch 5 §9
$f_T = \dfrac{g_m}{2\pi C_{gs}} = \dfrac{v_{sat}}{2\pi L} = \dfrac{1}{2\pi\tau_{tr}}$	unity-gain frequency; independent of $W$W; 63.7 GHz at 0.25 µm	Ch 5 §10
$t = \tau_{tr}(1 + 1/\eta)$1/η), $\eta = C_g/C_d$	an NFET discharging an equal NFET	Ch 5 §11
FO1 $= 3\tau_{tr}(1 + 1/\eta)$1/η), FO4 $= 3\tau_{tr}(4 + 1/\eta)$	PFET $2W$2W; a W/W inverter at equal strengths has 2 in place of 3 (MT21-2)	Ch 5 §12–13

9. Stick layouts

MT24-4 and MT23-4, worked in M5, Sections 5–6: draw the schematic, then name the function. About five minutes.

Rule	Meaning, and when it holds	Taught in
poly crossing diffusion = a transistor	a poly line across both rows is two devices, a PFET and an NFET with the same input	Ch 9 §10
only a contact (X) connects layers	metal crossing a poly or a diffusion without one is not connected	Ch 9 §10
uncontacted shared diffusion = series; the same two nets = parallel	name each diffusion piece by its contact’s net, then read the networks	Ch 9 §10, Ch 5 §6
PUN = dual of PDN	the check on your reading; a poly with no input label is an internal net, so there is a second stage	Ch 9 §10, M5 §5
PC over RX = transistor; PC over STI = wire	poly; keep poly wires short	Ch 9 §2
RX active, NW n well, PC poly, BP p⁺ implant, CA contact to M1	the five front-end (FEOL) layers: FEOL makes the transistors, the back end (BEOL) the wires; shapes on layers become masks (GDS, tape-out)	Ch 9 §2
RX under BP = p⁺, otherwise n⁺	the implant decides the diffusion type	Ch 9 §2
n⁺ outside NW: NFET; p⁺ in NW: PFET; p⁺ outside NW: substrate plug (ground); n⁺ in NW: well plug ($V_{DD}$VDD​)	device or tie	Ch 9 §2
one gate order that is an Euler path of both networks	shared diffusions, unbroken rows, straight polys	Ch 10 §1
contact a diffusion if its net leaves the row or recurs	an uncontacted shared diffusion is a series internal node	Ch 10 §1
share the drain on the switching node	one shared diffusion carries less junction capacitance than two	Ch 5 §6
b bordered, a abutted, s shared	the layout-dependent letters of a device’s two diffusions, source then drain	Ch 10 §2
$W$ over 10–15 µm: fingers of at most 10–15 µm	a wide device split for its aspect ratio and the gate’s RC delay	Ch 10 §3
DRC, LVS, extraction	geometry against the rules; layout against the schematic; wire R and C	Ch 9 §6
resolution, alignment, miscellaneous	kinds of design rule: width and spacing on one layer; between two layers; fill, antenna, ERC	Ch 9 §7
5-2-2 metal stack; CMP → metal fill and antenna rules	the class’s back end; alternate routing directions up the stack	Ch 9 §3, §5
$n = \lfloor (W - 2e + s)/(a + s)\rfloor$	contacts of size $a$a, spacing $s$ and enclosure $e$ in a row of width $W$ added	Ch 9 §7

10. Common mistakes

Collected from the chapters’ “common mistakes” lists and from the errors found in the past answer keys while re-solving them. Where a key made the mistake, its part is named; the full lists are in M3, M4 and M5.

Conventions and units

• Mixing device strengths. With equal strengths the balanced inverter is W/W, its input $2W$ and $\tau_{inv} = 2R_{nfet}C_g$2Rnfet​Cg​; using $3W$ or $3R_{nfet}C_g$ there is wrong (Ch 7 §7).
• Multiplying by 0.69. $R$ is defined from the 50% delay, so $(R/W)C$ already is the delay. Use 0.69 only if the question asks, and say which you used (Ch 7 §1).
• Units of the result. $\tau_{inv}$ in ps times a sum of gains near 25 is about a nanosecond, not 1000 ns (MT23-5b–d’s keys write “1244.7 ns”); MT23-3b’s key writes ns for ps.
• pA for nA. 10 µA/µm divided by $10^{2.22}$ is 59.9 nA/µm (MT23-1b’s key).
• Arithmetic under time pressure. $25/4 = 6.25$6.25, not 6.75 (MT17-3a’s key); a NAND’s stage gain “3/2 = 1” should be 3/3 (MT17-5a’s key).

Energy and leakage

• Per cycle or per transition. Per transition only the nodes that rise draw energy; per cycle every node does. MT23-1c’s key divides by one transition’s energy where the cycle’s belongs (Ch 6 §6).
• Counting both edges in $f$f. $P = CV_{DD}^2f$ counts full cycles.
• Leaving $T$ unsubstituted. When the cycle equals the chain delay, substitute it: $W$ cancels from the leakage share.
• The off width. In a 2W/W inverter the off device is $W$ half the time and $2W$ the other half: $1.5W$ on average.

Delay and sizing

• Counting every transistor of the receiving gate. One input drives one NFET and one PFET; only those load the stage (Ch 7 §8).
• Dividing by the gate’s own input. That gives $h$h, not the gain; the gain divides by the normalized inverter’s input (Ch 8 §1).
• Resizing the first gate. Its input is the constraint; size back from the load (Ch 8 §6).
• An odd number of added inverters flips the logic function (Ch 8 §7).
• The wrong node for a side load. Add it only to the stage that drives that node (MT23-5c’s key loads stage 3 instead of stage 2).
• Resizing only the stage that drives a branch. Its larger input moves the excess gain to the stage before it; the delay doesn’t fall (MT17-5d’s key). Rebalance the pair instead (Ch 8 §9).
• Treating a recomputed $F$ as fixed once a branch is present: $F$ moves as you resize (MT23-5d’s key).
• FO4 = 4 FO1 in the transit-time model. Only the gate load scales with the fan-out; FO4 $= \frac{1 + 4\eta}{1 + \eta}$ FO1 (Ch 5 §13).
• Leaving devices out of a series path. Every device in the conducting stack counts, footer included (MT23-3b’s key counts one PFET of a three-high path; Ch 11 §4).

Pass-transistor logic

• One threshold per series device. Two series NFETs with gates at $V_{DD}$ pass $V_{DD} - V_{Tn}$VTn​; the second drop needs a degraded node on a gate (Ch 10 §5).
• An example input that gives a full level. Check the example you quote: at A = B = C = 1 MT23-2’s carry is a full $V_{DD}$ (its key’s example).
• “Only one select.” It must be exactly one: with none on, the output floats (MT21-1a’s key).
• The cut-off condition. An NFET pass transistor stops when $V_{GS} = V_{Tn}$VTn​, so its output is $V_{DD} - V_{Tn}$ (MT21-1b’s key writes $V_{GS} = V_{DD} - V_{Tn}$VTn​).
• Judging “static” from the settled states. A half latch fights on transitions, so the circuit is ratioed (MT24-3a’s key says static; its own rubric says not).
• Dual-rail is not complementary pass transistors. Full rail needs a PFET in parallel on the same path (Ch 10 §5).

Dynamic and domino logic

• Counting the precharge device in the evaluate delay or in $C_{in}$Cin​. It is off, and its gate is on the clock (Ch 12 §2).
• Four times stronger is eight times wider when $R_{pfet} = 2R_{nfet}$ (Ch 12 §3).
• Driving the half latch from the dynamic node, or making it as strong as the pull-down (Ch 11 §8).
• The charge-sharing fraction is $C_{int}/(C_X + C_{int})$Cint​), not $C_{int}/C_X$Cint​/CX​; and no path to ground is needed (Ch 11 §10).
• Delayed reset without the domino inverter. A bare dynamic node rises during precharge, so delaying the next stage’s reset guarantees the collision (Ch 12 §7).

Noise margins and devices

• Pairing the wrong points. $NM_L$ pairs $V_{IL}$ with $V_{OL}$VOL​, from different points of the curve (Ch 6 §4).
• Firm directions for $V_{OH}$ and $V_{OL}$VOL​. They move little; say which picture you assume (MT24-1c–d). The firm directions are $V_{IL}$VIL​, $V_{IH}$ and the margins.
• Fanout and DC margins. Capacitive loading changes no DC level.
• The slope backwards. A smaller mV/decade is better, and it grows with temperature (Ch 4 §11).
• The square law in a short channel. At 0.25 µm it overestimates the current about 3.5 times (Ch 4 §7).
• A body at the wrong rail. The body of an NMOS must stay at or below its source, the n well of a PMOS at or above (Ch 5 §1, §8).

Check yourself Without looking: the three conventions you should state at the top of an inverter-chain answer, and the three of a path-sizing answer.

Chain: the device strength (2W/W with $R_{pfet} = 2R_{nfet}$2Rnfet​, or W/W with equal strengths, which sets $\tau_{inv}$ and the node capacitance); whether delays carry the 0.69 factor; and whether the energy is per cycle or per transition. Path: the device strength (which sets the normalized inverter’s input, $3W$ or $2W$2W, and the logical efforts); the load in µm of gate at the given $C_g$Cg​; and that only gate capacitance counts, with $\tau_{inv}$ as the unit.