M7. Practice midterm

This page is a new midterm, written for this guide in the pattern of the two most recent past midterms (MT23 and MT24): five questions, 75 minutes, closed book, with the points printed on every part. Every circuit and every number is new. Each question takes one of the families that the past exams keep asking, and adds one twist that they haven’t used yet.

It is practice, not a prediction. Page M1 explains what the four past midterms share and labels its own guess at the Fall 2026 exam as a guess. Page M2 collects the formulas; don’t use it during the 75 minutes.

How to use it.

1. Print the exam or keep it on screen, and put the solutions out of sight. Allow 75 minutes, no notes, a calculator.
2. Write an explanation with every answer: the past exams give partial credit only with one.
3. Then mark your answers against the solutions. Each solution shows the steps, the answer with units, the chapter section that teaches the method, and the trap the question sets.
4. Use the score sheet to see which pages to review.

Question	Family	Points	Pace at 22.5 s a point
1	Inverter chain: energy, leakage, energy × delay	50	19 min
2	Pass-transistor logic	45	17 min
3	Dynamic and domino logic	50	19 min
4	Stick layout to schematic	15	5 min
5	Static path sizing	40	15 min

The exam

Practice midterm, E4321 study guide. Time: 75 minutes. Total: 200 points.

1. This exam is closed book, closed notes.
2. Partial credit will be given. If you don’t have time to work a problem completely, explain how you would solve it and set up the problem. No credit will be given for answers without explanation.
3. There are five questions. Most of them require short answers with little calculation. Pace yourself so that you reach every problem; the easiest problems may not be the first.
4. Unless a question says otherwise: a transistor of width $W$ driving a capacitance $C$ takes $(R/W)\,C$(R/W)C, with $R$ in kΩ·µm and $C$ in fF (1 kΩ × 1 fF = 1 ps), and no 0.69 factor; only gate capacitance counts; the FO1 delay of the balanced inverter is $\tau_{inv}$τinv​.

Question 1. An inverter chain that runs hot (50 points)

Consider a chain of $N$ 2W/W inverters (PFET $2W$2W, NFET $W$W), each output loaded by an additional 6 fF of side-branch capacitance. In this technology $C_g = 1\,\mathrm{fF/\mu m}$1fF/μm, $R_{nfet} = 1\,\mathrm{k\Omega\cdot\mu m}$ and $R_{pfet} = 2\,\mathrm{k\Omega\cdot\mu m}$2kΩ⋅μm. Ignore drain capacitances. The input is a 50-percent-duty-cycle square wave of period $T_{cycle}$Tcycle​, and $V_{DD} = 1.0\,\mathrm{V}$1.0V. Both the NFET and the PFET draw $10\,\mu\mathrm{A/\mu m}$ at their threshold voltage, $|V_T| = 300\,\mathrm{mV}$300mV, and both have a subthreshold slope of 75 mV/decade at 300 K.

Question 1.

(a) What is the energy drawn from the supply by this chain of $N$ inverters during one $T_{cycle}$Tcycle​? Express it as a function of $N$ and $W$W. Ignore crowbar currents. (10 points)

(b) What is the total subthreshold leakage energy of the $N$ inverters at 300 K during one cycle? (10 points)

(c) Assume that $T_{cycle}$ equals the delay of the $N$-stage chain. What is the ratio of the leakage energy of (b) to the total energy consumed in a cycle, as a function of $N$ and $W$W? (10 points)

(d) If you can change the sizing of the inverters, what value of $W$ minimizes the product of the energy of (a) and the delay of the chain? (10 points)

(e) The chip now runs at 400 K. Assume that $R$R, $C_g$Cg​, $V_T$ and the current at threshold do not change, and that the subthreshold slope is proportional to the absolute temperature. What is the ratio of (c) now? If the energy in (d) included the leakage energy, would your answer to (d) change? Explain. (10 points)

Question 2. A pass-transistor select gate (45 points)

Consider the pass-transistor circuit below. The inputs A, B, $\bar B$Bˉ, C and S are driven by static inverters, so they are full-rail signals. Use $V_{DD} = 5\,\mathrm{V}$ and $V_{Tn} = |V_{Tp}| = 1\,\mathrm{V}$ where you need numbers, and ignore body effect.

Question 2. N1–N3 are NFETs; P1 and P2 are PFETs (bubble on the gate).

(a) Is this a static CMOS circuit? Explain. Would your answer change if P2 were removed? (10 points)

(b) What logic function does this circuit perform at Y and at the output Z? (10 points)

(c) With P2 removed, what are the lowest logic high and the highest logic low that Y can reach, and under what static values of the inputs? (10 points)

(d) What function is P2 performing? Which of the levels in (c) does it fix, and which does it not? (5 points)

(e) Draw a complementary static CMOS circuit with the same logic function at Z. (10 points)

Question 3. A domino gate with a branching driver (50 points)

Consider the footed domino gate below. In this technology $R_{pfet} = 2R_{nfet}$2Rnfet​, $C_g = 1\,\mathrm{fF/\mu m}$ and $\tau_{inv} = 20\,\mathrm{ps}$20ps. Ignore diffusion and overlap capacitances. In the dynamic stage every NFET (C, A, B and the clocked footer) is $W_N$ wide and the precharge PFET is 1 µm. The output inverter has a PFET of width $W_P$ and an NFET of width $W_P/8$WP​/8, and it drives $C_L = 250\,\mathrm{fF}$250fF. Input A comes from the inverter I0 (PFET 2 µm, NFET 1 µm), which also drives input A of an identical domino gate elsewhere.

Question 3.

(a) What logic function does the dynamic node X compute during evaluate, and what does the output Y compute? What is Y during precharge? (8 points)

(b) Let $W_N = 2\,\mu\mathrm{m}$ and $W_P = 8\,\mu\mathrm{m}$8μm. What are the logical efforts of the dynamic stage (for input A) and of the output inverter on the edge that carries the logic? Estimate the delay from the input of I0 falling to Y rising, in evaluate, with B = 0 and C = 1. (12 points)

(c) Now resize $W_N$ and $W_P$ to minimize this delay. Keep I0 as it is, keep the inverter’s NFET at $W_P/8$WP​/8, and resize the identical gate on the branch the same way. What are the new widths and the new delay? (14 points)

(d) How does the 8:1 sizing of the output inverter change its static noise margins compared with a balanced inverter? Which margin matters for node X, and why? (8 points)

(e) Node X needs protection against leakage. What would you add, where would its gate connect, and how wide should it be for your sizes of (c), by the course’s rule of thumb? A minimum device is 1 µm wide. (8 points)

Question 4. A stick layout (15 points)

Consider the stick layout below, with a row of PFET devices and a row of NFET devices.

p diffusion n diffusion poly metal 1✕ contact

Question 4. The short poly at the left crosses only the p diffusion; its contact is on the metal line that runs down to GND. A, B and C cross only the n diffusion.

(a) Draw the schematic that corresponds to this layout. (8 points)

(b) What logic function does this gate perform? (4 points)

(c) Is it a static CMOS gate? Name one consequence. (3 points)

Question 5. A static path, and how many stages (40 points)

Consider the critical path below through complementary static CMOS gates. In this technology the NFET and PFET have the same drive strength, and every gate is sized for equal rising and falling delays: the inverters have NFET and PFET $W_i$Wi​; the NOR3 has NFETs $W_2$ and PFETs $3W_2$3W2​; the NAND2 has NFETs $2W_3$ and PFETs $W_3$W3​. $C_g = 1\,\mathrm{fF/\mu m}$1fF/μm, $\tau_{inv} = 50\,\mathrm{ps}$50ps, a minimum device is 1 µm wide, and $C_{load} = 2\,\mathrm{pF}$2pF. Ignore diffusion and overlap capacitances. The unused inputs are tied as shown.

Question 5. The dashed 60 fF capacitor on node C is present in part (d) only.

(a) Estimate the delay from A to E with $W_1 = 1$1, $W_2 = 2$2, $W_3 = 4$ and $W_4 = 8\,\mu\mathrm{m}$8μm. (8 points)

(b) $W_1$ is fixed at 1 µm. Choose $W_2$W2​, $W_3$ and $W_4$ to minimize the delay, and estimate the new delay. (10 points)

(c) Could the path be made faster by adding inverters? If so, how many would you add, where, and what delay would result? (10 points)

(d) Return to your four-stage sizing of (b). A 60 fF wire load is added at node C. What is the delay now? Retune $W_2$W2​, $W_3$ and $W_4$ ($W_1$W1​ fixed) to reduce it, and give the new delay. You need not reach the exact minimum. (12 points)

End of the exam.

Solutions

Try every part before you open its steps. Each solution names the section that teaches the method; the past-exam pages M3, M4, M5 and M6 work the original questions of each family.

Conventions used throughout (the past keys mix them, so state yours):

• Delay $= (R/W)\,C$(R/W)C, no 0.69 factor. MT24-2c’s key accepted both; MT23-3b used 0.69.
• With $R_{pfet} = 2R_{nfet}$ the balanced inverter is 2W/W, its input $3W$3W, and $\tau_{inv} = 3R_{nfet}C_g$3Rnfet​Cg​. With equal strengths it is W/W, its input $2W$2W, and $\tau_{inv} = 2R_{nfet}C_g$ (Chapter 7, Section 7).
• Energy is per cycle when every node rises once, per transition when only every other node rises (Chapter 6, Section 6).
• Leakage currents are per µm of width, and only the device that is off leaks.

Solution 1. The inverter chain

This is the inverter-chain question, and it takes the moves of page M3’s “How to approach an inverter-chain question” in their usual order: the node first, then the switching energy, the leakage, the delay and the best width. It is MT23-1’s 2W/W chain with new numbers; part (e), a hot chip, is new.

Before the parts: one node. Every part needs the capacitance on one node and the delay of one stage, so find them once. On the output of each inverter hang:

• the next inverter’s input. An input is wired to both gates, the PFET’s ($2W$2W) and the NFET’s ($W$W), so it presents $3W\,C_g$3WCg​;
• the 6 fF side load;
• the inverter’s own drains, which the question tells you to ignore.

$$C_{node} = (3W + 6)\,\mathrm{fF}\quad(W\text{ in }\mu\text{m}).$$

The PFET has half the NFET’s drive per micron ($R_{pfet} = 2R_{nfet}$Rpfet​=2Rnfet​), but it is twice as wide, so it pulls up exactly as hard as the NFET pulls down: $R_{pfet}/2W = R_{nfet}/W$Rnfet​/W. The 2W/W inverter is balanced, and every stage takes the same time on either edge: $(R_{nfet}/W)\,C_{node} = 3 + 6/W$ ps. Without the side load that is the FO1 delay, $\tau_{inv} = (R_{nfet}/W)(3W\,C_g) = 3R_{nfet}C_g = 3\,\mathrm{ps}$3ps.

1a. Energy per cycle (10 points).

Hint

Over one period of the square wave, how many times does each node rise, and what does each rise cost the supply?

What it asks. The energy the supply delivers to the whole chain in one full period of the input: one rising edge and one falling edge. The words “during one $T_{cycle}$Tcycle​” decide how many nodes you count. A question that says “per transition” counts one edge, and its answer is half as large.

The idea. The supply delivers energy only when it charges a node. Raising a node of capacitance $C$ from 0 to $V_{DD}$ draws the charge $CV_{DD}$ from the supply at the voltage $V_{DD}$VDD​, so the supply delivers $CV_{DD}^2$CVDD2​. Half of it is stored on the node and half burns in the PFET. When the node falls, the NFET burns the stored half and the supply delivers nothing (Chapter 6, Section 6). So the energy per cycle is (the number of nodes that rise in one cycle) × $C_{node}V_{DD}^2$Cnode​VDD2​. The tempting slip is $\tfrac12 CV_{DD}^2$21​CVDD2​: that is the energy stored on a node, not the energy drawn from the supply.

1a: energy per cycle (10 points)

1. Price one rise. Because the supply pays only when it charges a node, a node draws $C_{node}V_{DD}^2$ from the supply each time it rises, and nothing when it falls (Chapter 6, Section 6).
2. Count the rises. An inverter’s output rises when its input falls. In one period the input rises once and falls once: the even nodes rise on one edge and the odd nodes on the other, so every node rises exactly once.
3. Add them up. $E_{cycle} = N(3W + 6)\,\mathrm{fF} \times (1.0\,\mathrm{V})^2 = N(3W + 6)\,\mathrm{fJ}$6)fJ, with $W$ in µm, since fF × V² = fJ. For $W = 1\,\mu\mathrm{m}$1μm: $9N$ fJ.

Check. At $V_{DD} = 1.0$ V the energy in fJ is the same number as the capacitance in fF, so each inverter’s share is just its node: 9 fF and 9 fJ at $W = 1\,\mu\mathrm{m}$1μm. ✓ The 6 fJ per inverter that has no $W$ in it is the side load’s share ($6\,\mathrm{fF} \times 1\,\mathrm{V^2}$6fF×1V2): no choice of width removes it.

Answer: $E_{cycle} = N(3W + 6)\,\mathrm{fJ}$6)fJ. Not half of it: the ½ is the energy stored on the node, not the energy drawn.

Remember. Supply energy = (number of rising nodes) × $CV_{DD}^2$CVDD2​. Per cycle every node rises once; per transition, half of them do.

1b. Leakage energy per cycle (10 points).

Hint

In each inverter one transistor is off. Which one is it, how wide is it, and how many decades below threshold is its gate?

What it asks. The energy lost while nothing switches: the current through the transistors that are meant to be off, in all $N$ inverters, for one whole cycle. Three things decide it: which device is off and how wide it is, how much current it still passes, and for how long.

The idea. A MOSFET doesn’t shut off at its threshold. Below $V_T$ its current falls by one decade (a factor of 10) for every $S$ millivolts that the gate is below threshold, where $S$ is the subthreshold slope (Chapter 4, Section 11):

$$I = I(V_T) \cdot 10^{-(V_T - V_{GS})/S}$$

(for the PFET, in magnitudes). An off device has $V_{GS} = 0$0, so its gate sits a full $V_T$ below threshold. What differs from MT24-2b’s W/W chain is the width of the device that is off: in a 2W/W inverter it depends on the output, as in MT23-1b on page M3.

1b: leakage energy per cycle (10 points)

1. How far below threshold? Because an off device has $V_{GS} = 0$0, its gate is the whole 300 mV below threshold: $300/75 = 4$ decades (Chapter 4, Section 11).
2. How much current? Four decades divide the current at threshold by $10^4$104: $I_{off} = 10\,\mu\mathrm{A/\mu m}/10^4 = 1\,\mathrm{nA/\mu m}$1nA/μm.
3. Which device, and how wide? In a settled inverter exactly one device is off. With the output high the NFET ($W$W) is off; with the output low the PFET ($2W$2W) is off. The 50% duty cycle keeps each output high for half the cycle and low for the other half, so the average off width is $1.5W$1.5W.
4. What is across it? The off device has one end at the output and the other at a rail, and the output sits at the opposite rail, so the full $V_{DD}$ is across it. Power is current × voltage, and energy is power × time: $E_{leak} = N \cdot 1.5W \cdot 1\,\mathrm{nA/\mu m} \cdot 1.0\,\mathrm{V} \cdot T_{cycle}$Tcycle​.
5. Units. nW × s = nJ, so $E_{leak} = 1.5\,NWT_{cycle}$ nJ with $T_{cycle}$ in seconds. With $T_{cycle}$ in ps, nW × ps = $10^{-21}$ J = $10^{-6}$ fJ, so it is $1.5\times10^{-6}\,NWT_{cycle}$ fJ. Part (c) needs this form.

Check. One 1 µm inverter leaks 1.5 nW. Through a 1 ns cycle that is 1.5 aJ, or $1.5\times10^{-3}$ fJ, against the 9 fJ it spends switching in (a): about one part in 6000. At 300 K leakage is small; part (c) makes the comparison exact, and part (e) shows what heat does to it.

Answer: $E_{leak} = 1.5\,N\,W\,T_{cycle}$ nJ ($W$W in µm, $T_{cycle}$ in s). The trap is the off width: a 2W/W inverter leaks through $W$ half the time and $2W$ the other half.

Remember. Leakage is always three questions: which device is off and how wide, how many decades below threshold, and for how long. When the two devices differ in width, average the off width over the cycle.

1c. The leakage share (10 points).

Hint

Leakage grows with the length of the cycle; switching energy doesn’t. Write $T_{cycle}$ as the chain’s delay, and both energies become functions of $N$ and $W$ alone.

What it asks. The fraction of all the energy used in one cycle that is leakage, when the clock runs as fast as the chain allows: $T_{cycle}$ equals the chain’s delay. “Total” means switching (a) plus leakage (b). Because $T_{cycle}$ is now tied to the circuit, it has to be replaced by the delay before you divide.

The idea. The chain’s delay comes from the course’s delay model: the conducting transistor acts as a resistor $R/W$ that charges or discharges the node, so one stage takes $(R/W)\,C_{node}$ (Chapter 7, Section 1), and $N$ stages in a row take $N$ times as long. Put that into (b), then divide by (a). The algebra is MT23-1c’s (page M3, Section 2); only the numbers change.

1c: the leakage share (10 points)

1. The chain delay. Because every stage takes $3 + 6/W$ ps on either edge (before the parts), $N$ of them take $T_{cycle} = N(3 + 6/W) = N(3W + 6)/W$ ps.
2. Leakage over that cycle. Put it into (b)‘s ps form: $E_{leak} = 1.5\times10^{-6}\,NW \cdot N(3W + 6)/W = 1.5\times10^{-6}\,N^2(3W + 6)$ fJ. The $W$ cancels: wider devices leak more, but they shorten the cycle in the same proportion.
3. Divide by (a). The switching energy is $N(3W + 6)$ fJ, so $3W + 6$ cancels too: leakage ÷ switching $= 1.5\times10^{-6}N$10−6N.
4. The share of the total. The total is switching plus leakage, so leakage ÷ total $= \dfrac{1.5\times10^{-6}N}{1 + 1.5\times10^{-6}N}$1+1.5×10−6N1.5×10−6N​.

Check. A second route gives the coefficient directly added. Leakage is $N \cdot 1.5W \cdot I_{off}V_{DD}$ for a time $N(R_{nfet}/W)\,C_{node}$N(Rnfet​/W)Cnode​, and switching is $NC_{node}V_{DD}^2$NCnode​VDD2​, so their ratio is $1.5\,I_{off}R_{nfet}N/V_{DD}$1.5Ioff​Rnfet​N/VDD​: the capacitance and $W$ cancel, and a current times a resistance over a voltage has no units, as a ratio must. 1 nA × 1 kΩ = 1 µV, and $1.5 \times 1\,\mu\mathrm{V} \times N/1\,\mathrm{V} = 1.5\times10^{-6}N$10−6N. ✓

Answer: $\dfrac{1.5\times10^{-6}N}{1 + 1.5\times10^{-6}N}$1+1.5×10−6N1.5×10−6N​, independent of $W$W. For $N = 100$ it is $1.5\times10^{-4}$10−4. The same algebra as MT23-1c on page M3.

Remember. When $T_{cycle}$ is tied to a delay, substitute the delay before you divide. The leakage share is then $1.5\,I_{off}R_{nfet}N/V_{DD}$ in disguise: no $W$W, and proportional to $N$N.

1d. The best width for energy × delay (10 points).

Hint

Write energy × delay as a function of $W$W. The energy grows with $W$ and the delay shrinks; where do the two pulls balance?

What it asks. The width that makes (the energy per cycle of (a)) × (the chain’s delay) smallest. Why a product: the energy alone is smallest for the smallest $W$W, and the delay alone for the largest $W$ (MT24-2e on page M3). The product charges for both, so it has a best width in between.

The idea. Both factors contain $3W + 6$6. The energy grows with $W$ (bigger gates to charge); the delay falls with $W$ (stronger devices, so the fixed 6 fF matters less). Their product is smallest where the two effects balance. A sum of the form $aW + b/W$ is smallest where its two terms are equal; setting the derivative to zero added finds the same point.

1d: the best width for energy × delay (10 points)

1. Multiply. $E \cdot D = N(3W + 6) \times N\dfrac{3W + 6}{W} = N^2\,\dfrac{(3W + 6)^2}{W}\,\mathrm{fJ\cdot ps}$N2W(3W+6)2​fJ⋅ps.
2. Keep only what depends on W. $N^2$ is a constant factor, so minimize $\dfrac{(3W + 6)^2}{W} = 9W + 36 + \dfrac{36}{W}$W36​.
3. Balance the two terms added. The 36 is constant. As $W$ grows, $9W$ grows and $36/W$ shrinks, and their sum is smallest where they are equal: $9W = 36/W$36/W, so $W = 2\,\mu\mathrm{m}$2μm. The derivative agrees added: $\dfrac{(3W + 6)(3W - 6)}{W^2} = 0$0, so $3W = 6$6.
4. What it means. At $W = 2\,\mu\mathrm{m}$ the inverters’ own gate load, $3W\,C_g = 6\,\mathrm{fF}$6fF, equals the side load. Narrower, and the side load dominates every node, so the delay climbs; wider, and most of the energy goes into the inverters’ own gates.
5. The numbers there. Each stage takes $6\,\mathrm{ps} = 2\tau_{inv}$2τinv​, the energy is $12N$ fJ, and $E \cdot D = 72N^2\,\mathrm{fJ\cdot ps}$72N2fJ⋅ps.

Check. Try the neighbours: $(3W + 6)^2/W$ is 81 at $W = 1$1, 72 at $W = 2$ and 81 at $W = 4$4. The minimum is at 2, and it is shallow: a width off by a factor of 2 costs 12.5%.

Answer: $W = 2\,\mu\mathrm{m}$2μm.

Remember. Energy × delay is least where the gates’ own load equals the fixed side load: $3W\,C_g = 6$ fF here, $2W\,C_g = 4$ fF in MT24-2d.

1e. A hot chip (10 points).

Hint

Only one quantity in the leakage formula depends on temperature. Which one, and how many decades below threshold is an off gate at 400 K?

What it asks. Two things. First, the share of (c) when the chip runs at 400 K, with everything held fixed except the subthreshold slope. Second, whether the best width of (d) would move if its energy included the leakage. The question’s own words give the only change: the slope is proportional to the absolute temperature.

The idea. The subthreshold slope is $m\,(kT/q)\ln 10$m(kT/q)ln10, so it is proportional to the absolute temperature added (Chapter 4, Section 11; MT17-1c on page M3 uses the same step). With $V_T$ and the current at threshold fixed, a larger slope means fewer decades between threshold and $V_{GS} = 0$0, and so more off current. Nothing else in (c) changes, so the share grows with $I_{off}$Ioff​. For the second question, ask whether the extra energy depends on $W$W. The tempting answer, “wider devices leak more, so $W$ must shrink”, forgets that (c) found no $W$ in the leakage share.

1e: the twist, a hot chip (10 points)

1. The new slope. The slope is proportional to the absolute temperature added (as in MT17-1c, page M3, Section 9): $75 \times 400/300 = 100\,\mathrm{mV/decade}$100mV/decade.
2. The new off current. The off gate is still 300 mV below threshold, but that is now only 3 decades: $I_{off} = 10\,\mu\mathrm{A/\mu m}/10^3 = 10\,\mathrm{nA/\mu m}$10nA/μm, ten times more.
3. The new share. Because the share of (c) is $1.5\,I_{off}R_{nfet}N/V_{DD}$ and only $I_{off}$ changed, it grows tenfold: leakage ÷ switching $= 1.5\times10^{-5}N$10−5N, and leakage ÷ total $= \dfrac{1.5\times10^{-5}N}{1 + 1.5\times10^{-5}N}$1+1.5×10−5N1.5×10−5N​. For $N = 100$100: $1.5\times10^{-3}$10−3.
4. The energy with leakage. With the leakage included, the energy is $E_{cycle}(1 + 1.5\times10^{-5}N)$10−5N). The factor in parentheses has no $W$ in it (step 2 of 1c), so it multiplies $E \cdot D$ by a constant.
5. A constant factor doesn’t move a minimum: $W = 2\,\mu\mathrm{m}$ still. A wider chain does leak more current, but it also runs a shorter cycle, and the two cancel.

Check. At 300 K the same formula must give back (c): $1.5 \times 1\,\mathrm{nA} \times 1\,\mathrm{k\Omega} \times N/1\,\mathrm{V} = 1.5\times10^{-6}N$10−6N. ✓ And for small shares the two temperatures differ by exactly the ratio of the off currents: $1.5\times10^{-3}$ against $1.5\times10^{-4}$ at $N = 100$100, a factor of 10.

Answer: $\dfrac{1.5\times10^{-5}N}{1 + 1.5\times10^{-5}N}$1+1.5×10−5N1.5×10−5N​, ten times the 300 K share for small shares; $W = 2\,\mu\mathrm{m}$ is unchanged, because when $T_{cycle}$ is the chain delay the leakage grows with $W$ exactly as the switching energy does.

Remember. Temperature reaches the leakage only through the slope: fewer decades below threshold, more current. Before you change a width because of leakage, check whether the leakage share depends on the width at all.

The twist. The past chains changed the sizing (W/W or 2W/W) or the side load; this one changes the temperature. Two traps: forgetting that only the slope scales (the question holds $V_T$ and the current at threshold fixed), and answering “a wider W leaks more, so W must shrink” without checking that the share doesn’t depend on $W$W.

Check yourself At 400 K, roughly how many stages would the chain need before its leakage energy per cycle equals its switching energy?

Leakage ÷ switching $= 1.5\times10^{-5}N = 1$ gives $N \approx 67\,000$67000. At 300 K it would take about 670 000. A cycle that long is unrealistic, which is the point of the past exams’ version: with $T_{cycle}$ equal to the chain delay, leakage stays a small share.

Solution 2. The pass-transistor select gate

This is the pass-transistor question, and it takes the moves of page M5’s “How to approach a pass-transistor question” in order: read the circuit node by node, decide static or ratioed, the function, the levels, restoring, and the static CMOS equivalent. Read the circuit first (Chapter 10, Section 4): each node is fed by a pair of switches, and every part uses what they do.

Reading the circuit

1. Node P. N1 and N2 have complementary gates (B and $\bar B$Bˉ), so exactly one of them conducts. B = 1 turns N1 on, and it passes A; B = 0 turns N2 on, and it passes B itself, which is then 0. So $P = AB$AB: the lecture’s PTL AND.
2. Node Y. N3 (an NFET) and P1 (a PFET) share the gate S. An NFET conducts when its gate is high and a PFET when its gate is low, so exactly one of them conducts: S = 1 gives Y = P, S = 0 gives Y = C.
3. Z and P2. An inverter makes $Z = \bar Y$Yˉ. P2 runs from $V_{DD}$ to Y with Z on its gate, and a PFET conducts when its gate is low: P2 is on whenever Z is 0, that is whenever Y reads as 1. It feeds the output back to help a high Y.

2a. Is it static? (10 points).

Hint

Check every settled state first. Then take a transition in which Y has to fall while P2 is still on.

What it asks. Whether the circuit, as drawn, is a static CMOS circuit, and whether removing P2 changes that. “Explain” means: say which test you apply, and show where the circuit passes or fails it.

The idea. The lecture’s test has two halves (Chapter 10, Section 4, Section 9). A circuit is static when every node, for every input, has a path to exactly one rail (no node floats, none is pulled both ways), and its correct operation never depends on the transistors’ sizes. A half latch passes the first half and can fail the second: when the node has to change against it, the result depends on which device is stronger, and a circuit like that is ratioed (Chapter 10, Section 6). So check the settled states first, then the transitions.

2a: is it static? (10 points)

1. Without P2. P is fed by two NFETs with complementary gates (B, $\bar B$Bˉ), so exactly one path in every state, ending at an inverter output and so at one rail. Y is fed by N3 and P1 with a common gate, again exactly one path. Z is an inverter. No node floats, nothing fights, and sizing changes the speed, never the value: static, though not complementary (Chapter 10, Section 4).
2. With P2, the settled states. In every settled state Y still has one path to one rail, because P2 is on only while Y is high, and then it pulls the same way as Y’s driver.
3. With P2, a transition. But take A, B, S = 1, 1, 1 (Y high, so Z = 0 and P2 on) and let A fall to 0. N1 and N3 now pull Y down through A’s driver, while P2, whose gate Z is still 0, holds it up: a fight, settled by sizes (Chapter 10, Section 6).
4. How the fight comes out added. In Chapter 10’s switch model (each device $R/W$R/W, a PFET $2R/W$2R/W; A’s driver NFET, N1 and N3 all 1 µm in series against a P2 of width $w$w): $V_Y = 15w/(3w + 2)$ V. A 0.25 µm P2 gives 1.36 V, and Y falls; a 1 µm P2 gives 3 V, above the inverter’s threshold, and Y stays high: the wrong answer. The switch-over is $w = 2/3\,\mu\mathrm{m}$2/3μm.
5. The verdict. Correct operation depends on P2 being weak: by the lecture’s test that is ratioed, not static (Chapter 10, Section 9).

Check. The switch-over in step 4 sits where it should. At $w = 2/3\,\mu\mathrm{m}$ the formula gives $15 \times (2/3)/(2 + 2) = 2.5$ V, half the supply: the output inverter’s threshold in the switch model, which takes that inverter as symmetric. A wider P2 holds Y above it, a narrower one lets Y fall below it.

Answer: As drawn, no: the half latch P2 makes it ratioed (every falling transition of Y must overpower P2). Without P2, yes: every node has exactly one path to one rail for every input, and nothing depends on sizing. Write both views; MT24-3a’s rubric gave full credit only for the transition argument (page M5, Section 1).

Remember. Static needs both halves: one path to one rail in every settled state, and no fight on any transition. A half latch passes the first and fails the second, so it makes the circuit ratioed.

2b. The functions (10 points).

Hint

Write each node as “the control selects one of two inputs”, then fill in what the two inputs are.

What it asks. The logic function at the internal node Y, and at the output Z.

The idea. Two switches that feed one node and have complementary controls form a 2:1 multiplexer: the node equals one input when the control is 1 and the other when it is 0. With control $s$s, inputs $x$ and $y$y, that is $s \cdot x + \bar s \cdot y$ (Chapter 10, Section 7). The reading above found two such pairs: one at P (control B) and one at Y (control S). So write each as a multiplexer, substitute, and invert for Z.

2b: the functions (10 points)

1. Node P. Control B selects A (B = 1) or B itself (B = 0, so 0): $P = B \cdot A + \bar B \cdot B = AB$ (reading, step 1).
2. Node Y. Control S selects P (S = 1) or C (S = 0): $Y = S \cdot P + \bar S \cdot C = SAB + \bar S C$SˉC, a 2:1 multiplexer that selects $AB$ when S = 1 and C when S = 0.
3. The output. The inverter complements Y: $Z = \bar Y = \overline{SAB + \bar S C}$SAB+SˉC​. For S = 1, $Z = \overline{AB}$ (a NAND); for S = 0, $Z = \bar C$Cˉ.

Check. Try two rows. S = 1, A = B = 1: P = 1, Y = 1, Z = 0, and $\overline{SAB + \bar S C} = \overline{1 + 0} = 0$0. ✓ S = 0, C = 0: Y = C = 0, Z = 1, and $\overline{0 + 0} = 1$1. ✓

Answer: $Y = SAB + \bar S C$ and $Z = \overline{SAB + \bar S C}$SAB+SˉC​.

Remember. Read a node fed by two switches with complementary controls as a multiplexer. When one of its inputs is the control signal itself (N2 passes B only when B = 0), the multiplexer becomes an AND.

2c. The worst levels without P2 (10 points).

Hint

Which kind of transistor carries each level to Y, and is any gate along the way driven by a degraded node?

What it asks. With the half latch removed, the weakest high and the weakest low that Y can settle at, and the inputs that produce them. “Static values” means settled DC levels, not the voltages during a transition.

The idea. The threshold rule (Chapter 10, Section 5). An NFET passes a 0 fully but a 1 only up to its gate voltage minus $V_{Tn}$VTn​, because it turns off once its $V_{GS}$ falls to $V_{Tn}$VTn​. A PFET passes a 1 fully, but a 0 only down to its gate voltage plus $|V_{Tp}|$∣VTp​∣. A second threshold is lost only when a degraded node drives a gate; a degraded level passed on through an NFET whose gate is a full $V_{DD}$ loses nothing more. So trace every path that can reach Y and apply the rule along it. The tempting slip here is $V_{DD} - 2V_{Tn}$ for two NFETs in series.

2c: the worst levels without P2 (10 points)

1. Node P first, because Y’s high comes through it. A 1 reaches P only through N1, an NFET with a full gate (B = 1): $V_{DD} - V_{Tn}$VTn​. A 0 reaches P fully through either NFET.
2. Lowest high. S = 1, A = B = 1: P is at $V_{DD} - V_{Tn}$VTn​, and N3, whose gate S is a full $V_{DD}$VDD​, passes it on. N3 stops only when its own $V_{GS}$ reaches $V_{Tn}$VTn​, at $V_{DD} - V_{Tn}$VTn​, which P already is. So Y $= V_{DD} - V_{Tn}$VTn​, not $V_{DD} - 2V_{Tn}$2VTn​: two NFETs in series with full gates lose one threshold (Chapter 10, Section 5). C doesn’t matter.
3. The other high. S = 0 with C = 1: P1 passes a 1, fully: $V_{DD}$VDD​.
4. Highest low. S = 0, C = 0: P1, a PFET, passes the 0 only down to $|V_{Tp}|$∣VTp​∣. A and B don’t matter. With S = 1 a 0 arrives through NFETs, fully.
5. The numbers, and why they matter. 4 V and 1 V. Both weak levels leave the output inverter at an edge: at Y = 4 V its PFET has $V_{SG} = 1\,\mathrm{V} = |V_{Tp}|$∣VTp​∣, at Y = 1 V its NFET has $V_{GS} = V_{Tn}$VTn​, so neither is firmly off.

Check. Each weak level is exactly one threshold from its rail, $5 - 1 = 4$ V and $0 + 1 = 1$ V, as one device of the wrong type on the path predicts. The two full levels come through the right type of device: the high of C through the PFET P1, the low of P through the NFETs.

Answer: Lowest high $V_{DD} - V_{Tn}$ (4 V), for S = 1 and A = B = 1 (any C). Highest low $|V_{Tp}|$ (1 V), for S = 0 and C = 0 (any A, B).

Remember. An NFET costs one threshold on a high and a PFET one on a low, once per path. Only a degraded node driving a gate costs a second.

2d. What P2 does (5 points).

Hint

P2 is a PFET whose gate is Z. When is it on, and which way can it pull Y?

What it asks. Name P2’s job, and say which of the two weak levels of (c) it repairs and which it leaves.

The idea. A half latch is a PFET from $V_{DD}$ to a pass-transistor node, with its gate on the output of the inverter that the node drives (Chapter 10, Section 6). Once the node is high enough for the inverter to read a 1, the inverter’s output falls, the PFET turns on, and it pulls the node the rest of the way up. A PFET to $V_{DD}$ can only pull up, and it is on only while the node is already high, so it can do nothing for a weak low.

2d: what P2 does (5 points)

1. It is a half latch (Chapter 10, Section 6). When Y arrives at $V_{DD} - V_{Tn}$VTn​, the inverter reads it as a 1, Z goes to 0, P2 turns on and pulls Y the rest of the way to $V_{DD}$VDD​.
2. It fixes the high, not the low. It fixes the weak high. It can’t fix the weak low: P2 can only pull up, and while Y is low, Z is 1 and P2 is off. Y still sits at $|V_{Tp}|$ for S = 0, C = 0.
3. What it costs. The price is (a): it makes the gate ratioed, so it must be weak.
4. Fixing the low too. Because a weak low comes from a PFET passing a 0, put an NFET gated by $\bar S$ in parallel with P1 (a complementary pass pair, Chapter 10’s fix 1).

Check. This agrees with (a): the property that restores the high, P2 being on while Y is high, is the same one that made Y fight P2 when it had to fall. A device that helps one edge always gets in the way of the other.

Answer: P2 restores the $V_{DD} - V_{Tn}$ high to $V_{DD}$VDD​; the $|V_{Tp}|$ low stays.

Remember. A PFET half latch restores highs only. A weak low needs a different fix, such as an NFET beside the PFET that passes it.

2e. A static CMOS equivalent (10 points).

Hint

Z is already the complement of a sum of products. What does one complementary gate compute?

What it asks. A complementary static CMOS circuit with the same logic function as Z.

The idea. In a complementary gate the pull-down network conducts exactly when the output should be 0, and the pull-up is its dual: series becomes parallel and parallel becomes series (Chapter 7, Section 4). One gate therefore computes the complement of its pull-down’s function, and the complement of a sum of products is one AND-OR-invert gate, with each product a series chain in the pull-down (Chapter 7, Section 5). Z has exactly that form, so it needs no output inverter; only $\bar S$ needs one.

2e: a static CMOS equivalent (10 points)

1. One gate. A complementary gate computes an inverted function, and Z is already inverted: $Z = \overline{SAB + \bar S C}$SAB+SˉC​. So one gate, with no output inverter (Chapter 7, Section 5).
2. The pull-down conducts when Z = 0, that is when $SAB + \bar S C = 1$1: S, A, B in series, in parallel with $\bar S$Sˉ, C in series.
3. The pull-up is the dual: (S ∥ A ∥ B) in series with ($\bar S$Sˉ ∥ C).
4. Try one row. S = 0, C = 1: the $\bar S$–C branch conducts, the pull-up’s ($\bar S$Sˉ ∥ C) branch is off, Z = 0. ✓
5. The count. 10 transistors, NFET stack 3 high, PFET stack 2 high, plus an inverter for $\bar S$Sˉ: 12. The pass version uses 7, plus the inverter for $\bar B$Bˉ.

Question 2e: Z = NOT(S·A·B + S̄·C), one AND-OR-invert gate; S̄ comes from an inverter.

Check. A second row, from the other branch: S = 1, A = B = 1. The S–A–B chain conducts, and the pull-up’s (S ∥ A ∥ B) group is off, so Z = 0, as $\overline{SAB + \bar S C} = 0$ requires. ✓ The two networks are never on together, because one is the dual of the other.

Answer: one AND-OR-invert gate, $Z = \overline{SAB + \bar S C}$SAB+SˉC​: pull-down S–A–B in series, in parallel with $\bar S$–C; pull-up (S ∥ A ∥ B) in series with ($\bar S$Sˉ ∥ C); $\bar S$ from an inverter. 12 transistors in all.

Remember. A complementary gate gives the complement of its pull-down’s function for free. When the target is already inverted, one AOI gate does it.

The twist. MT23-2 and MT24-3 lost a second threshold, or none, by other routes. Here two NFETs sit in series, which tempts you to write $V_{DD} - 2V_{Tn}$2VTn​, and the half latch fixes only one of the two weak levels.

Check yourself Suppose S reached N3 and P1 through an NFET pass transistor whose gate is at V_DD, so that S's high is V_DD − V_Tn. Without P2, what is the lowest high at Y now, and what happens to P1 when S is high?

N3’s gate is now at $V_{DD} - V_{Tn}$VTn​, so N3 stops one threshold below that: Y’s lowest high falls to $V_{DD} - 2V_{Tn}$ (3 V), for S = 1, A = B = 1. A degraded node driving a gate costs a second threshold (MT23-2c’s mechanism). And P1 is no longer firmly off: with C = 1 its source is at $V_{DD}$ and its gate at $V_{DD} - V_{Tn}$VTn​, so $V_{SG} = V_{Tn}$VTn​, exactly its threshold. In a real circuit it conducts slightly, and for AB = 0 it fights N3, which is pulling Y to 0.

Solution 3. The domino gate

This is the dynamic-logic question, and it takes the moves of page M6’s “How to approach a dynamic-logic question”: n-type or p-type, the node’s function, the one edge each stage makes, dynamic logical effort with the whole stack, and then the skewed inverter’s margins and the half latch. Part (d) is also a noise-margin question, with the moves of page M3’s “How to approach a noise-margin question”.

Before the parts: the clocked devices. They tell you the kind of gate. The clk PFET from $V_{DD}$ to X charges X high while clk = 0, and the clk NFET at the foot lets the pull-down conduct only while clk = 1. So this is a footed n-type stage: X is precharged high, and during evaluate it can only fall. The convention is $R_{pfet} = 2R_{nfet}$2Rnfet​, so the balanced inverter is 2W/W, with input $3W$ for an NFET of $W$W.

3a. The function (8 points).

Hint

During evaluate, when does the NFET network give X a path to ground?

What it asks. The logic function at the dynamic node X during evaluate, the function at the output Y, and the value of Y during precharge.

The idea. A dynamic node is charged high during precharge, then discharged during evaluate only if its pull-down network conducts (Chapter 11, Section 4). Devices in series conduct when all of them are on (an AND); devices in parallel conduct when any one is on (an OR). So X is the complement of the pull-down’s function, and the inverter after it undoes the complement: a domino gate is non-inverting.

3a: the function (8 points)

1. Which phase, which devices. In evaluate (clk = 1) the footer is on and the precharge PFET off. X falls when the pull-down conducts: C in series with (A ∥ B), so when $(A + B)\,C$ (Chapter 11, Section 4).
2. X and Y. $X = \overline{(A + B)\,C}$(A+B)C​; the inverter gives $Y = (A + B)\,C$B)C, an OR-AND. Domino is non-inverting.
3. Precharge. In precharge (clk = 0) X is pulled to $V_{DD}$VDD​, so Y = 0. That 0 is what keeps the next domino gate from starting early (Chapter 11, Section 6).

Check. Two rows. A = 1, B = 0, C = 1: C, A and the footer are all on, so X falls and Y = 1, and $(A + B)C = 1$1. ✓ C = 0: the path is broken whatever A and B are, so X stays high and Y = 0. ✓

Answer: $X = \overline{(A + B)C}$(A+B)C​, $Y = (A + B)C$ in evaluate; Y = 0 in precharge.

Remember. Read a dynamic node’s function off its pull-down: series is AND, parallel is OR, and the node is the complement. Precharge leaves every domino output at 0.

3b. Logical efforts and the delay as drawn (12 points).

Hint

Follow the edge from I0 to Y first. Then, for each stage, compare its input with the balanced inverter that drives as hard on that edge.

What it asks. Two logical efforts, each on the edge that carries the logic, and then the delay through I0, the dynamic stage and the inverter at the given sizes. “B = 0 and C = 1” makes A the input that matters; “I0 falling to Y rising” names the edges.

The idea. A stage’s logical effort $g$ is its input’s capacitance over the input of the balanced inverter that drives as hard as it does, on the edge that matters (Chapter 12, Section 2). Transistors in series act like one transistor of width $1/\sum(1/W_i)$1/∑(1/Wi​). For a dynamic stage only the evaluate edge counts, and the evaluate path includes the footer: with $R_{pfet} = 2R_{nfet}$ a stack of $k$ equal devices gives $g = k/3$k/3. The skewed inverter after a dynamic node makes only one logic edge, rising, so it is compared with the balanced inverter that has the same PFET. Each stage then takes $\tau_{inv}$ times its gain $g \cdot h$h, where the electrical effort $h$ is the capacitance it drives over its own input, and the path delay is $\tau_{inv}$ times the sum of the gains (Chapter 8, Section 2). I0 drives two identical inputs, so its load is doubled.

3b: logical efforts and the delay as drawn (12 points)

1. Follow the edges first. I0’s input falls, so A rises; with C = 1 the pull-down conducts and X falls; the inverter makes Y rise. Every stage switches on its logic edge, so the requested path exists. (Two past keys asked for an output edge their circuit could not make along that path; see page M6.)
2. Dynamic stage, input A. Its evaluate path is A, C and the footer: three $W_N$ devices in series, which pull down like one NFET of $W_N/3$WN​/3. The balanced 2W/W inverter with that pull-down has input $3 \times W_N/3 = W_N$WN​. Input A is one NFET of $W_N$WN​. So $g = W_N/W_N = 1$1: $k/3$ with $k = 3$ (Chapter 12, Section 2). The 1 µm precharge PFET plays no part.
3. Inverter, rising edge. Its PFET $W_P$ pulls Y up like the PFET of a balanced $W_P$ over $W_P/2$ inverter, whose input is $1.5W_P$1.5WP​. Its own input is $W_P + W_P/8 = 1.125W_P$1.125WP​. So $g = 1.125/1.5 = 3/4$ (Chapter 12, Section 4). Its strength ratio is $(W_P/2)/(W_P/8) = 4$4.
4. I0 (g = 1) drives input A of this gate and of the identical one: $2 + 2 = 4\,\mu\mathrm{m}$ from its 3 µm input. Gain $4/3 = 1.33$ (branching factor 2).
5. Dynamic stage drives the inverter’s input, $8 + 1 = 9\,\mu\mathrm{m}$9μm, from 2 µm: $g\,h = 1 \times 4.5 = 4.5$4.5.
6. Inverter drives 250 µm (250 fF at 1 fF/µm) from 9 µm: $g\,h = 0.75 \times 27.8 = 20.83$20.83.
7. Add. Delay $= (1.33 + 4.5 + 20.83)\,\tau_{inv} = 26.67\,\tau_{inv} = 533\,\mathrm{ps}$533ps.

Check. Multiply the three gains: $1.333 \times 4.5 \times 20.83 = 125$125. In that product $W_N$ and $W_P$ cancel, so it is the path effort that part (c) needs; if your (c) finds a different $F$F, one of these gains is wrong.

Answer: $g = 1$ for the dynamic stage, $g = 3/4$ for the inverter’s rising edge; $26.7\,\tau_{inv} \approx 533$ ps. The last stage, at gain 20.8, is badly overloaded.

Remember. Logical effort = input capacitance over the balanced inverter with the same drive on the edge that matters. For a footed dynamic stage, count every device in the stack: $g = k/3$ with $R_{pfet} = 2R_{nfet}$2Rnfet​.

3c. Sizing for minimum delay (14 points).

Hint

The product of the three gains doesn’t depend on $W_N$ or $W_P$WP​. What is it, and what does that make each gain at the minimum?

What it asks. Choose $W_N$ and $W_P$ (with the copy on the branch resized the same way, and I0 fixed) to make (b)‘s delay as small as possible, and give the widths and the delay.

The idea. With I0’s input and the load fixed, the product of the gains is the path effort $F = G \cdot B \cdot H$H: $G$ is the product of the logical efforts, $B$ the product of the branching factors (the total load at a branch over the load on the path), and $H$ the load over the path’s input (Chapter 8, Section 8). The inner widths cancel, so $F$ is fixed. With a fixed product, the sum of the gains is smallest when they are all equal, $f = F^{1/N}$ (Chapter 8, Section 3); then size back from the load. $B = 2$ stays exact because the identical gate is resized too, so the branch is always half of I0’s load. The traps: leaving the footer out of $k$ ($g = 2/3$g= instead of 1); counting the precharge PFET; giving the skewed inverter $g = 1$1; forgetting the branch, which gives $f = 3.97$ and a first stage that is really at gain 7.9.

3c: sizing for minimum delay (14 points)

1. The path effort (Chapter 8, Section 8): $G = 1 \times 1 \times 3/4$3/4; $B = 2$ (the identical gate is resized too, so the branch stays half of I0’s load); $H = 250/3$250/3. $F = G \cdot B \cdot H = 0.75 \times 2 \times 83.3 = 125$125.
2. Equal gains. Three stages: $f = \sqrt[3]{125} = 5$5; delay $3 \times 5 = 15\,\tau_{inv} = 300\,\mathrm{ps}$ (Chapter 8, Section 3).
3. Back from the load, because the load is known and each step back adds one unknown. Inverter: $0.75 \times 250/C_{in} = 5$5, so $C_{in} = 37.5\,\mu\mathrm{m} = 1.125\,W_P$1.125WP​: $W_P = 33.3\,\mu\mathrm{m}$33.3μm, NFET $4.17\,\mu\mathrm{m}$ (Chapter 12, Section 3).
4. Dynamic stage: $1 \times 37.5/W_N = 5$5, so $W_N = 7.5\,\mu\mathrm{m}$ for A, B, C and the footer.
5. I0 is not chosen; it checks the work: $2 \times 7.5/3 = 5$5. ✓

Check. From 533 ps to 300 ps. The inverter, overloaded at gain 20.8, now runs at 5, and the dynamic stage grew from 2 to 7.5 µm to drive the larger inverter. Move either width a little ($W_N$WN​ to 7 or 8 µm, $W_P$ to 30 or 37 µm) and the sum of the gains rises: the equal-gain point is the minimum.

Answer: $W_N = 7.5\,\mu\mathrm{m}$7.5μm, $W_P = 33.3\,\mu\mathrm{m}$ (NFET 4.17 µm); delay $15\,\tau_{inv} = 300\,\mathrm{ps}$300ps, down from 533 ps.

Remember. When the branch’s load grows with the path (an identical gate resized the same way), $B$ is a constant and $F$ stays fixed: $f = F^{1/N}$F1/N, size back from the load, and let the first stage check your arithmetic.

3d. Noise margins of the skewed inverter (8 points).

Hint

Does a strong PFET against a weak NFET slide the transfer curve sideways or change its slope? Then: which way can noise move a precharged node?

What it asks. How the 8:1 sizing (a PFET four times as strong as the NFET) moves the inverter’s static noise margins compared with a balanced inverter, and which of the two margins protects node X. The moves are those of page M3’s “How to approach a noise-margin question”.

The idea. A noise margin is the distance from where a node sits to where the next gate starts to amplify, at the points where the transfer curve’s slope is −1; with noise everywhere, $NM_L = V_{IL} - V_{OL}$ and $NM_H = V_{OH} - V_{IH}$ (Chapter 6, Section 4). The output switches where the NFET’s current matches the PFET’s. A stronger PFET needs a higher input before the NFET can match it, so the steep part of the curve slides right. Then ask which way noise can push X: in evaluate a dynamic node is held only by its stored charge.

3d: noise margins of the skewed inverter (8 points)

1. The curve slides right. A strong PFET against a weak NFET moves the inverter’s switching point up toward $V_{DD}$VDD​; $V_{IL}$ and $V_{IH}$ both rise (Chapter 6, Section 4).
2. The margins follow. So $NM_L = V_{IL} - V_{OL}$ grows and $NM_H = V_{OH} - V_{IH}$ shrinks.
3. Which way noise pushes X. X rests at $V_{DD}$ in evaluate whenever the gate should not fire, and every noise source pulls it down: leakage through the off NFETs, charge sharing with the node between C and A ∥ B, coupling (Chapter 11, Sections 8–10).
4. The margin that matters. The margin that protects a high X is $NM_H$NMH​, the one the skew shrinks: a smaller droop flips the inverter, and a dynamic node that has fallen can’t recover until the next precharge.

Check. added In Chapter 6’s illustrative square-law inverter ($V_{DD} = 5\,\mathrm{V}$VDD​=5V, $V_T = \pm 1\,\mathrm{V}$±1V, $\lambda = 0.05$0.05; illustrative, not a lecture value), making the PFET four times as strong as the NFET moves the switching point from 2.50 to 2.99 V, $NM_L$ from 1.67 to 2.51 V and $NM_H$ from 1.67 to 1.04 V: the directions of step 2. Page M6’s MT23-3c computes the mirror case, an NFET four times as strong.

Answer: $NM_H$ falls and $NM_L$ rises. $NM_H$ is the one that matters, because X is a floating high that noise can only pull down. (MT23-3c asks the mirror question about a p-type gate, whose node rests low: there $NM_L$ matters.)

Remember. A skew slides the curve and trades one margin for the other. A node precharged high can only be pulled down, so it needs $NM_H$NMH​, the margin the skew gives away.

3e. The half latch (8 points).

Hint

What keeps X high while it floats, and how weak must that device be for the pull-down still to win?

What it asks. The keeper for X: which device, where its gate connects, and how wide it should be for the widths of (c), by the course’s rule of thumb, with a 1 µm minimum width.

The idea. A half latch is a weak PFET from $V_{DD}$ to the dynamic node, with its gate on the inverter’s output (Chapter 11, Section 8). While X is high, Y is 0 and the PFET replaces the charge that leakage takes away; once X has fallen far enough, Y rises and turns it off. It has to be weak, because during evaluate the pull-down must overpower it before Y flips. The rule of thumb is a tenth of the pull-down’s strength (Chapter 11, Section 9). Compare strengths as NFET-equivalent widths, using the series rule, then convert to a PFET with $R_{pfet} = 2R_{nfet}$2Rnfet​.

3e: the half latch (8 points)

1. Where it goes. Add a half latch: a weak PFET from $V_{DD}$ to X, its gate driven by Y (Chapter 11, Section 8). While X is high, Y is 0 and the PFET holds X up; once X falls, Y rises and turns it off.
2. The pull-down’s strength. Rule of thumb: one tenth of the pull-down’s strength (Chapter 11, Section 9). The pull-down’s weakest path is A (or B), C and the footer: three 7.5 µm NFETs, like one 2.5 µm NFET.
3. A tenth, as a PFET. One tenth: a 0.25 µm NFET, which is a 0.5 µm PFET ($R_{pfet} = 2R_{nfet}$Rpfet​=2Rnfet​).
4. Building it. That is below the 1 µm minimum. Use two 1 µm PFETs in series, which act as one 0.5 µm PFET. Keep the one whose gate is Y at minimum length and width, so it loads Y as little as possible; the other can be lengthened if it must be weaker still. Its gate doesn’t load Y, so tie it to ground (always on) added.

Question 3e: the half latch as two minimum PFETs in series (equivalent to one 0.5 µm PFET).

Check. The strengths agree: a 0.5 µm PFET drives like a 0.25 µm NFET, a tenth of the 2.5 µm stack, and two 1 µm PFETs in series act as $1/(1/1 + 1/1) = 0.5\,\mu\mathrm{m}$0.5μm. ✓ At the drawn sizes of (b), $W_N = 2\,\mu\mathrm{m}$2μm, the same rule would ask for a 0.133 µm PFET, which is harder still to build.

Answer: a half-latch PFET from $V_{DD}$ to X with its gate on Y, sized at a tenth of the pull-down: 0.5 µm, built as two 1 µm PFETs in series. It costs evaluation speed, because the pull-down must fight it until Y rises.

Remember. A keeper is a PFET from $V_{DD}$ to the dynamic node, gated by the inverter’s output, with a tenth of the pull-down’s drive. Below the minimum width, build it from minimum devices in series.

The twist. MT24-5 sized a dynamic path with a branch inside the gate; here the branch is on the driver, and the gate is footed with a three-high stack, so its logical effort comes out at exactly 1. The half latch is sized, not just named.

Check yourself If the inputs were guaranteed low before every precharge, the footer could go. With the footer removed and the other assumptions of (c), what is the dynamic stage's logical effort, and what minimum delay does the path reach?

The stack is now A and C, two high: $g = 2/3$ ($k/3$k/3). $F = (2/3)(3/4)(2)(250/3) = 83.3$83.3, $f = 4.37$4.37, delay $3 \times 4.37 = 13.1\,\tau_{inv} = 262\,\mathrm{ps}$262ps, about 13% faster than the footed 300 ps. The cost is the collision risk of Chapter 12, Section 7.

Solution 4. The stick layout

This is the stick-layout question, and it takes the moves of page M5’s “How to approach a stick-layout question”: poly crossing diffusion is a transistor; contacts and metal name the nodes; shared diffusion puts devices in series, and two ends on the same nodes put them in parallel; then the stages and the function.

4a. The schematic (8 points).

Hint

Count the places where poly crosses diffusion. Then name every piece of diffusion between them by what it is contacted to.

What it asks. The transistor-level schematic: every transistor, its type, its gate signal, and the two nodes its ends connect to.

The idea. In a stick diagram (Chapter 9, Section 10) a poly line that crosses a diffusion line is a transistor: a PFET on p diffusion, an NFET on n diffusion, with the poly as its gate. The diffusion on either side is its source and drain. A contact ties a piece of diffusion, or a poly, to the metal above it, and the metal names the node. Two devices that share a piece of diffusion with no contact on it are in series; two whose ends land on the same two nodes are in parallel. The trap is the poly with no input label: follow its contact to its metal.

4a: the schematic (8 points)

1. Find the transistors. Each poly line crossing a diffusion line is one transistor (Chapter 9, Section 10). The short poly at the left crosses only the p row: one PFET. A, B and C cross only the n row: three NFETs.
2. The unlabelled gate. The PFET’s poly has no input label. It gets its signal through its contact, which sits on the metal running down to GND: its gate is at ground, so it is always on. (MT24-4’s fourth poly was also fed through a contact.)
3. The p row, read from its contacts: a contact to $V_{DD}$VDD​, the PFET, a contact wired to Y. The PFET runs from $V_{DD}$ to Y.
4. The n row, read the same way: GND, A, an uncontacted piece, B, a contact wired to Y, C, GND. A and B share the uncontacted piece, so they are in series from GND to Y; C runs from Y to GND, in parallel with that pair.
5. The two networks. Pull-down: (A–B) ∥ C. Pull-up: one PFET with its gate grounded. The pull-up is not the dual of the pull-down.

Question 4a: the pull-up is one PFET whose gate is GND (always on); the pull-down is A–B in series, in parallel with C.

Check. Count both ways. Four poly crossings give four transistors, one PFET and three NFETs, and every piece of diffusion has a name: $V_{DD}$ and Y on the p row; GND at both ends of the n row, the one uncontacted piece between A and B, and Y between B and C.

Answer (a): one PFET from $V_{DD}$ to Y with its gate at GND (always on); NFETs A and B in series from GND to Y, in parallel with NFET C (the schematic above).

Remember. Every poly crossing is a transistor. A poly without a label takes its signal from the metal its contact sits on, even when that metal is a rail.

4b. The function (4 points).

Hint

When does the pull-down conduct, and what is the always-on PFET doing then?

What it asks. The logic function at Y.

The idea. Y is low when the pull-down conducts and high when it doesn’t. Here the pull-up is always on, so “low” means that the NFETs overpower the PFET: a pseudo-NMOS gate, which works only if the PFET is weak (Chapter 10, Section 10). Read the function from the pull-down: series is AND, parallel is OR.

4b: the function (4 points)

1. When the pull-down conducts. A–B in series conducts when $AB$AB; C in parallel adds $+\,C$+C. So the pull-down conducts when $AB + C$C.
2. What Y does then. The NFETs pull Y low against the always-on PFET; otherwise the PFET holds it high.
3. The function. $Y = \overline{AB + C}$AB+C​: an AND-OR-invert with one AND of two inputs and one single input, the AOI21.

Check. Two rows. A = B = C = 0: no NFET path, the PFET holds Y high, and $\overline{0 + 0} = 1$1. ✓ C = 1: C alone pulls Y low, and $\overline{AB + 1} = 0$0. ✓

Answer (b): whenever $AB + C$ is true the NFETs pull Y low against the always-on PFET; otherwise the PFET holds it high: $Y = \overline{AB + C}$AB+C​, a pseudo-NMOS AND-OR-invert (AOI21) gate (Chapter 10, Section 10).

Remember. With a single always-on PFET, the gate computes the complement of its pull-down’s function, and the low is valid only if the NFETs win.

4c. Static or not (3 points).

Hint

In a state where Y is low, which transistors are on?

What it asks. Whether this is a static CMOS gate, and one consequence of the answer.

The idea. In complementary static CMOS the pull-up is the dual of the pull-down, so in every state exactly one network conducts and the output sits at a rail (Chapter 7, Section 4). If both networks can be on at once, the output is set by their strength ratio: the gate is ratioed (Chapter 10, Section 10).

4c: static or not (3 points)

1. Both networks on. Because the PFET is always on, both networks conduct whenever the pull-down does: the gate is ratioed, not static CMOS.
2. First consequence: the low. The low level is a divider between the PFET and the NFETs, so it sits above ground, and the PFET must be weak to keep it low.
3. Second consequence: static current. Current flows from $V_{DD}$ to ground for as long as the output is low.

Check. The trade is in the transistor count: 4 transistors here, against 6 for the complementary AOI21, whose pull-up would be (A ∥ B) in series with C.

Answer (c): No. Whenever the pull-down conducts, both networks are on: it is ratioed. The low level is not at ground (it is set by the strength ratio, so the PFET must be weak), and current flows from $V_{DD}$ to ground for as long as the output is low. In return it needs 4 transistors, against 6 for the complementary AOI21.

Remember. A pull-up that isn’t the dual of the pull-down makes a ratioed gate: a low above ground, and static current while the output is low.

The twist. Both past layouts were complementary gates. A poly tied to a rail is read by the same rule as MT24-4’s internal net: follow the contact to its metal.

Solution 5. The static path

This is the path-sizing question, and it takes the moves of page M4’s “How to approach a path-sizing question”: tabulate the stages, sum the gains, size back from the load at equal gains, add the side load to the one stage that drives its node, then retune. Part (c), the number of stages, is the twist.

Reading the path. Every part needs two numbers for each gate: its normalized inverter’s input (its strength) and the capacitance of one of its inputs (the load it puts on the stage before it). The NFET and PFET have equal strength, so an NFET and a PFET of the same width drive equally, and the balanced inverter is W/W, input $2W$ (Chapter 8, Section 1). Transistors in series act like one transistor of width $1/\sum(1/W_i)$ (Chapter 7, Section 8).

Reading the path gate by gate

1. Stage 1, an inverter W₁/W₁. It is its own normalized inverter: input $2W_1$2W1​, $g = 1$1.
2. Stage 2, the NOR3. When one input switches, one NFET of $W_2$ pulls down alone, and three PFETs of $3W_2$ in series pull up, acting as one of $W_2$W2​. So it has the drive of a $W_2$/$W_2$ inverter, input $2W_2$2W2​. One real input drives $W_2 + 3W_2 = 4W_2$4W2​, so $g = 4/2 = 2$2. The two unused inputs are tied to 0, which leaves their PFETs on and in the stack, as the worst case assumes.
3. Stage 3, the NAND2. Its two NFETs of $2W_3$ are in series and act as one of $W_3$W3​; one PFET of $W_3$ pulls up alone. So its normalized inverter is $W_3/W_3$W3​/W3​, input $2W_3$2W3​; one input is $3W_3$ and $g = 3/2$3/2. The unused input is tied to 1, which leaves its NFET on, in the stack.
4. Stage 4, an inverter W₄/W₄: input $2W_4$2W4​, $g = 1$1.
5. The load: $2\,\mathrm{pF}/(1\,\mathrm{fF/\mu m}) = 2000\,\mu\mathrm{m}$ of gate. A stage’s gain is the capacitance it drives over its normalized input, $2W_i$2Wi​.

5a. The delay as drawn (8 points).

Hint

Each stage’s gain is the next stage’s input (or the load) over its own normalized input, $2W_i$2Wi​.

What it asks. The delay of the path exactly as drawn, with $W_1$ to $W_4$ = 1, 2, 4 and 8 µm. Nothing is sized yet.

The idea. Delays are counted in $\tau_{inv}$τinv​, the fan-out-of-one delay of the balanced inverter. A gate behaves, for its delay, like its normalized inverter: the inverter with the same drive. So each stage takes $\tau_{inv}$ times its gain, the capacitance it drives over its normalized inverter’s input, and the path delay is $\tau_{inv}$ times the sum of the gains (Chapter 8, Section 2). The trap is dividing by the gate’s own input instead: that gives the electrical effort $h$h, not the gain.

5a: the delay as drawn (8 points)

1. Stage 1 drives one NOR input, $4W_2 = 8$8, from $2W_1 = 2$2: gain 4.
2. Stage 2 drives one NAND input, $3W_3 = 12$12, from $2W_2 = 4$4: gain 3.
3. Stage 3 drives $2W_4 = 16$ from $2W_3 = 8$8: gain 2.
4. Stage 4 drives 2000 from $2W_4 = 16$16: gain 125.
5. Add. Delay $= (4 + 3 + 2 + 125) \times 50\,\mathrm{ps} = 134\,\tau_{inv} = 6.70\,\mathrm{ns}$6.70ns.

Check. The four gains multiply to $4 \times 3 \times 2 \times 125 = 3000$3000, the path effort that (b) finds without any widths: the inner widths cancel in the product, so this is a check on the gains. And read the last gain as “how many copies of its own normalized inverter does it drive”: a 16 µm input driving 2000 µm, 125 copies.

Answer: $134\,\tau_{inv} = 6.70$ ns, nearly all of it in the last stage.

Remember. Gain = load ÷ normalized inverter’s input; delay = $\tau_{inv}$ × the sum of the gains. One gain of 125 next to gains of 2–4 says the path is badly sized.

5b. Equal-gain sizing (10 points).

Hint

Write the four gains with $W_2$W2​, $W_3$ and $W_4$ as unknowns and multiply them. What is left?

What it asks. Choose $W_2$W2​, $W_3$ and $W_4$ to make the delay as small as possible, with the first inverter fixed at 1 µm, and give the new delay. Fixing $W_1$ fixes the path’s input capacitance; without that you could make every gate huge and push the problem onto whatever drives A.

The idea. Two facts do all the work (Chapter 8, Section 2, Section 3). The product of the gains is fixed: each inner width appears once as a load (on top) and once as a strength (underneath), and cancels, leaving the path effort $F = G \cdot H$H, the product of the logical efforts times the load over the input. And with a fixed product, the sum of the gains is smallest when they are all equal, $f = F^{1/N}$F1/N: making one stage faster forces another to be slower by a larger factor. So set every gain to $f$ and size back from the load.

5b: equal-gain sizing (10 points)

1. The path effort (Chapter 8, Section 2): $F = G \cdot H = (1 \times 2 \times 1.5 \times 1) \times (2000/2) = 3000$3000, fixed whatever $W_2$–$W_4$ are.
2. Equal gains: $f = \sqrt[4]{3000} = 7.40$7.40.
3. Back from the load, because the load is known: the last stage’s equation has one unknown, and each step back adds one more (Chapter 8, Section 6). $2000/(2W_4) = f$f, $W_4 = 135.1\,\mu\mathrm{m}$135.1μm.
4. $2W_4/(2W_3) = f$f: $W_3 = 18.26\,\mu\mathrm{m}$18.26μm.
5. $3W_3/(2W_2) = f$f: $W_2 = 3.70\,\mu\mathrm{m}$3.70μm.
6. Stage 1 is not chosen; it checks the work: $4W_2/2 = 7.40$7.40. ✓ It has to come out at $f$f, because the four gains multiply to $F = f^4$f4. Delay $= 4f = 29.60\,\tau_{inv} = 1.48\,\mathrm{ns}$1.48ns.

Check. From 134 to 29.6 $\tau_{inv}$τinv​: 4.5 times faster, from resizing alone. A gain of 7.4 per stage is well above the 3 to 4 that Chapter 8 aims for, which says that more stages would help: that is part (c).

Answer: $W_2 = 3.70$3.70, $W_3 = 18.3$18.3, $W_4 = 135\,\mu\mathrm{m}$135μm; $29.6\,\tau_{inv} \approx 1.48$ ns.

Remember. With nothing branching off the path, $F$ is fixed: take $f = F^{1/N}$F1/N, size back from the load, and let the first stage check your arithmetic.

5c. How many stages (10 points).

Hint

A gain of 7.4 per stage is large. How many stages would bring it near 3 or 4, and what does adding an inverter do to the logic?

What it asks. Whether adding inverters can make the path faster, and if so how many, where, and the delay that results.

The idea. With $F$ fixed, an $N$-stage path at equal gains takes $N\,F^{1/N}\,\tau_{inv}$NF1/Nτinv​. More stages lower each stage’s gain but add a stage; the sum is least near a gain of $e$ per stage, about $\ln F$ stages added, and the curve is flat near its bottom, so gains of 3 to 4 are as good in practice (Chapter 8, Section 4). An inverter has $g = 1$1, so adding one leaves $F$ unchanged; but each inverts the logic, so they must come in pairs. Where they go doesn’t change the delay, but it changes how big the other gates must be (Chapter 8, Section 7).

5c: the twist, how many stages (10 points)

1. Is the gain too large? A gain of 7.4 per stage is well above the best of about $e$e, or 3 to 4 in practice (Chapter 8, Section 4). The best stage count is about $\ln F = \ln 3000 = 8.0$8.0.
2. Only pairs. Inverters must come in pairs, or the logic is inverted: 4, 6, 8 or 10 stages. Each inverter has $g = 1$1, so $F$ stays 3000.
3. Compare the counts with $N\,F^{1/N}$NF1/N: 4 stages 29.60, 6 stages $6 \times 3.80 = 22.79$22.79, 8 stages $8 \times 2.72 = 21.76$21.76, 10 stages 22.27 $\tau_{inv}$τinv​.
4. Weigh the gain. One pair takes the path from 1.48 ns to 1.14 ns (23% faster); a second pair gives 1.09 ns, only 4.5% more, for another two inverters.
5. Where: next to the load (Chapter 8, Section 7). The delay is the same wherever the equal-gain inverters go, but at the load end the other gates stay small: 755 µm of total transistor width, against 1310 µm with the pair at the input (and 426 µm for the four-stage path of b).

Check. At eight stages the gain is $3000^{1/8} = 2.72$2.72, which is $e$e: exactly what $\ln F = 8.0$ stages predicts. And the curve is flat near its bottom: 22.79, 21.76 and 22.27 $\tau_{inv}$ for 6, 8 and 10 stages.

Answer: Yes. Add one pair of inverters at the load end: six stages at $f = 3.80$3.80, $22.8\,\tau_{inv} \approx 1.14$ ns. Eight stages ($\ln F = 8$lnF=8) are marginally faster, 1.09 ns; either is a good answer if you say why.

Remember. About $\ln F$ stages is best, but the optimum is flat. Add inverters in pairs, and put them at the load end, where they keep the other gates small.

5d. The side load and retuning (12 points).

Hint

Which stage drives node C? Then: nothing branches between stages 1 and 2, so what stays fixed when only $W_2$ changes?

What it asks. First the delay with a 60 fF capacitor on node C and the sizes of (b); then a retuning of $W_2$W2​, $W_3$ and $W_4$W4​, with $W_1$ fixed, to bring it down. The exact minimum isn’t required, only a sensible method.

The idea. A side load is extra capacitance on one node, and each node is driven by one stage, so it raises that one stage’s gain. The 60 fF doesn’t grow when the gates grow, so the path effort now depends on the widths, and a recomputed $F^{1/4}$ is only a guess (Chapter 8, Section 8). But equal gains still hold on any piece of the path with nothing branching off it. So rebalance the overloaded stage with the one before it, then try a larger gate after the branch, balancing each side (Chapter 8, Section 9). The lecture enlarges first; that order pays off when the branch is most of the load, and here it is about half.

5d: the side load and retuning (12 points)

1. With the sizes of (b). The 60 fF hangs on node C, the output of stage 2. Stage 2 now drives $3W_3 + 60 = 54.8 + 60 = 114.8\,\mu\mathrm{m}$114.8μm: gain $114.8/7.40 = 15.51$15.51. The other three stay at 7.40.
2. The delay: $3 \times 7.40 + 15.51 = 37.71\,\tau_{inv} = 1.89\,\mathrm{ns}$1.89ns.
3. Which move first. The branch is 52% of stage 2’s load, so enlarging the NAND alone first makes things worse ($W_3 = 25$W3​= gives 38.45 $\tau_{inv}$τinv​); page M4 found the same for MT23-5 (page M4, Section 1). Rebalance the overloaded pair first.
4. Rebalance stages 1 and 2. Nothing branches between them; moving only $W_2$ keeps their product, $2W_2 \cdot 114.8/(2W_2) = 114.8$114.8, fixed, so make them equal: $\sqrt{114.8} = 10.71$ each, $W_2 = 5.36\,\mu\mathrm{m}$5.36μm. Delay $2(10.71) + 2(7.40) = 36.23\,\tau_{inv} = 1.81\,\mathrm{ns}$1.81ns.
5. Then enlarge the gate after the branch (Chapter 8, Section 9). Choose $W_3$ and balance each side: stages 1–2 share the product $3W_3 + 60$60, stages 3–4 the product $1000/W_3$1000/W3​, and a balanced pair with product $P$ contributes $2\sqrt{P}$2P​. So the delay for a chosen $W_3$ is $2\sqrt{3W_3 + 60} + 2\sqrt{1000/W_3}$21000/W3​​: 36.23 at $W_3 = 18.3$18.3, 36.05 at 20, 35.89 at 25, 36.04 at 30.
6. Take the best of those. $W_3 = 25\,\mu\mathrm{m}$25μm: stages 1–2 at $\sqrt{135} = 11.62$ each ($W_2 = 5.81\,\mu\mathrm{m}$W2​=5.81μm), stages 3–4 at $\sqrt{40} = 6.32$ each ($W_4 = 158\,\mu\mathrm{m}$W4​=158μm). Delay $35.89\,\tau_{inv} = 1.79\,\mathrm{ns}$1.79ns, the minimum to within 0.1%.

Check. At $W_3 = 18.3$18.3, the size from (b), the split formula of step 5 gives 36.23, the same as the rebalance of step 4: the formula contains the first move as a special case. And the delay rose in step 2 by $37.71 - 29.60 = 8.11\,\tau_{inv}$8.11τinv​, exactly stage 2’s rise from 7.40 to 15.51: nothing else moved.

Answer: $37.7\,\tau_{inv} \approx 1.89$ ns with the sizes of (b). Rebalancing $W_2$ alone gives 1.81 ns; with $W_2 = 5.8$5.8, $W_3 = 25$25, $W_4 = 158\,\mu\mathrm{m}$158μm, 1.79 ns. Full marks need the method (rebalance, then trade the two sides), not the exact minimum.

Remember. A side load changes one gain, that of the stage driving its node. With a branch, balance pieces, not the whole path: rebalance the overloaded pair first, then trade the two sides.

Score yourself

The past keys gave partial credit for a reasonable attempt with an explanation, so mark generously for a correct method with an arithmetic slip, and harshly for a right number with no reasoning.

Question	Points	Most-missed parts	Review
1. Inverter chain	50	1b (1.5W off width), 1e (only the slope scales; W unchanged)	page M3, Sections 1–2; Chapter 4, Section 11; Chapter 6, Section 6
2. Pass-transistor gate	45	2a (the transition argument), 2c (one threshold, not two), 2d (the low stays weak)	page M5, Sections 1–2; Chapter 10, Sections 4–6
3. Domino gate	50	3b (footer in k, skewed g = 3/4), 3c (the branch), 3e (the tenth, then the series PFETs)	Chapter 12, Sections 2–4; Chapter 11, Sections 7–9; page M6
4. Stick layout	15	4a (the grounded poly), 4c (ratioed)	page M5, Section 5; Chapter 9, Section 10
5. Static path	40	5c (pairs, at the load), 5d (rebalance first)	page M4; Chapter 8, Sections 4, 7–9

What this exam drilled, family by family.

• Inverter chain. Node capacitance first; per cycle every node rises once; the off device leaks with $V_{DD}$ across it; with $T_{cycle}$ equal to the chain delay, $W$ cancels from the leakage share; energy × delay is least where the gates’ load equals the side load. New here: temperature moves the slope, nothing else.
• Pass-transistor logic. Read each node as a two-way switch. Static means one path to one rail for every input, and no fight on any transition. One threshold per path with full gates, a second only through a degraded gate. A PFET half latch fixes highs, not lows.
• Domino. Size only the logic edge; $g = k/3$ (footer counted) or $k/2$ at equal strengths; the skewed inverter’s rising $g$ is 3/4 at 8:1; a branch enters through $B$B; the half latch is a tenth of the pull-down, from Y to a PFET on X; a skewed inverter costs $NM_H$NMH​.
• Stick layout. One transistor per poly crossing; uncontacted pieces mean series; a poly without a label takes its signal from its contact, even a rail.
• Path sizing. $F = G \cdot H \cdot B$B; equal gains back from the load; about $\ln F$ stages, inverters in pairs at the load end; with a fixed side load, rebalance the overloaded pair first, then trade the two sides.