E4321 midterm study guide

This guide teaches the device physics and circuits behind E4321 from the ground up, one lecture at a time. It is built from the historical lightboard recordings: the boards are real video frames, and every formula is checked against them.

Preparing for the midterm? Start with M1. What to expect, then work through the midterm kit and finish with the practice midterm.

Chapters

0. Toolkit: units, constants, logarithms, one-dimensional electrostatics, band diagrams and capacitance, the tools the lectures assume.
1. The big picture (Lecture 1): Moore’s law and Dennard scaling, technology nodes, levels of abstraction and CAD tools, analog versus digital, why silicon CMOS, and the device-physics road map.
2. Semiconductor basics (Lecture 2): silicon and its units, bands, intrinsic carriers, doping, the Fermi–Dirac function and the Fermi level; making a pn junction, its barrier, and why it is a diode.
3. The pn junction and the MOS capacitor (Lecture 3): built-in voltage, depletion width and capacitance; the MOS transistor’s structure; depletion, inversion and the threshold voltage.
4. Transport and the MOSFET I–V (Lecture 4): drift velocity, mobility and velocity saturation; the long-channel and velocity-saturated I–V models; Dennard scaling and why it broke; subthreshold slope, short-channel effects and gate leakage; exam-style checks from MT17, MT23 and MT24.
5. Body effect, capacitance and delay (Lecture 5): the body effect; MOS, overlap and junction capacitances; g_m, f_T and the transit time; FO1 and FO4 delays; exam-style checks from MT17 and MT21.
6. The CMOS inverter (Lecture 6): the voltage transfer characteristic from the two I–V curves; noise rejection and noise margins; switching energy, dynamic power and crowbar current; compact models and process corners; delay and slew.
7. Delay models and static CMOS gates (Lecture 7): the simplified delay model with C_g in fF/µm and R in kΩ·µm, and how to characterize them; static and complementary CMOS, NOR, NAND and AOI gates, pin swapping and stacks; FO1 = τ_inv, logical effort, electrical effort and gain.
8. Logical effort and path sizing (Lecture 8): path effort, equal gains, the best number of stages, branching and retuning, and why the bottom of a stack is slow.
9. Fabrication and layout (Lecture 9): from layout to masks, the RX/NW/PC/BP/CA layers and reverse toning, the 5-2-2 metal stack, CMP, design rules, DRC/LVS/extraction, the layout image, an inverter layout and stick diagrams.
10. Pass-transistor and ratioed logic (Lecture 10): Euler-path diffusion sharing, the b/a/s device models and fingers; pass-transistor logic, V_DD − V_T and its two fixes, one-hot multiplexers, channel-connected components, the ratioed 6T XOR and pseudo-NMOS.
11. Dynamic and domino logic (Lecture 11): pass-transistor sizing, precharge and evaluate, the race and domino logic, and the noise on a dynamic node (leakage, charge sharing, coupling, supply) with the half latch and babysit devices.
12. Domino sizing and delayed reset (Lecture 12, to the 23:15 midterm cutoff): dynamic logical effort, sizing a domino gate by gain, NP (zipper) domino and p-type stages, and footless domino on delayed-reset clocks.

Midterm kit

For the Fall 2026 midterm: what to expect, then the four past midterms (MT17, MT21, MT23, MT24) re-solved by question family, newest first, with the answer keys’ errors marked. Every worked solution in the kit teaches the approach: a “How to approach” section for each question family, then, in each part, what it asks, the idea behind the method, steps that give their reasons, a check and one thing to remember.

M1. What to expect on the midterm: the format, where the points went on MT17–MT24, the Fall 2026 signals, a labelled guess, and a study plan ordered by expected points. Start here.
M2. Formula sheet: every midterm formula by exam family, with its meaning, conditions and chapter section; which model a question wants; units, constants and the exams’ conventions; common mistakes, including the answer keys’ errors. It has a recall mode that hides the formulas.
M3. Past midterms: inverters, energy and devices: every inverter-chain energy and leakage, noise-margin, τ_inv-delay and device short-answer part, re-solved step by step.
M4. Past midterms: path sizing: MT23-5, MT21-5 and MT17-5 (gains, equal-gain sizing, a side branch, retuning), with a widget for retuning around a branch.
M5. Past midterms: pass transistors and layout: MT24-3, MT23-2, MT21-1 and MT21-3, and the stick layouts MT24-4 and MT23-4.
M6. Past midterms: dynamic and domino logic: MT24-5, MT23-3 and MT17-3c re-solved, with FN12-8 and FN17-2 as drills.
M7. Practice midterm: a new five-question, 75-minute, 200-point exam in the MT23/MT24 pattern, then stepped solutions and a score sheet. Take it with a timer after M1–M6.

Homework review

Homework 1–4 re-solved in the homework’s own order, limited to the parts related to the midterm, with the keys’ errors marked; each page ends by naming the midterm family that uses each method. The solutions teach the approach in the same way as the midterm kit’s.

H1. Homework 1: MOSFET I–V, junction capacitance and scaling: PMOS I–V curves with and without velocity saturation, a junction’s capacitance range, capacitors discharged through transistors, subthreshold current, v_sat and width from I–V curves, and scaling with a field factor. HW1-2d (a bipolar transistor) is out: the course doesn’t teach the BJT.
H2. Homework 2: device parameters from simulated I–V curves: v_sat, V_T and the subthreshold slope from the key’s Cadence readings, and how to tell velocity saturation from the square law by reading the curves.
H3. Homework 3: delay calibration, crowbar energy and path sizing: the C_g and R benches behind every exam’s numbers (the key’s R comes out twice too large), drain capacitance, crowbar energy against input slew, and sizing a NAND–XOR–inverter path with the best number of stages.
H4. Homework 4: stick layout, gain-based design and CPL: a three-inverter stick layout and its delay, a four-input XOR designed by gain within an input-capacitance limit, and CPL gates, a CPL full adder and cross-coupled PFETs; the simulation and layout-tool parts are explained as methods.

Finals review

The parts of the four past finals (FN10, FN12, FN17, FN19) that test midterm material, re-solved by question family, newest exam first, with the keys’ errors marked; FN19 has no key. The solutions teach the approach in the same way as the midterm kit’s. Latches and clocking, wires and Elmore delay, power grids, test, memory, datapath blocks and PLAs are left out.

F1. Past finals: devices: the device short answers: DIBL, threshold roll-off and halo doping, the threshold against oxide thickness, subthreshold leakage with a raised source and in a stack, the body effect in a shifted-supply inverter, why FO1 is more than a quarter of FO4, and how delay depends on the supply.
F2. Past finals: inverters, chains and low-voltage operation: an inverter run below threshold (I_off, I_on/I_off, delay and power) and chains of inverting stages (delay, energy per transition, the delay-optimal width). The supply that minimizes energy and the lowest working supply are left out.
F3. Past finals: path sizing: a path with an input-capacitance limit and a 500 fF branch (MT21-5’s shape), and two dynamic-to-static paths sized within a β limit, one with a side branch; FN12-8 links to M6.
F4. Past finals: pass-transistor and dynamic logic: a dynamic OR that resets itself, charge sharing and its fixes, NP domino, a differential XOR, and a pass-transistor network that counts ones (the key misses that its outputs can float) with its static CMOS equivalent; FN17-2 links to M6.

How the chapters work

Each concept follows the same steps: the idea in one sentence, a picture, an interactive where it helps, the math one step at a time, a worked example, common mistakes, and a “check yourself” question with a hidden answer.

board marks content written on the board in the lecture; added marks explanations and examples the guide adds.
Board frames show their time in the recording, for example Lecture03 @ 24:58. Recordings are not hosted in this copy. Use the timestamps with your local recordings; all board images are included.
Times in parentheses, like (13:44), point to where the lecture says it.