F1. Past finals: devices

The finals open with device short answers: a few sentences, sometimes one line of arithmetic, on why the threshold moves, how much a transistor leaks, what the body effect does to a gate, and what sets a delay. This page re-solves every such part of the four past finals that the midterm material covers, grouped by family, newest exam first. The midterm asks the same kind of question (MT17-1b–c, MT21-2; see M3), so these are extra practice for the same points.

Every number below is re-solved here and checked in this page’s review/examples.check.ts; none is copied from a key. Where a key disagrees or leaves something out, the folded note on the key at the end of the part explains it, and the table at the end lists them all. The 2019 final has no key: its parts are solved independently, with no other solution shown.

After this page you can:

1. explain DIBL, threshold roll-off and inverse roll-off from the share of the bulk charge the gate controls;
2. say which way the threshold moves with the oxide thickness, and why;
3. turn a current-defined threshold into decades of leakage, with the source raised or in a stack;
4. say which edge of a gate the body effect slows, and by about how much;
5. explain why FO1 is more than a quarter of FO4;
6. find how sensitive a delay is to the supply, for a velocity-saturated and a square-law device.

Before you start

How to use this page. Each part is restated with its source page (FN12-1b, p3 is the Fall 2012 final, question 1b, physical PDF page 3) and its points, and shows the exam’s figure where it has one. The threshold family opens with a short How to approach section: how to recognize the question, the moves in order, why the formulas apply, and the traps. The other families use the midterm page’s approach sections, and each one’s first part links them. Then every part is worked the same way: what it asks, the idea behind the method, the solution in steps (each step gives its reason first), a check on the result, the answer, and one thing to remember. Try each part on your own first; open the Hint if you are stuck, and step through the solution before you press “Show all”. The answer key’s verdict is folded at the end of each part. The chapters teach each method in full, and every solution links the section.

Family	Parts (newest first)	Points	Chapters
The threshold: short channels and the oxide	FN19-2a, 2b, 2c (partial), FN17-1a, FN17-1c	30 + 10	3, 4
Subthreshold leakage: a defined threshold, a raised source, a stack	FN12-1a–c	18	4, 5, 7
The body effect in a shifted-supply inverter	FN10-1	10	5
Delay as charge over current: FO1, FO4 and the supply	FN12-2, FN10-6a–b	6 + 20	4, 5

The rest of these questions is on later topics and left out: FN17-1b, 1d and 1e (decoupling capacitance, clock latency, infant mortality) and FN10-6c–d (clock jitter and hold failure).

Conventions.

• An NFET’s threshold falls when the gate has less bulk charge to hold: $V_T = V_{FB} + 2\phi_F + Q_{bulk}/C_{ox}$ (Chapter 3, Section 8). For a PFET read $|V_T|$∣VT​∣.
• Subthreshold current changes tenfold per $S$ millivolts of $V_{GS}$VGS​: $I = I(V_T)\times10^{(V_{GS} - V_T)/S}$ (Chapter 4, Section 11). The course treats it as independent of $V_{DS}$ once DIBL is ignored.
• A delay is charge over current: $t \approx V_{DD}C/I_{DSAT}$ (Chapter 5, Section 11). Chapter 7’s $R$ is a fitted constant with no supply dependence, so supply questions go back to the currents.

How to approach a threshold question

Recognize it by its wording. The question names a change to the device or to how it is wired (a higher $V_{DS}$VDS​, a shorter channel, halo doping, a thinner oxide, a source above the body) and asks “why is this?” or “how does $V_T$ vary with …?”. There is rarely a number to compute: the points are for a cause-and-effect chain of three or four sentences. FN19-2 carried 30 points, FN17-1a and 1c 10 together, and FN10-1 10. FN12-1c leans on the same reasoning.

The moves, in order.

1. Write the threshold: $V_T = V_{FB} + 2\phi_F + Q_{bulk}/C_{ox}$Qbulk​/Cox​. Every answer in this family comes out of one of its terms.
2. Name the term the change touches. The drain or the source taking a share of $Q_{bulk}$ (DIBL, roll-off); the body doping, through $Q_{bulk}$ and $\phi_F$ (halos); $t_{ox}$tox​, through $C_{ox}$Cox​; $V_{SB}$VSB​, through $Q_{bulk}$ (the body effect).
3. Say which way it moves, as a chain. “A wider drain depletion region holds part of the charge, so the gate holds less, so $Q_{bulk}/C_{ox}$ falls, so $V_T$ falls.” Each link needs its because.
4. Say what that does to the device: its current, its delay or its leakage. A lower $V_T$ means more overdrive and more leakage; a higher one, less of both.

Why these formulas.

• The threshold. At threshold the gate voltage is split into three parts: $V_{FB}$VFB​, the offset from the gate’s and the silicon’s work functions; $2\phi_F$2ϕF​, the band bending that inverts the surface; and $Q_{bulk}/C_{ox}$Qbulk​/Cox​, the voltage across the oxide needed to hold the depletion charge under the gate. The oxide is a capacitor, $C_{ox} = \kappa_{ox}\varepsilon_0/t_{ox}$ per unit area, and $\phi_F = (kT/q)\ln(N_A/n_i)$(kT/q)ln(NA​/ni​). The formula holds for a uniformly doped body at the strong-inversion criterion, measured from the gate to the source (Chapter 3, Section 8).
• The bulk charge. $Q_{bulk} = \sqrt{2\kappa_s\varepsilon_0(2\phi_F + V_{SB})qN_A}$ is the charge of the depletion region under the gate. It grows as $\sqrt{N_A}$ with the doping and with a source-to-body reverse bias $V_{SB} \ge 0$ (Chapter 5, Section 1). In a short channel the source’s and the drain’s depletion regions reach under the gate and hold part of that charge themselves, so the gate has less to hold (Chapter 4, Section 12).
• What the device does with it. Above threshold the current depends on the overdrive $V_{GS} - V_T$VT​: in proportion when velocity saturated (Chapter 4, Section 7), as its square in the long-channel square law (Chapter 4, Section 4). Below threshold it falls one decade for every $S$ millivolts below $V_T$ (Chapter 4, Section 11).

Decisions to make on the way. NFET or PFET: for a PFET, read $|V_T|$ and $|V_{DS}|$∣VDS​∣, and remember that its body is the n well. Then each device’s own $V_{GS}$ and $V_{SB}$VSB​, measured from its own source, not from ground.

Traps. “The gate has full control of the bulk charge” (FN17-1c’s key): the oxide thickness doesn’t change $Q_{bulk}$Qbulk​, only the voltage needed to hold it. Comparing absolute voltages instead of each device’s $V_{GS}$ and $V_{SB}$ (FN10-1’s circuit runs from 2.5 to 5 V). Adding $V_{SB}$ to $V_T$ itself: it enters only under the root. A direction with no because.

1. The threshold: short channels and the oxide

Lecture04 @ 68:40DIBL (top right), its effect on the I–V (top left), and V_T roll-off (centre).

FN19-2a: the threshold falls as V_DS rises

FN19-2, p5 (Fall 2019). Consider short-channel effects. Remember that device $V_T$ is strongly affected by bulk charge under the channel.

(a) (10 points) One typically finds that the magnitude of the threshold voltage of a short-channel device decreases with increasing $V_{DS}$VDS​. Why is this?

Hint

Which term of the threshold holds the bulk charge, and what does a higher drain voltage do to the region around the drain?

What it asks. Why a short transistor’s threshold falls when its drain voltage rises. The words “short-channel” and the stem’s “bulk charge under the channel” decide the method: an argument about who holds the depletion charge under the gate.

The idea. The gate must hold all of $Q_{bulk}$ through the oxide, and that sets the threshold’s term $Q_{bulk}/C_{ox}$ (How to approach). The drain is a reverse-biased junction, so its depletion region widens as $V_{DS}$ rises (Chapter 3, Section 4). Depletion widths didn’t shrink with the channel length, so in a short device the drain’s region reaches under the gate and holds part of the charge there. This is charge sharing, and it is how Lecture 4 explains every short-channel effect (Chapter 4, Section 12). The long-channel picture, in which $V_T$ doesn’t depend on $V_{DS}$ at all, can’t explain the effect.

DIBL

1. Start from the threshold. Because the stem points at the bulk charge, write $V_T = V_{FB} + 2\phi_F + Q_{bulk}/C_{ox}$Qbulk​/Cox​. The gate must support all of $Q_{bulk}$ through the oxide (Chapter 4, Section 12).
2. The drain’s depletion region grows. The drain is a reverse-biased junction, so raising $V_{DS}$ widens its depletion region (Chapter 3). Depletion widths did not scale with the channel, so in a short device that region reaches under the gate (64:30).
3. The gate holds less. Because the drain now holds part of the depletion charge under the channel, the gate controls less of it: $Q_{bulk}$ in the formula falls (64:58–65:24).
4. So the threshold falls. A smaller $Q_{bulk}/C_{ox}$ gives a lower $|V_T|$∣VT​∣, and more so the higher $V_{DS}$VDS​. This is drain-induced barrier lowering, DIBL. (For a PFET read $|V_{DS}|$ and $|V_T|$∣VT​∣.)
5. Why only short devices. In a long device the drain’s depletion region is a small part of the channel, so its share is negligible: DIBL is a short-channel effect.

Check. The long-channel limit. As $L$ grows, the drain’s share of the charge under the gate goes to zero, and $V_T$ stops depending on $V_{DS}$VDS​: the flat saturated current of the long-channel I–V (Chapter 4, Section 4). The effect has the right sign too: the board’s I–V (top left) keeps rising in saturation, as a falling $V_T$ requires.

Answer: DIBL. A larger $V_{DS}$ widens the drain’s depletion region, which takes over part of the bulk charge under the gate; the gate has less $Q_{bulk}$ to hold, so $|V_T|$ falls.

Remember. A short-channel question is charge sharing. Say who else holds part of $Q_{bulk}$Qbulk​, and the threshold falls with it. With DIBL, the drain’s share grows with $V_{DS}$VDS​.

FN19-2b: the threshold falls as the channel shortens

FN19-2b, p5 (10 points). Before the advent of advanced halo doping techniques, one found that circuits with smaller channel lengths had threshold voltage of lower magnitude. Why was this? This is the effect we described in class as “$V_T$VT​ rolloff.”

Hint

Which lengths in the device shrink with $L$L, and which don’t?

What it asks. Why shorter transistors had lower thresholds before halo doping: “$V_T$VT​ roll-off”. The variable is now the channel length, at a fixed $V_{DS}$VDS​.

The idea. The charge-sharing argument of (a), with $L$ as the variable instead of $V_{DS}$VDS​. The source and the drain have depletion regions even at low $V_{DS}$VDS​, from their built-in voltages, and those regions hold the charge at the two ends of the channel. Their widths are set by the doping and the junction voltages, not by $L$ (Chapter 3, Section 3). So what matters is their share of the region under the gate, and that share grows as $L$ shrinks (Chapter 4, Section 12).

Roll-off

1. The ends of the channel belong to the junctions. Even at low $V_{DS}$ the source and the drain have depletion regions, and they hold the charge at the two ends of the channel (Chapter 4, Section 12, 67:15).
2. Their share grows as L shrinks. Their width is set by the doping and the junction voltages, not by $L$L. So as $L$ shrinks they hold a larger share of the charge under the gate (67:44).
3. So the threshold falls. Because the gate is left with less $Q_{bulk}$ per unit area, $|V_T|$ falls with $L$L: $V_T$ roll-off. The drain, being reverse-biased, has the wider region and contributes the larger part.
4. Why it matters (68:13). $L$ varies from device to device with lithography. Where $V_T(L)$ is steep, that becomes threshold variation, so $L_{min}$ is placed where the curve is flat.

Check. The two ends of the curve. At long $L$ the junctions’ shares vanish and $V_T$ approaches Chapter 3’s long-channel value, so the curve is flat; at short $L$ the shares grow and it falls. That is the shape of the board’s “$V_T$VT​ rolloff” plot (centre).

Answer: at short $L$ the source and drain depletion regions, which don’t shrink with $L$L, hold a larger share of the bulk charge under the gate; the gate holds less, so $|V_T|$ is lower.

Remember. Roll-off is DIBL’s argument with $L$ as the variable: regions of fixed width take a larger share of a shorter channel. Put $L_{min}$ where $V_T(L)$ is flat.

FN19-2c: halo doping and inverse roll-off (partial)

FN19-2c, p6 (source figure): p⁺ halo regions directly under the n⁺ source and drain.

FN19-2c, p6 (10 points). Modern device technologies have introduced halo doping. In this case, the region directly under the source and drain is more heavily doped than the substrate as a whole. This helps control the extent of the source and drain depletion regions. The case of the nFET is shown below. In the presence of halo doping, one generally finds an “inverse” rolloff in which smaller channel lengths lead to higher magnitude threshold voltages. Why might this be?

Partial. Lecture 4 names inverse roll-off, “with some of these more complicated doping tricks” (68:45), and draws it (72:49), but never says “halo” and never says why the threshold rises. The answer below uses only what the course does teach; the picture of halo pockets averaging into the channel’s doping goes beyond the lecture.

Lecture04 @ 72:49Inverse roll-off: the V_T(L) curve with its hump before the roll-off (centre).

Hint

Which term of the threshold depends on the body doping, and what do the halos change about the doping under the gate?

What it asks. With halo doping, shorter channels have higher thresholds: the opposite of (b). Why “might” this be? The word “might” asks for a plausible mechanism, argued from the threshold formula.

The idea. The threshold now rises, so the mechanism must give the gate more charge to hold, not less. The doping is the term to look at: $Q_{bulk} = \sqrt{2\kappa_s\varepsilon_0(2\phi_F)\,qN_A}$ grows as $\sqrt{N_A}$NA​​, so heavier doping under the gate raises $V_T$ (Chapter 3, Section 8). The halos are pockets of heavier doping of fixed size at the two ends of the channel. As $L$ shrinks they make up more of it, so the doping the gate sees rises added. They also narrow the source and drain depletion regions, which works against (b)‘s roll-off.

Inverse roll-off

1. Find the term. Because the threshold rises, look for something that adds charge: the oxide term grows with the body doping, $Q_{bulk} = \sqrt{2\kappa_s\varepsilon_0(2\phi_F)\,qN_A}$2κs​ε0​(2ϕF​)qNA​​, so $V_T$ rises roughly as $\sqrt{N_A}$ (Chapter 3, Section 8). Real devices shape the doping profile to control short-channel effects (Chapter 3, Section 10).
2. Long channels see the substrate. The halo regions sit at the two ends of the channel, and their size does not shrink with $L$L. In a long device they are a small part of the region under the gate, which sees mostly the substrate’s doping.
3. Short channels see the halos. As $L$ shrinks, the two halos make up a larger fraction of the channel, and finally they meet. So the doping the gate must deplete, averaged along the channel, rises added.
4. So the threshold rises. More doping means more $Q_{bulk}$ for the gate to hold, so $V_T$ rises as $L$ shrinks: inverse roll-off.
5. The roll-off is delayed, not gone. Because heavier doping keeps the source and drain depletion regions narrow (width $\propto 1/\sqrt{N}$1/N​, Chapter 3), they take less of the gate’s charge, and the ordinary roll-off of part (b) sets in later. At still shorter $L$ it wins again, and $V_T$ rolls off, as the board’s curve shows.

Check. added The steps must reproduce the board’s hump, and in the halo-averaging picture they do. Once the halos meet, a shorter channel can’t raise the average doping any further, while the junctions’ share of the charge keeps growing. So the rise has to stop and turn into a roll-off at the shortest lengths: up first, then down.

Answer: at short $L$ the heavily doped halo regions fill a larger share of the channel, so the gate must hold more bulk charge, $Q_{bulk} \propto \sqrt{N_A}$NA​​, and $|V_T|$ rises; at the same time the halos keep the source and drain depletion regions small, so the charge-sharing roll-off of part (b) sets in only at shorter lengths.

How big? added In Chapter 3’s worked device ($t_{ox} = 5\,\mathrm{nm}$tox​=5nm), doubling the doping from $10^{17}$ to $2\times10^{17}\,\mathrm{cm^{-3}}$ raises the oxide term $Q_{bulk}/C_{ox}$ from 0.241 V to 0.348 V and $2\phi_F$ from 0.833 V to 0.869 V. A modest change in the average doping moves $V_T$ by a tenth of a volt or more.

Remember. Ask which way the charge moves. Anything that adds doping under the gate raises $V_T$VT​; anything that takes charge off the gate lowers it. With halos, the first wins at moderate lengths and the second at the shortest.

FN17-1a: DIBL against channel length

FN17-1a, p2 (Fall 2017, 5 points). How is drain-induced barrier lowering (DIBL) affected by device channel length? Why? What effect does DIBL have on MOS device characteristic?

Hint

You have the mechanism from FN19-2a. If $V_T$ falls as $V_{DS}$ rises, what happens to the overdrive along a saturated curve?

What it asks. Three things in 5 points: how DIBL depends on $L$L, why, and what it does to the device’s characteristic (its I–V curves).

The idea. The mechanism is FN19-2a’s: the drain’s depletion region takes a share of the charge under the gate. What this question adds is the approach section’s last move: say what the moved threshold does to the device. In saturation the current depends on the overdrive $V_{GS} - V_T$ (Chapter 4, Section 7), so a $V_T$ that falls with $V_{DS}$ gives a current that rises with $V_{DS}$VDS​. Below threshold the current depends on how far $V_{GS}$ is below $V_T$VT​, so the leakage rises too.

1. Shorter channels have more DIBL. Because the drain’s depletion region does not shrink with $L$L, it takes a larger share of the bulk charge under a shorter gate (the argument of FN19-2a and 2b).
2. The saturated curves slope. Because in saturation the current is set by the overdrive, a higher $V_{DS}$ that lowers $V_T$ raises the overdrive and so raises the current (Chapter 4, Section 12, 66:03–66:42). The saturated curves slope upward: a finite output conductance; the device is no longer a current source.
3. The off-state leaks more added. Because the off device has $V_{DS} = V_{DD}$VDD​, it has the lowest $V_T$VT​, and so more subthreshold leakage (Chapter 4, Section 11). This is why FN12-1 and FN19-1 say “ignore DIBL”.

Check. The sign. A lower $V_T$ means more current, so the saturated curves must slope up with $V_{DS}$VDS​, never down; the board’s I–V sketch (top left) slopes up. And in the long-channel limit the slope disappears, as step 1 requires.

Answer: DIBL grows as $L$ shrinks, because the drain controls a larger share of the bulk charge; it makes $V_T$ fall with $V_{DS}$VDS​, which gives the saturated I–V curves a slope (lower output resistance) and raises the off-state leakage.

Remember. For “what effect on the characteristic”, follow $V_T$ into the overdrive: a threshold that falls with $V_{DS}$ gives a saturated current that rises with $V_{DS}$VDS​, and more leakage when off.

The answer key agrees

FN17-1c: the threshold against oxide thickness

FN17-1c, p2 (5 points). How does the transistor threshold voltage of an nMOS transistor vary with oxide thickness? Explain.

Hint

Which of the threshold’s three terms contains $t_{ox}$tox​?

What it asks. Which way an NFET’s threshold moves when its gate oxide is made thinner or thicker, and why. “Explain” says that the reason carries the points.

The idea. The approach section’s second move: find the term the change touches. The oxide thickness enters only through $C_{ox} = \kappa_{ox}\varepsilon_0/t_{ox}$κox​ε0​/tox​, so only the oxide term $Q_{bulk}/C_{ox}$ moves (Chapter 3, Section 8). The oxide is a capacitor that must hold the charge $Q_{bulk}$Qbulk​, and a capacitor’s voltage is its charge over its capacitance. The tempting reason, “a thinner oxide gives the gate more control over the bulk charge”, is wrong: $Q_{bulk}$ is set by the body doping and doesn’t change with $t_{ox}$tox​. Only the voltage needed to hold it does.

1. Write the threshold. Because $t_{ox}$ could enter any of its terms, start from the whole formula: $V_T = V_{FB} + 2\phi_F + Q_{bulk}/C_{ox}$Qbulk​/Cox​, with $C_{ox} = \kappa_{ox}\varepsilon_0/t_{ox}$ (Chapter 3, Section 8).
2. Find the term. $2\phi_F$ and $Q_{bulk}$ depend only on the body doping. Only the oxide term depends on $t_{ox}$tox​, and it is proportional to it: the oxide is a capacitor that must hold $Q_{bulk}$Qbulk​, and a thinner one needs less voltage to do it.
3. Say which way. So a thinner oxide gives a lower $V_T$VT​, a thicker one a higher $V_T$VT​. In Chapter 3’s device ($10^{17}\,\mathrm{cm^{-3}}$1017cm−3, $V_{FB} = 0$0) the oxide term is 0.120, 0.241 and 0.482 V at 2.5, 5 and 10 nm, so $V_T$ is 0.954, 1.074 and 1.315 V.
4. What else it does. Because the body effect’s growing term is the same $Q_{bulk}/C_{ox}$Qbulk​/Cox​, a thinner oxide also shrinks the body effect (Chapter 5, Section 1).

Check. Only one term moves, so each change in $V_T$ must equal the change in the oxide term: $1.315 - 1.074 = 0.241\,\mathrm{V}$ from 5 to 10 nm, and $1.074 - 0.954 = 0.120\,\mathrm{V}$ from 2.5 to 5 nm. ✓ Doubling $t_{ox}$ doubles the oxide term each time, as proportionality requires.

Answer: $V_T$ falls as $t_{ox}$ falls (and rises as it grows), because the voltage across the oxide needed to hold the depletion charge, $Q_{bulk}/C_{ox} = Q_{bulk}t_{ox}/\kappa_{ox}\varepsilon_0$Qbulk​tox​/κox​ε0​, is proportional to $t_{ox}$tox​.

Remember. One term at a time. $t_{ox}$ enters only through $C_{ox}$Cox​: a thinner oxide lowers $V_T$ and shrinks the body effect. The doping enters through $Q_{bulk}$ and $\phi_F$ϕF​.

The answer key differs

It gives the same direction, but its reason, “the gate has full control of the bulk charge”, is loose: $Q_{bulk}$ does not change with $t_{ox}$tox​; the voltage needed to hold it does.

Check yourself A process thins the gate oxide from 5 nm to 2.5 nm and wants to keep V_T. Which way must the body doping move?

Up. The oxide term halves (0.241 → 0.120 V in Chapter 3’s device), so $Q_{bulk} \propto \sqrt{N_A}$ must grow to make it up, or $V_{FB}$ must be changed by the gate material (Chapter 3, Section 10).

2. Subthreshold leakage: a defined threshold, a raised source, a stack

FN12-1a: a threshold defined by a current

FN12-1a, p2 (source figure).

FN12-1a, p2 (Fall 2012, 6 points). If the nFET threshold voltage is defined by a saturated drain current of $100\,\mu\mathrm{A}$ through a $10\,\mu\mathrm{m}/0.18\,\mu\mathrm{m}$ device, what is the threshold voltage of the device above if the drain leakage current is 100 nA? Please ignore DIBL and assume a 80 mV/decade subthreshold slope.

Hint

From the current that defines the threshold down to the leakage at $V_{GS} = 0$0, how many decades does the current fall?

What it asks. The threshold is defined as the $V_{GS}$ at which the device carries 100 µA in saturation, and at $V_{GS} = 0$ it leaks 100 nA. Find $V_T$VT​. The words “defined by a saturated drain current” decide the method: this threshold is a point on the current curve, so the gate voltage between it and zero follows from the two currents.

The idea. This is the subthreshold count of M3’s device short answers, run backwards: from two currents to a voltage, instead of from a voltage to a current. Below threshold the current changes tenfold for every $S$ millivolts of $V_{GS}$VGS​, $I = I(V_T)\times10^{(V_{GS} - V_T)/S}$ (Chapter 4, Section 11). With DIBL ignored, $V_{DS}$ doesn’t change it. Put $V_{GS} = 0$ and solve: $V_T = S\log_{10}\bigl(I(V_T)/I_{off}\bigr)$Slog10​(I(VT​)/Ioff​). The threshold here is the current-criterion one, $V_{T,sat}$VT,sat​, not the physics one (Chapter 4, Section 8).

1. Which threshold. Because the question defines it by a current, this is the current-criterion threshold, $V_{T,sat}$ (Chapter 4, Section 8): with $V_{DS}$ at the supply, $V_T$ is the $V_{GS}$ where the current reaches $100\,\mu\mathrm{A}$100μA, i.e. $10\,\mu\mathrm{A}$ per µm of width.
2. Count the decades. The figure’s device has $V_{GS} = 0$ and leaks 100 nA. So from $V_T$ down to 0 the current falls by $100\,\mu\mathrm{A}/100\,\mathrm{nA} = 10^3$103: three decades.
3. Price them in volts. Because the slope is 80 mV per decade, each decade costs 80 mV of $V_{GS}$ (Chapter 4, Section 11), so $V_T = 3 \times 80 = 240\,\mathrm{mV}$240mV.

Check. Run it forward. At $V_{GS} = 0$ the gate is 240 mV below threshold, which at 80 mV per decade is three decades: $100\,\mu\mathrm{A} \times 10^{-3} = 100\,\mathrm{nA}$100nA, the leakage the question gives. ✓

Answer: $V_T = 80\,\mathrm{mV} \times \log_{10}(100\,\mu\mathrm{A}/100\,\mathrm{nA}) = 240\,\mathrm{mV}$240mV.

Remember. A current-defined threshold turns into decade counting: $V_T = S \times$ (decades between the threshold current and the leakage). Always ask which definition of $V_T$ a question uses.

The answer key agrees

FN12-1b: the source raised to 1 V

FN12-1b, p3 (source figure).

FN12-1b, p3 (6 points). If the source voltage is instead set to 1.0 V as shown below, what is the drain current through the device. Please ignore DIBL and body effect.

Hint

The gate is still grounded. What is $V_{GS}$ now?

What it asks. The same device with its source raised to 1.0 V, gate at 0 and drain at 1.8 V. “Ignore DIBL and body effect” decides what stays fixed: the threshold stays at (a)‘s 240 mV, and $V_{DS}$ doesn’t matter, so only $V_{GS}$ changes.

The idea. The same decade count as (a). The new point is that $V_{GS}$ is measured from the gate to the source. The gate hasn’t moved, but the source has risen 1 V above it, so the gate is 1 V further below threshold than in (a). Reading “the gate is grounded, as in (a)” and keeping (a)‘s current is the trap of comparing absolute voltages (How to approach). With DIBL ignored, the subthreshold current depends on $V_{GS}$ alone (Chapter 4, Section 11).

1. Measure from the source. Because the subthreshold current depends on $V_{GS}$VGS​, gate to source, read both terminals: the gate is at 0 and the source at 1.0 V, so $V_{GS} = -1.0\,\mathrm{V}$−1.0V. The drain still sits 0.8 V above the source, which with DIBL ignored changes nothing.
2. Count the decades. Because every 80 mV below $V_{GS} = 0$ is another decade, $1000/80 = 12.5$ decades below the 100 nA of part (a).
3. The current. $I_D = 100\,\mathrm{nA} \times 10^{-12.5} = 10^{-7} \times 3.16\times10^{-13} = 3.16\times10^{-20}\,\mathrm{A}$10−20A.

Check. Count from the threshold instead. $V_{GS} = -1.0\,\mathrm{V}$ is $1.24\,\mathrm{V}$ below $V_T = 240\,\mathrm{mV}$240mV, which is $1240/80 = 15.5$ decades below the 100 µA that defines it: $10^{-4}\,\mathrm{A} \times 10^{-15.5} = 3.16\times10^{-20}\,\mathrm{A}$10−20A. ✓ The same, because (a)‘s three decades plus these 12.5 make 15.5.

Answer: $3.16\times10^{-20}\,\mathrm{A}$10−20A: raising the source by 1 V cuts the leakage by 12.5 decades.

Remember. $V_{GS}$ is gate to source. A source raised above the gate is a reverse gate bias, and every $S$ millivolts of it is one more decade of turn-off. Part (c) uses this.

The answer key agrees

FN12-1c: two stacked devices against one

FN12-1c, p4 (source figure; the “A” is the key’s handwriting).

FN12-1c, p4 (6 points). Stacked devices are often used to control subthreshold leakage. Which of the two circuits below could be expected to have the smaller drain leakage current? Explain. Hint: Consider carefully your answer to part (b).

Hint

Node A is tied to nothing. What sets its voltage, and what does that voltage do to each of the two devices?

What it asks. Which leaks less when off: two 10 µm NFETs in series (i), or one 5 µm NFET (ii)? Explain. The exam’s hint points at (b): a raised source. “Explain” carries the points, and this time the question doesn’t say to ignore DIBL or the body effect.

The idea. First make sure the comparison is fair: by the stack rule, transistors in series drive like one transistor of width $1/\sum(1/W_i)$1/∑(1/Wi​), so two 10 µm devices drive like one 5 µm device (Chapter 7, Section 8). Then find node A. It is tied to nothing, and the two devices are in series, so it settles where they carry the same current. Then read each device’s own $V_{GS}$VGS​, $V_{SB}$ and $V_{DS}$ from that node, and apply the threshold section’s moves to each. Three effects come out: part (b)‘s negative $V_{GS}$ and the body effect on the top device, and the missing DIBL on the bottom one. Naming only part (b)‘s effect is the tempting answer, and on its own, with the other two ignored, it is not enough.

Stack against single device

1. A fair comparison. By the stack rule, two 10 µm devices in series drive like one 5 µm device (Chapter 7, Section 8). So both circuits have the same on-current; the question is their off-current.
2. Circuit (ii). Because leakage is per µm of width, one 5 µm device with $V_{GS} = 0$ and the full 1.8 V across it leaks, by part (a), half of the 10 µm device’s leakage, about 50 nA.
3. Circuit (i): node A rises. Because the same current must flow through both devices, A can’t stay at 0: there the top device would leak like a full 10 µm device while the bottom one, with nothing across it, could carry none of it. So A charges up until the two currents match, to some voltage between 0 and 1.8 V.
4. The top device sees part (b). Its source is at $V_A$ and its gate at 0, so $V_{GS} = -V_A$−VA​: every 80 mV at node A cuts its current tenfold. Its threshold is also raised by the body effect, since its source sits above its grounded body: the case Lecture 5 draws (Chapter 5, Section 1, 02:03–02:56).
5. The bottom device has almost nothing across it. Because only $V_A$ sits on its drain, it has none of the DIBL that lowers the threshold of the 5 µm device, which has 1.8 V on its drain (Chapter 4, Section 12).
6. Conclude. So circuit (i) leaks less: the stack’s current is set by a device with a negative $V_{GS}$VGS​, a body-affected threshold and, at the bottom, no DIBL.

Check. The size of “node A rises”. Each 80 mV at A cuts the top device’s current tenfold, so A needs only a small fraction of the supply to balance the two devices. The fuller model in the note below finds about 21 mV with part (b)‘s assumptions and about 150 mV with an illustrative DIBL added. “Between 0 and 1.8 V” means tens of millivolts, not volts, which is why the small effects of steps 4 and 5 decide the comparison.

Answer: circuit (i), the stack. Node A floats up between 0 and 1.8 V, which turns the top device’s $V_{GS}$ negative (part b), raises its threshold through the body effect, and leaves the bottom device without DIBL; the single 5 µm device has none of these. Both circuits have the same drive when on.

How much less is beyond the course. added The course’s subthreshold model doesn’t say how the current falls when $V_{DS}$ drops to a few $kT/q$kT/q, and that sets where node A settles. A fuller model, kept in this page’s review/decisions.md, shows how much rests on DIBL: with DIBL and the body effect both ignored, as in part (b), node A settles near 21 mV and the stack leaks about as much as the 5 µm device (10% more); with an illustrative DIBL of 100 mV per volt, node A rises to about 150 mV and the stack leaks about 58 times less. Real stacks leak far less, mostly through DIBL and the body effect.

Remember. A stack’s middle node rises until the two currents match. Read each device’s own $V_{GS}$VGS​, $V_{SB}$ and $V_{DS}$ from it, and name all three effects: the top device’s negative $V_{GS}$ and its body effect, and the bottom device’s missing DIBL.

The answer key differs

It answers (i), with the reason “node A will charge to something between 1.8 V and 0 V, dramatically reducing the leakage of the top device”. The conclusion is right; the reason names only part (b)‘s effect, which on its own (with DIBL and the body effect ignored) is not enough. Name all three.

3. The body effect in a shifted-supply inverter

FN10-1, p2 (source figure): in (I) the NFET’s body goes to ground, 2.5 V below its source.

FN10-1, p2 (Fall 2010, 10 points). Joe Engineer decides he wants to design logic circuits that operate between 2.5 V and 5 V (rather than between 0 V and 2.5 V). Consider an inverter in this circuit style shown in (I). How will the rising and falling delays of this inverter compare with the “regular” logic scheme of (II) for the same output loading and input slew times?

Hint

Measure every terminal of each transistor from its own source. Which terminal is not shifted up with the rest?

What it asks. How the rising and falling delays of the shifted inverter (I) compare with those of the ordinary one (II). “For the same output loading and input slew times” removes every other difference: only the transistors’ bias can change the delays.

The idea. This is the threshold section’s $V_{SB}$ term (How to approach). A transistor responds to the voltages between its own terminals, not to their values above ground. Shifting a whole circuit up by 2.5 V changes nothing, unless some terminal isn’t shifted. Here one is: the NFET’s body stays at ground. A source above its body is a reverse bias $V_{SB}$VSB​, which deepens the depletion region under the gate. Then $Q_{bulk} = \sqrt{2\kappa_s\varepsilon_0(2\phi_F + V_{SB})qN_A}$ grows, and so does $V_T$ (Chapter 5, Section 1). A higher threshold at the same $V_{GS}$ leaves less overdrive, and less current. The delay is charge over current (Chapter 5, Section 11), so the edge that device drives gets slower.

Rising and falling edges

1. Measure from each source. Because a transistor feels only the voltages between its own terminals, look at each one relative to its source. Both circuits swing 2.5 V, so every gate-to-source voltage is the same in (I) and (II): 2.5 V when on.
2. Rising output (the PFET pulls up). Because the PFET drives this edge, compare its terminals: in (I) its source is at 5 V and its body (the n well) at 5 V, the same relation as in (II). Same $V_{SG}$VSG​, same threshold, same current: the rising delay is about the same.
3. Falling output (the NFET pulls down). Because the NFET drives this edge, compare its terminals: in (I) its source is at 2.5 V but its body is drawn to ground: $V_{SB} = 2.5\,\mathrm{V}$2.5V. The depletion region under the gate must hold $2\phi_F + V_{SB}$VSB​, so $Q_{bulk}$ and $V_T$ rise (Chapter 5, Section 1).
4. Less current, a slower edge. Because the NFET has the same $V_{GS}$ and a higher $V_T$VT​, its overdrive is smaller, its current lower, and the falling delay longer.
5. How much, in Chapter 5’s device added ($V_{T0} = 0.5\,\mathrm{V}$VT0​=0.5V). At $V_{SB} = 2.5\,\mathrm{V}$ the bulk charge doubles and $V_T = 0.760\,\mathrm{V}$0.760V. The overdrive falls from 2.0 to 1.74 V. A velocity-saturated current falls in proportion, so the falling delay grows by $2.0/1.74 = 1.15$ (15%); a square-law current would make it 1.32 (32%).

Check. Remove the cause. Tie the NFET’s body to its own source at 2.5 V instead of ground: then $V_{SB} = 0$0, every terminal of both devices is shifted by the same 2.5 V, and (I) behaves exactly like (II) on both edges. Only the body tie changed, so the body tie causes the slower fall.

Answer: the rising delay is about the same (the PFET sees the same overdrive and the same body bias); the falling delay is longer in (I), because its NFET’s body is 2.5 V below its source, and the body effect raises its threshold and cuts its overdrive.

A smaller effect the other way added. The NFET’s drain junction in (I) is reverse-biased by 2.5 to 5 V instead of 0 to 2.5 V, so its junction capacitance is smaller (Chapter 5, Section 5): in Chapter 5’s junction, 0.486 down to 0.371 fF/µm² instead of 0.905 down to 0.486. That speeds both edges a little; it does not undo the body effect on the falling edge. The question does not need it.

Remember. Never compare absolute voltages: read each device’s $V_{GS}$ and $V_{SB}$ from its own source. A body below an NFET’s source raises its $V_T$ and slows the edge that NFET drives.

The answer key agrees

It gives the same: rising about the same, falling slower because the NFET is body affected ($V_{SB} = 2.5\,\mathrm{V}$VSB​=2.5V). It does not mention the smaller drain-capacitance effect in the other direction.

Lecture05 @ 08:09The body effect: the threshold with V_SB, and the stack where it happens (centre).

Set $V_{SB}$ to 2.5 V to see the falling edge’s threshold in (I):

source-to-body bias V_SB

2.50 V

body doping N_A

10¹⁷ cm⁻³

oxide thickness t_ox

5.4 nm

2φ_F

0.833 V

Q_bulk: at V_SB = 0 → now

1.66 → 3.33 ×10⁻⁷ C/cm² (×2.00)

depletion depth under the gate

104 → 208 nm

V_T: at V_SB = 0 → now

0.500 → 0.760 V (+260 mV)

overdrive at V_GS = 1.5 V: no body effect → now

1.00 V → 0.74 V

The threshold rises as a square root of 2φ_F + V_SB: steeply at first, then more slowly. Heavier body doping and a thicker oxide both make the effect larger, because Q_bulk/C_ox is the term that grows. The flat-band voltage is held at −0.59 V, chosen so the default device has V_T = 0.5 V at V_SB = 0.

4. Delay as charge over current: FO1, FO4 and the supply

Lecture05 @ 60:10FO1 = 3τ_tr(1 + 1/η) (bottom) and FO4 = ((4C_g + C_d)/(C_g + C_d)) FO1 (right).

FN12-2: why FO1 is more than a quarter of FO4

FN12-2, p5 (the key’s sketch).

FN12-2, p5 (Fall 2012, 6 points). In general one finds that the fanout-of-one (FO1) delay is greater than one-fourth the fanout-of-four (FO4) delay. Why is this?

Hint

When the fanout goes from one to four, which capacitances on the output node grow, and which stay the same?

What it asks. Why FO1 is more than a quarter of FO4: why four loads don’t take four times as long. “Why” asks for the reason, a count of the capacitance on the output node.

The idea. This is the charge-over-current move of M3’s device short answers, and the same counting as MT21-2. What this question adds is that it asks for the reason instead of the formula, with the lecture’s 2W/W inverter. The output node at $V_{DD}$ holds the charge $V_{DD}C_{node}$VDD​Cnode​, and the switching transistor, saturated, removes it at $I_{DSAT}$IDSAT​, so $t \approx V_{DD}C_{node}/I_{DSAT}$ (Chapter 5, Section 11). The driver is the same in both cases, so the current is too, and the delay is in proportion to the capacitance on the node. The tempting answer, FO4 = 4 × FO1, counts four drivers’ drains where there is one.

1. Charge over current. A delay is the charge to move over the current: $V_{DD}\times(\text{node capacitance})/I_{DSAT}$ (Chapter 5, Section 11). Because the driver, and so the current, is the same in both cases, only the capacitance differs.
2. Count the node. Because the node is the driver’s output, it carries the loads’ gates and the driver’s own drains. FO1’s node carries one load’s gate capacitance and the driver’s drain capacitance: $C_G + C_D$CD​. FO4’s carries four loads’ gates but still one driver’s drain: $4C_G + C_D$ (Chapter 5, Section 13).
3. Divide. Because the current is the same, the two delays are in the ratio of their node capacitances: $\mathrm{FO4} = \dfrac{4C_G + C_D}{C_G + C_D}\,\mathrm{FO1} = \dfrac{1 + 4\eta}{1 + \eta}\,\mathrm{FO1}$ with $\eta = C_G/C_D$CG​/CD​, which is less than $4\,\mathrm{FO1}$ whenever $C_D > 0$0.
4. For scale, at η = 2. The lecture’s inverter is 2W/W, and its FO1 is $3\tau_{tr}(1 + 1/\eta)$1/η), where $\tau_{tr} = L/v_{sat}$ is the transit time and the 3 counts the 2W PFET’s capacitance (Chapter 5, Section 12). So $\mathrm{FO1} = 4.5\tau_{tr}$ and $\mathrm{FO4} = 3\tau_{tr}(4 + 1/\eta) = 13.5\tau_{tr}$13.5τtr​, so $\mathrm{FO4}/4 = 3.375\tau_{tr}$ and $\mathrm{FO1}$ is $4/3$ of it. With $\tau_{tr} = 2.5\,\mathrm{ps}$2.5ps: 11.25 ps against 8.44 ps.

Check. The limits of the ratio $(1 + 4\eta)/(1 + \eta)$η). With no drain capacitance ($\eta \to \infty$η→∞) it is 4, and FO1 is exactly a quarter of FO4. With more drain capacitance it falls: 3 at $\eta = 2$2, 2.5 at $\eta = 1$1. The more of the node the driver’s own drains make up, the less the fanout matters.

Answer: the driver’s own drain capacitance is in both loads, but it does not grow with the fan-out. FO4 has four times the gate load and the same drain load, so a quarter of FO4 carries only a quarter of the drain capacitance, while FO1 carries all of it. Only with no drain capacitance ($\eta \to \infty$η→∞) would FO1 equal FO4/4.

Remember. Count the loads’ gates times the fanout, and the driver’s drains once. In Chapter 7’s RC model, which ignores drain capacitance, FO4 is exactly $4\tau_{inv}$ (M2, Section 2 explains the two models).

The answer key agrees

FN10-6a: supply sensitivity of a velocity-saturated inverter

FN10-6, p9 (Fall 2010). One of the issues in using inverters as delay elements (or in distributing clocks) is that they have a high sensitivity to power-supply variations. Let’s try to calculate this (back-of-the-envelope).

(a) (10 points) To estimate the delay, assume that the inverter is driven by a step input, the discharging (or charging) transistor is always saturated (with full overdrive), and the device is completely velocity saturated. Variations in the supply voltage affect both the logic high level of the inverter input as well as the supply of the inverter. If $V_{DD} = 2.5\,\mathrm{V}$ and $|V_{Tn}| = |V_{Tp}| = 0.5\,\mathrm{V}$0.5V, find the power supply sensitivity $\dfrac{V_{DD}}{t_{delay}}\dfrac{\partial t_{delay}}{\partial V_{DD}}$tdelay​VDD​​∂VDD​∂tdelay​​.

Hint

Write the delay as charge over current. Which of its factors contain $V_{DD}$VDD​?

What it asks. By what percentage the delay changes when the supply changes by 1%: that is what $\dfrac{V_{DD}}{t}\dfrac{\partial t}{\partial V_{DD}}$ measures. “Affect both the logic high level of the inverter input as well as the supply” says that $V_{DD}$ appears twice: in the charge on the node and in the overdrive. “Completely velocity saturated” picks the current law.

The idea. The delay is charge over current, the move of M3’s device short answers: the node holds $CV_{DD}$CVDD​, and the step input gives the switching transistor the full overdrive $V_{DD} - V_T$VT​. A fully velocity-saturated current is in proportion to the overdrive, $I_{DSAT} = C_{ox}Wv_{sat}(V_{DD} - V_T)$ (Chapter 4, Section 7). What this question adds is the logarithmic derivative added: $\dfrac{V_{DD}}{t}\dfrac{\partial t}{\partial V_{DD}} = \dfrac{\partial\ln t}{\partial\ln V_{DD}}$∂lnVDD​∂lnt​, the fractional change in $t$ per fractional change in $V_{DD}$VDD​. Taking the logarithm turns the delay’s product and quotient into a sum and a difference, so each factor contributes on its own. In words: the charge grows in proportion to $V_{DD}$VDD​, which lengthens the delay, while the current grows in proportion to the overdrive, which shortens it. The overdrive changes by a larger fraction than $V_{DD}$VDD​, because $V_T$ doesn’t move.

Velocity-saturated

1. Charge over current (Chapter 5, Section 11): $t \propto CV_{DD}/I_{DSAT}$CVDD​/IDSAT​. Because the step input reaches $V_{DD}$VDD​, the overdrive is $V_{DD} - V_T$VT​.

2. The current law. Because the device is fully velocity-saturated (Chapter 4, Section 7), $I_{DSAT} = C_{ox}Wv_{sat}(V_{DD} - V_T) = k(V_{DD} - V_T)$VT​). So $t = \dfrac{CV_{DD}}{k(V_{DD} - V_T)}$k(VDD​−VT​)CVDD​​.

3. Take logarithms added, because the sensitivity is the derivative of $\ln t$ with respect to $\ln V_{DD}$lnVDD​: $\ln t = \ln V_{DD} - \ln(V_{DD} - V_T) + \text{const}$const, so

   $$\frac{V_{DD}}{t}\frac{\partial t}{\partial V_{DD}} = 1 - \frac{V_{DD}}{V_{DD} - V_T}$$ $$= -\frac{V_T}{V_{DD} - V_T} .$$

4. The numbers. $V_{DD} = 2.5\,\mathrm{V}$2.5V, $V_T = 0.5\,\mathrm{V}$0.5V: $-0.5/2.0 = -0.25$−0.25.

5. Read it. A 1% lower supply makes the delay 0.25% longer. The charge to move falls with $V_{DD}$VDD​, and the current falls slightly faster, by $V_{DD}/(V_{DD} - V_T)$VT​).

Check. Compute two delays directly. At 2.5 V, $t \propto 2.5/2.0 = 1.25$1.25; at 1% more supply, 2.525 V, $t \propto 2.525/2.025 = 1.2469$1.2469. That is 0.25% shorter for 1% more supply: a sensitivity of −0.25. ✓

Answer: $-V_T/(V_{DD} - V_T) = -0.25$−0.25.

Remember. Supply sensitivity is the exponent of $V_{DD}$ in the charge (1) minus the current’s exponent of the overdrive times $V_{DD}/(V_{DD} - V_T)$VT​). The current feels the overdrive, not the supply, so the threshold is what makes a delay supply-sensitive.

The answer key agrees

FN10-6b: the same with a square-law device

FN10-6b, p9 (10 points). If the device were “square-law” (i. e., not velocity saturated), what would the power-supply sensitivity be?

Hint

Only the current law changes. How does a square-law current respond to a 1% change in the overdrive?

What it asks. The same sensitivity as (a), for a device whose saturated current follows the square law instead.

The idea. Everything in (a) stays except the current law. The long-channel saturated current goes as the square of the overdrive, $I_{DSAT} = k'(V_{DD} - V_T)^2$VT​)2; it holds when the carriers are not velocity saturated (Chapter 4, Section 4). In the logarithm the square becomes a factor 2, so the current’s term in (a)‘s sensitivity counts twice added.

Square law

1. The current law. Because the device is square-law (Chapter 4, Section 4), $I_{DSAT} = k'(V_{DD} - V_T)^2$VT​)2, so $t = \dfrac{CV_{DD}}{k'(V_{DD} - V_T)^2}$k′(VDD​−VT​)2CVDD​​.

2. Take logarithms, as in (a), because the sensitivity is $\partial\ln t/\partial\ln V_{DD}$∂lnt/∂lnVDD​: $\ln t = \ln V_{DD} - 2\ln(V_{DD} - V_T) + \text{const}$const, so

   $$\frac{V_{DD}}{t}\frac{\partial t}{\partial V_{DD}} = 1 - \frac{2V_{DD}}{V_{DD} - V_T}$$ $$= -\frac{V_{DD} + V_T}{V_{DD} - V_T} .$$

3. The numbers. $-(2.5 + 0.5)/(2.5 - 0.5) = -1.5$−1.5.

4. Compare with (a). It is six times the velocity-saturated value, because the current now falls as the square of the overdrive.

Check. Compute two delays directly again. At 2.5 V, $t \propto 2.5/2.0^2 = 0.625$0.625; at 2.525 V, $t \propto 2.525/2.025^2 = 0.6158$0.6158. That is 1.5% shorter for 1% more supply. ✓

Answer: $-(V_{DD} + V_T)/(V_{DD} - V_T) = -1.5$−1.5.

Why velocity saturation helps here added. With $V_T \to 0$ a velocity-saturated delay doesn’t depend on the supply at all ($CV_{DD}/kV_{DD}$CVDD​/kVDD​), while a square-law delay still goes as $1/V_{DD}$1/VDD​, sensitivity $-1$−1. The sensitivity is a slope: for a large droop, compute the two delays directly. From 2.5 V to 2.0 V (20% lower) the velocity-saturated delay grows by 6.7% (the slope alone says 5%) and the square-law delay by 42% (the slope says 30%).

Remember. The current’s exponent of the overdrive multiplies its share of the sensitivity: 1 for velocity saturation, 2 for the square law. A velocity-saturated device is much less sensitive to its supply.

The answer key agrees

Its last line, which the transcription reads as “−0.25)6”, is $-(0.25)\times6$6, that is $\frac{1}{1 - 5}\times(1 + 5)$5).

nominal supply V_DD

2.50 V

threshold V_T

0.50 V

supply droop ΔV

0.50 V

sensitivity, velocity-saturated

−0.25

sensitivity, square law

−1.50

velocity-saturated at 2.00 V

+6.7% (slope +5.0%)

square law at 2.00 V

+42.2% (slope +30.0%)

Delay ∝ V_DD/(V_DD − V_T)^a, with a = 1 for the velocity-saturated current and a = 2 for the square law; the sensitivity is (V_DD/t)(∂t/∂V_DD) = 1 − aV_DD/(V_DD − V_T). The grey lines mark the nominal supply and the lowered one, V_DD − ΔV. Both curves blow up as V_DD nears V_T. Slide V_T to 0.10 V: the velocity-saturated delay barely moves with the supply, while the square law still falls as 1/V_DD. The two lower readouts give the delay change at the lowered supply, exactly and from the sensitivity alone (the slope); large droops bend away from the slope.

What to notice.

• At the exam’s values the two readouts are −0.25 and −1.50.
• Raise $V_T$ toward $V_{DD}$VDD​: both sensitivities grow without bound, because the overdrive is what the supply really moves.
• Chapter 4’s full velocity-saturation model lies between the two curves, closer to the linear one for short channels (compare H1’s doubling test).

Check yourself A velocity-saturated inverter runs at V_DD = 1.0 V with V_T = 0.3 V. What is its supply sensitivity, and why is it larger than FN10-6a's?

$-0.3/(1.0 - 0.3) = -0.43$−0.43. The threshold is a larger fraction of the supply, so a given change in $V_{DD}$ moves the overdrive by a larger fraction. Low-voltage designs are more supply-sensitive.

Formulas this page uses

• Threshold (the approach): $V_T = V_{FB} + 2\phi_F + Q_{bulk}/C_{ox}$Qbulk​/Cox​, $Q_{bulk} = \sqrt{2\kappa_s\varepsilon_0(2\phi_F + V_{SB})qN_A}$2κs​ε0​(2ϕF​+VSB​)qNA​​, $C_{ox} = \kappa_{ox}\varepsilon_0/t_{ox}$ (Chapter 3, Section 8; Chapter 5, Section 1). Less bulk charge for the gate (DIBL, roll-off) or a thinner oxide: lower $V_T$VT​. More doping (halos) or $V_{SB} > 0$0: higher $V_T$VT​.
• Subthreshold: $I = I(V_T)\times10^{(V_{GS} - V_T)/S}$10(VGS​−VT​)/S; a current-defined $V_T$ is $S\log_{10}(I_{def}/I_{off})$ (Chapter 4, Sections 8 and 11).
• FO1 and FO4: $\mathrm{FO1} = 3\tau_{tr}(1 + 1/\eta)$1/η), $\mathrm{FO4} = \frac{1 + 4\eta}{1 + \eta}\mathrm{FO1}$ (Chapter 5, Sections 12–13).
• Supply sensitivity of $t \propto V_{DD}/(V_{DD} - V_T)^a$VT​)a: $1 - aV_{DD}/(V_{DD} - V_T)$VT​); $-V_T/(V_{DD} - V_T)$ velocity-saturated ($a = 1$a=1), $-(V_{DD} + V_T)/(V_{DD} - V_T)$ square law ($a = 2$a=2).

What this means for the midterm

Device short answers (MT17-1b–c, MT21-2; M3, Sections 8–9).

• Counting decades (FN12-1a–b) is the move of MT17-1c, of the leakage step in MT24-2b and MT23-1b, and of HW1-3. Trap: $V_{GS}$ is gate to source; a raised source counts. About 2 minutes.
• Body connections (FN10-1) are MT17-1b’s question from the other side: a body below an NFET’s source is a reverse bias that raises $V_T$VT​; a body on the wrong side of a junction forward-biases it. Trap: comparing absolute voltages instead of each device’s $V_{GS}$ and $V_{SB}$VSB​. About 3 minutes.
• FO1 and FO4 (FN12-2) is MT21-2: count the gates of the loads and the drains of the driver only. Trap: FO4 = 4 FO1. About 3 minutes.

Explanation questions (FN19-2, FN17-1a, 1c, FN12-1c). The midterms ask few of these, but the instructions give partial credit for explanations. Answer from the threshold formula, with the approach’s four moves. Two or three sentences each.

Not asked by any past midterm. The supply sensitivity (FN10-6) and the short-channel effects (FN19-2, FN17-1a) appear only in the finals. They test the same two I–V models as M2’s chart.

What the keys get wrong

The 2019 final has no key. Every other part agrees with its key after re-solving; these notes are recorded in this page’s review/decisions.md.

Part	The key	Here
FN17-1c	thinner oxide, lower $V_T$VT​, because “the gate has full control of the bulk charge”	direction right; the reason is the oxide term $Q_{bulk}/C_{ox}$Qbulk​/Cox​, which shrinks with $t_{ox}$ while $Q_{bulk}$ stays
FN12-1c	(i), because node A rises and cuts the top device’s leakage	(i) is right; the raised node alone (part b’s assumptions) is not enough: the body effect and the bottom device’s missing DIBL carry the difference
FN10-1	rising the same, falling slower (body effect)	agrees; it leaves out the smaller drain-capacitance effect in the other direction

FN17-1a, FN12-1a–b, FN12-2 and FN10-6a–b agree with their keys.