M1. What to expect on the midterm

This page starts the midterm kit. It counts where the points went on the four past midterms (Fall 2017, 2021, 2023 and 2024), weights the two recent ones most, adds what the Fall 2026 class has said about the exam, and turns that into a study plan. The other pages solve the questions: M3 (inverters, energy and devices), M4 (path sizing), M5 (pass transistors and layout), M6 (dynamic and domino logic), M7 (a practice midterm) and M2 (the formula sheet).

Every point total and percentage below was counted from the printed point values in the four exams and is rechecked by this page’s tests. The guess in Section 5 is an extrapolation from those counts; nobody has told us what is on the exam.

After this page you can:

1. say what the exam looks like: five questions, 75 minutes, closed book, explanations required;
2. name the question families that carry the points, and how much each has carried;
3. plan your study time by expected points, with the chapter sections to review for each family;
4. pace the exam: about 30 seconds a point on a 150-point exam, 22.5 seconds on a 200-point one.

At a glance.

• When and how much. The Fall 2026 syllabus dates the midterm October 21, 2026, and weights it at 25% of the course grade.
• Scope. Chapters 0–12, ending with delayed-reset clocks (Chapter 12, Section 7). Latches, flip-flops and clocking are not on it.
• Format. Five questions in 75 minutes, worth 150 points (200 in 2024). Closed book, closed notes. No credit for an answer without an explanation.
• What always comes. An inverter-chain question on energy, leakage and delay (23–25% of every exam).
• What came in both recent exams. A pass-transistor circuit (about 23%), a dynamic or domino gate (21–25%) and a stick layout (7–8%). The fifth question was static path sizing in 2023 and noise margins in 2024.

1. The format

All four exams have the same shape. Each question has lettered parts with printed point values, mostly 8–15 points a part.

	MT17	MT21	MT23	MT24
Date	November 1, 2017	October 21, 2021	October 19, 2023	October 17, 2024
Time	75 min	75 min	75 min	75 min
Points	150	150	150	200
Time per point	30 s	30 s	30 s	22.5 s
Questions	5	5	5	5
Pages	13 (the key; no page numbers)	9	14	12

The printed instructions. Every exam says:

• “This exam is closed book, closed notes.”
• “Partial credit will be given. If you don’t have time to work a problem completely, explain how you would solve it and try to set up the problem. No credit will be given for answers without explanation.”
• “Put all answers in the space provided in the exam booklet.” From 2021 on, you may use the back of a page if you draw arrows to the answer.

From 2021 on, the instructions add two lines that matter for pacing:

• “Most of the questions require very short answers with very little calculation. Pace yourself so that you get a chance to work all of the problems.”
• 2023 adds “Easier problems may not be the first”, and 2024 “The easiest problems may not be the first one.”

How the 2024 key was graded. A handwritten note on its cover reads “~30% partial credit for incorrect but reasonable attempts per grader discretion.” Its rubric gives most of each part’s points to the setup: in MT24-5b, 13 of the 15 points go to the electrical efforts, the logical efforts and the delay formula, and 2 to the final number.

2. Where the points go

By question family

Each part is counted once, in the family of the page that solves it. Percentages are of that exam’s total.

Family	MT17	MT21	MT23	MT24	Solved on	Chapters
Inverter chain: energy, leakage, delay, energy × delay	38 (25%) Q4	35 (23%) Q4	34 (23%) Q1	50 (25%) Q2	M3 §1–§4	4, 6, 7
Pass-transistor logic	—	55 (37%) Q1, Q3	34 (23%) Q2	45 (23%) Q3	M5 §1–§4	7, 10, 11
Dynamic and domino logic	8 (5%) Q3c	—	32 (21%) Q3	50 (25%) Q5	M6	11, 12, 8
Static path sizing with a branch	40 (27%) Q5	35 (23%) Q5	40 (27%) Q5	—	M4 §1–§3	7, 8
Noise margins and the transfer curve	24 (16%) Q1a, Q2	—	—	40 (20%) Q1	M3 §5, §6, §9	6
Stick layout to schematic	—	—	10 (7%) Q4	15 (8%) Q4	M5 §5, §6	5, 9, 10
Device short answers	16 (11%) Q1b–c	25 (17%) Q2	—	—	M3 §8, §9	3, 4, 5
Single-gate delays in units of the FO1 delay	24 (16%) Q3a, b, d	—	—	—	M3 §7	7, 8
Total	150	150	150	200

Two skills cut across the families:

• Sizing a path by gains ($\tau_{inv}\sum g_ih_i$τinv​∑gi​hi​, equal gains, a branch). It is the whole of every static path-sizing question and 35 of MT24’s 50 dynamic-logic points (MT24-5b–c). Counted that way, it is worth 35–40 points on every exam: 27%, 23%, 27% and 18%.
• The exam’s device convention. The questions switch between “the NFET and PFET have the same strength” ($\tau_{inv} = 2R_nC_g$τinv​=2Rn​Cg​, W/W inverters) and $R_p = 2R_n$ ($\tau_{inv} = 3R_nC_g$τinv​=3Rn​Cg​, 2W/W inverters), sometimes within one exam. Equal strengths appear in MT17-3, MT21-2, MT21-4c (second half), MT21-5, MT23-5, MT24-2 and MT24-5; MT23-1 and MT23-3 use $R_p = 2R_n$2Rn​.

Question by question

The order changes from year to year, which is why 2023 and 2024 warn that the easiest problem may not come first.

	Q1	Q2	Q3	Q4	Q5
MT24 (200)	noise margins, 40	inverter chain, 50	pass-transistor carry, 45	stick layout, 15	dynamic full adder, 50
MT23 (150)	inverter chain, 34	pass-transistor adder, 34	domino XOR, 32	stick layout, 10	path sizing, 40
MT21 (150)	pass-transistor multiplexer, 30	FO4 from the transit time, 25	six-transistor XOR, 25	inverter chain, 35	path sizing, 35
MT17 (150)	short answers, 24	three transfer curves, 16	gate delays, 32	inverter chain, 38	path sizing, 40

3. What the two recent exams show

• The inverter-chain question is nearly fixed. MT23-1 and MT24-2 are the same problem: $N$ inverters with 4 fF side loads, $C_g = 1$ fF/µm, $R_n = 1$ kΩ·µm, $V_{DD} = 1.2$ V, a 50% duty-cycle input, and 10 µA/µm at $|V_T| = 200$ mV with 90 mV/decade. Both ask for the supply energy per cycle, the leakage energy, the leakage share when $T_{cycle}$ equals the chain delay, and the $W$ that minimizes energy × delay. MT23 uses 2W/W inverters with $R_p = 2R_n$2Rn​; MT24 uses W/W with equal strengths and adds “minimize the delay” (no finite answer). The older versions (MT17-4, MT21-4) ask for the energy of one transition, not a cycle, and for a different optimum ($C_x = 3Wk_{gate}$Cx​=3Wkgate​; a PFET ratio of $\sqrt2$2​). Re-solved in M3, Sections 1–4; the leakage is 59.9 nA/µm.
• A pass-transistor circuit has come every year since 2021, and it asks the same four things: is it static (MT24-3a’s rubric gives full points for “not static, because the half latches make it ratioed”); what each output computes (a carry, a sum, a multiplexer); the worst output levels ($V_{DD} - V_{Tn}$VDD​−VTn​, $V_{DD} - 2V_{Tn}$2VTn​, $2|V_{Tp}|$2∣VTp​∣) or what the cross-coupled PFETs restore; and a complementary static CMOS equivalent (MT21-1c, MT24-3d). Both recent circuits are full-adder pieces. See M5, Sections 1–4.
• Dynamic logic has grown into a full question. MT17 had one 8-point part. MT23-3 is a domino XOR: its function, a delay from $R$ and $C$C, the noise margins of the skewed output inverter, and a half latch. MT24-5 is a dynamic full adder: its function, then a delay and a resizing by dynamic logical effort with a branch (50 points). In both, the first stage is a p-type dynamic gate, so NP domino (Chapter 12, Sections 5–6) is examined. They are solved on page M6.
• A stick layout came in both (MT23-4, MT24-4): draw the schematic and name the function. It is worth 7–8% and takes about five minutes (M5, Sections 5–6).
• Static path sizing alternates with noise margins. MT17-5, MT21-5 and MT23-5 are the same template: the gains as drawn, equal-gain sizing back from the load, a side load, then retuning (M4). MT24 had no static path; it put the sizing into the dynamic adder and spent 40 points on a noise-margin concept question instead (M3, Section 5).
• Standalone device physics has gone since 2021. What remains of Chapters 3–5 is the subthreshold leakage inside the chain question. The Fall 2026 lecturer still calls a forward-biased junction a classic exam problem (Section 4).
• The technology numbers repeat. $C_g = 1$ fF/µm (2 fF/µm in MT17 and MT21-4), $R_n = 1$ kΩ·µm (with $R_p$ 1 or 2 kΩ·µm), $\tau_{inv} = 50$ ps (25 or 100 ps in the older exams), $C_{load} = 1$ pF, a 1 µm minimum device, $V_{DD} = 1.2$ V.

4. Signals from the Fall 2026 class

• The syllabus dates the midterm October 21, 2026, and weights it at 25% of the grade (problem sets 10%, the design project 25%, the final 40%). It lists the midterm after “Latches and clocking”, but the lecturer drew the line earlier (next point).
• The scope. At 34:47 of Fall 2026 Lecture 11 (October 15), right after delayed-reset domino and before clocking and latches, the lecturer said: “herein ends the material that will be covered on midterm”. That is the same boundary as the end of Chapter 12 (historical Lecture 12 at 23:15).
• Dynamic logic took up most of two lectures. Fall 2026 Lecture 10 covered half latches, charge sharing, supply noise and NP (zipper) domino. Lecture 11 covered pass-gate sizing, the logical effort of a dynamic stage, the skewed domino inverter and its noise margin (MT23-3c’s question), and delayed reset.
• A “classic exam problem”. In Fall 2026 Lecture 4 (30:09) the lecturer called a circuit in which one of the pn junctions is forward biased, where you are asked what current flows, “a classic exam problem that I often give”. MT17-1b is that problem (M3, Section 9); neither recent midterm asked it.
• The October 16 recitation. The lecturer asked whether the class had started on “the back exams” (08:37). The session covered pass-transistor sizing, branching effort, half-latch strength, the effort of a skewed dynamic path, and a student’s question on sizing the six-transistor XOR (33:45). A student raised a past pass-transistor question whose key says both “static” and “not static” (40:02); that is MT24-3a. The lecturer said he did not write the solutions, and that the half latch makes the circuit ratioed, so “not static” is the right answer (40:56–41:47).

5. A guess at the Fall 2026 midterm

This is a guess, not information. It assumes the pattern of MT23 and MT24 holds. The lecturer can change any question, and the exam may hold a topic that no past midterm asked.

The “expected share” is the mean of the family’s share in MT23 and MT24. The minutes are that share of 75 minutes.

Slot	How likely	Basis	Expected share	Minutes
An inverter chain: energy per cycle, leakage, the leakage share, the best $W$W, with a new twist (the sizing, the side load, the slope or the temperature)	almost certain	all four exams, 23–25%	23.8%	17.9
A dynamic or domino gate: function, delay and sizing by logical effort with a branch, and a half-latch, noise or charge-sharing part	very likely	MT23, MT24 (21–25%); two Fall 2026 lectures	23.2%	17.4
A pass-transistor circuit: static?, function, levels, what restores them, a static CMOS equivalent	very likely	MT21, MT23, MT24 (23–37%)	22.6%	16.9
Either a static path to size and retune around a branch, or a noise-margin concept question	one of the two, likely	path sizing: MT17, MT21, MT23 (23–27%); noise margins: MT17, MT24 (16–20%)	13.3% + 10.0%	10.0 + 7.5
A stick layout to read	likely	MT23, MT24 (7–8%)	7.1%	5.3
A short device item: a forward-biased junction, or FO4 from the transit time	possible	MT17, MT21; Fall 2026 Lecture 4	—	—

Over all four exams, without the extra weight on the recent two, the order changes: chain 24.1%, pass transistors 20.5%, static path sizing 19.2%, dynamic logic 12.9%, noise margins 9.0%, device short answers 6.8%, single-gate delays 4.0% and stick layouts 3.5%.

6. A study plan

Ordered by expected points

Work down this list. For each family, solve the past questions closed-book first, then read the solution page, then fill the gaps from the chapter sections named. Step 4’s skill, sizing a path by gains, also carries most of MT24’s dynamic question, so don’t skip it because its own share is smaller.

1. Inverter chain (about 24%; about 18 minutes on the exam).
   • Practise: M3 Section 1 (MT24-2) and Section 2 (MT23-1), then Sections 3–4 for the per-transition and PFET-ratio variants.
   • Review: Chapter 6, Section 6 (energy per transition and per cycle), Chapter 4, Section 11 (leakage by decades), Chapter 7, Sections 1 and 7 (delay as $(R/W)C$(R/W)C, $\tau_{inv}$τinv​).
2. Dynamic and domino logic (about 23%; about 17 minutes).
   • Practise: page M6 (MT24-5, MT23-3, MT17-3c).
   • Review: Chapter 11, Sections 4–9 (precharge and evaluate, the race, domino, the skewed inverter, the half latch and its size) and Section 10 (charge sharing); Chapter 12, Sections 2–3 (a dynamic stage’s logical effort, sizing), Sections 5–6 (NP domino, p-type stages) and Section 7 (delayed reset).
3. Pass-transistor logic (about 23%; about 17 minutes).
   • Practise: M5 Sections 1–4 (MT24-3, MT23-2, MT21-1, MT21-3).
   • Review: Chapter 10, Sections 4–7 (tracing a network, the degraded high, the half latch, one-hot multiplexers), Section 9 (static or ratioed) and Chapter 7, Section 4 (the static CMOS equivalent).
4. Static path sizing with a branch (about 13% alone; 18–27% with the dynamic sizing; about 10 minutes).
   • Practise: M4 Section 1 (MT23-5), then Section 3 and Section 2, and the retuning widget.
   • Review: Chapter 8, Sections 1–3 (gains, path effort, equal gains), Section 6 (sizing back from the load) and Sections 8–9 (branching and retuning); Chapter 7, Section 8 (stacks and $g$g).
5. Noise margins (about 10%; about 7.5 minutes).
   • Practise: M3 Sections 5–6 (MT24-1, MT17-2) and MT17-1a in Section 9.
   • Review: Chapter 6, Sections 4–5, and Chapter 11, Section 7 for the skewed inverter’s margins.
6. Stick layout (about 7%; about 5 minutes).
   • Practise: M5 Sections 5–6.
   • Review: Chapter 9, Section 10 and Chapter 5, Section 6.
7. Short device items (not in the recent two; signalled in class).
   • Practise: M3 Sections 8–9 (MT21-2, MT17-1b–c).
   • Review: Chapter 5, Section 8 (wells), Sections 12–13 (FO1 and FO4).

Then memorize the formula sheet (page M2), because the exam is closed book, and take the practice midterm (page M7) in 75 minutes with a timer.

If you are short on time

1. Read the conventions box at the top of M3 and the “Patterns” boxes on M3, M4, M5 and M6.
2. Redo MT24-2 and MT23-1 (the chain) without looking. They are the most predictable points on the exam.
3. Redo MT24-3a–b and MT23-2a–b (static?, function) and one stick layout.
4. Read the formula sheet (page M2).

7. Exam technique from the exams’ own instructions

• Explain every answer. “No credit will be given for answers without explanation.” One sentence of reasoning is enough on the conceptual parts: “Most of the questions require very short answers with very little calculation.”
• Set up what you cannot finish. “If you don’t have time to work a problem completely, explain how you would solve it and try to set up the problem.” The 2024 key gives about 30% for a reasonable wrong attempt, and its rubric pays mostly for the setup (Section 1).
• Read all five questions first. “Easier problems may not be the first.” In MT24, the stick layout (Q4, 15 points) was the quickest, and the first question was a 40-point concept question.
• Pace by points. 75 minutes for 150 points is 30 seconds a point: a 10-point part is 5 minutes and a 40-point question 20 minutes. For 200 points it is 22.5 seconds a point: a 10-point part is 3.75 minutes and a 50-point question 18.75 minutes. Leave a part when it reaches its time, and come back.
• State your convention. The keys accept a stated choice: MT24-2c’s key took answers with and without the 0.69 factor, MT24-3b accepted “other logical equivalents”, and MT24-3d says “many possible answers”. Say which strength convention ($R_p = R_n$Rp​= or $2R_n$2Rn​), which delay model and which energy (per transition or per cycle) you use.
• Keep the answer where the grader looks. “Put all answers in the space provided”; if you continue on the back of a page, draw an arrow.

8. Where the keys go wrong

Two of the keys (MT21, MT23) are signed by teaching assistants, and the Fall 2026 lecturer said in the recitation that he did not write the solutions (40:56). Re-solving the parts found errors in all four. Never copy a key’s number. The solution pages list them in full; the MT23-3 and MT24-5 errors were found while writing Chapters 11 and 12, and page M6 re-solves those questions.

Exam	Parts where the key is wrong or incomplete	Re-solved on
MT24	1c–d (the directions of $V_{OH}$ and $V_{OL}$ depend on the model), 3a (says static; its own rubric says not static), 5a–c (a clock label, the last stage’s logical effort, a resizing with $H$ and $G$ held fixed)	M3, M5, M6
MT23	1b–c (pA for nA; one transition for a cycle), 2c (the input example), 3b–c (ns for ps, a missing series device; $NM_H$ for $NM_L$NML​), 5b–d (ns for ps, the side load on the wrong node, a retuning that gains nothing)	M3, M5, M4, M6
MT21	1a–c (“only one” for exactly one, the cut-off condition, $S_2$ for $S_3$S3​), 5a–b (no delay given; an algebra slip in the calculus)	M5, M4
MT17	3a (6.75 for 6.25), 5a–b (a stage gain, $F = 532$ for 533.3), 5d (the delay does not go back to 1.92 ns)	M3, M4