FS2. Final practice: clock generation, pulsed flip-flops and storage cells

This page practises the three kinds of clocking and storage question the past finals ask outside plain latch timing (which is the companion page FS1’s, “flip-flop and latch timing”). Clock generation: a few gates and delay blocks make the clocks a latch needs, and you sketch what comes out (FN12-7a). Pulsed flip-flops: a clock chopper turns each clock edge into a short pulse, the pulse’s width is capped by hold, and a pulse that is too short for its driver arrives as a runt (FN19-5). Storage-cell design: why a latch cannot be written and how to fix it (FN19-9), and a small sequential design with a synchronous reset (Problem Set 5’s counter, PS5-Q2). Together they are 47 points of the two finals (FN12-7a 15, FN19-5 22, FN19-9 10).

Each family opens with How to approach it: the picture that announces it, the moves in order, the formulas with their conditions, and the traps. Then each question is quoted in the paper’s own words and solved part by part: what it asks, the idea, why this formula, the steps (each with its reason first), a check by another route, the answer, and what to remember. Try each part first; open the Hint if stuck. The key’s verdict is folded at the end of each part: FN12 has a key, FN19 has none (only an unofficial proposed solution, used as a cross-check), and PS5 has none. Every family ends with harder variations added, longer chains on unfamiliar circuits with more arithmetic, the way the real Fall 2026 midterm was harder than the samples. Page numbers are the PDF’s physical pages.

Before you start. These questions rest on Chapter 13 (the static latch, the write fight, gated feedback, the master–slave flip-flop), Chapter 14 (two-phase clocks and their generator, pulsed latches, the chopper, runt pulses) and Chapter 15 (TSPC and half latches). Each question below restates what it uses.

Symbols

Symbol	Meaning	Unit	First appears
φ, φ̄	a global clock and its complement (made by an inverter)	—	FN12-7
φ1, φ2	the two phases a local generator makes from φ	—	FN12-7
$\Delta_1$Δ1​, $\Delta_2$	the delay blocks of the generator: φ2 delayed by $\Delta_1$ feeds φ1’s NOR, φ1 delayed by $\Delta_2$ feeds φ2’s NOR	ps	FN12-7
$t_{overlap}$	Chapter 14’s name for the non-overlap window, when both phases are low	ps	FN12-7
$t_{NOR}$tNOR​, $t_{inv}$	the delay of one NOR gate, of one inverter	ps	Variation 1
ψ1, ψ2	the phases of the NAND generator (Variation 2)	—	Variation 2
$\Delta$	the chopper’s delay block, which the paper calls the pulse width	ps	FN19-5
CLK1, CLK2; lclk	the clocks at the two latches of FN19-5; a chopped (pulsed) local clock	—	FN19-5
$t_{pulse}$	the width of a chopped pulse	ps	FN19-5
$\delta$	signed skew: the capturing clock’s edge minus the launching clock’s edge ($\delta < 0$δ<0: the capture clock is early)	ps	FN19-5
$t_{clk\to Q}$tclk→Q​, $t_{setup}$tsetup​, $t_{hold}$	clock-to-Q delay, setup time, hold time of a latch or flip-flop	ps	FN19-5
$t_{logic}$	the delay of the logic between two clocked elements (its shortest value for hold)	ps	FN19-5
$\tau_1$	FO1 delay: an inverter driving one copy of itself (the paper’s symbol; the chapters write $\tau_{inv}$τinv​)	ps	FN19-5
$C_g$Cg​, $C_{in}$Cin​, $C_L$	gate capacitance per µm; a driver’s input capacitance; its load	fF/µm, fF	FN19-5
$t_d$	a driver’s 50% delay into its load	ps	FN19-5
$\tau_{RC}$	the time constant of an RC whose 50% delay is $t_d$td​: $t_d/\ln 2$	ps	FN19-5
$V_{DD}$VDD​, $V_M$VM​, $V_T$	supply; an inverter’s switching threshold; a threshold voltage	V	FN19-5, FN19-9
A, X, Y	FN19-9’s input, its storage node (named here), its output	—	FN19-9
$R$R, $W$	the course’s device resistance (a 1 µm NFET pulling down) and a width; an NFET of width $W$ is $R/W$R/W, a PFET $2R/W$	kΩ·µm, µm	FN19-9
$R_{down}$Rdown​, $R_{up}$	the series resistance of the devices pulling X down, pulling it up	—	FN19-9
clk, $\overline{\mathrm{clk}}$	a latch’s clock and its complement	—	FN19-9
$Q_1$Q1​, $Q_0$Q0​; reset	the counter’s two bits; its synchronous reset input (the paper’s name)	—	PS5-Q2
$T_{cycle}$Tcycle​, $f$	the clock period and frequency	ps, GHz	PS5-Q2
$C_s$Cs​, $I_{leak}$Ileak​, $\Delta V_{max}$	a dynamic node’s capacitance, its leakage current, the droop the next gate still reads correctly	fF, nA, V	Variation 5

How to approach a clock-generation question

Recognize it by the picture: a box labelled CG (or CC) followed by “≡” and a handful of gates, an inverter and one or two boxes marked Δ, with one clock in and one or two clocks out. The prompt says “sketch the waveforms”, “indicate the delays on your sketch”, or “how must Δ be adjusted”. FN12-7 is the type: two NOR gates cross-coupled through delay blocks make two phases that are never high together.

The moves.

1. Read every wire. Write each gate’s output as a function of its inputs, with each delayed input written as the signal it comes from, shifted: $\phi_1 = \text{NOR}(\phi,\ \phi_2 \text{ delayed by } \Delta_1)$NOR(ϕ, ϕ2​ delayed by Δ1​). Which net feeds which delay block is the whole question.
2. Find each gate’s controlling value. A NOR’s output is 0 as soon as any input is 1 (1 controls a NOR); it goes to 1 only when all inputs are 0. A NAND is the mirror: 0 controls it.
3. Walk each edge of the input clock. When an input takes the controlling value, the output changes at once (plus the gate’s own delay, if it counts). When an input leaves the controlling value, the output must wait for its slowest other input, usually a delayed signal: that wait is where the Δ appears on the sketch.
4. Mark the windows between the edges that the delays separate, and say which edge each window follows.
5. If a timing question follows, decide which phase drives the master latch and which the slave: the window between the master’s closing edge and the slave’s opening edge is the one that protects hold.

The formulas.

• The generator’s windows (Derive, from the NOR truth table; Chapter 14 §3): for $\phi_1 = \text{NOR}(\phi, \Delta_1(\phi_2))$NOR(ϕ,Δ1​(ϕ2​)), $\phi_2 = \text{NOR}(\overline\phi, \Delta_2(\phi_1))$ with ideal gates, φ2 rises $\Delta_2$ after φ rises and φ1 rises $\Delta_1$ after φ falls; each phase falls at once with its own input. It holds while each delay is shorter than the half period it sits in.
• With gate delays (Derive, Variation 1): each window becomes $\Delta + t_{NOR}$tNOR​, because the delayed signal is itself a NOR output, one gate delay late.
• The window hold needs (Derive, Chapter 14 §3): $t_{overlap} \ge t_{skew} + t_{hold} - t_{clk\to Q} - t_{logic}$tlogic​, paid for on the long path, $t_{logic} \le T_{cycle} - (t_{clk\to Q} + t_{setup}) - t_{overlap}$toverlap​.

Decide on the way: whether gate delays are ignored (FN12-7a says so), which phase is the master, and whether the question wants the phases apart (non-overlap, for latches) or together (overlap, for two-phase domino; Variation 2).

Traps. Swapping $\Delta_1$ and $\Delta_2$Δ2​: read which output each delay block takes. Drawing the two phases as mirror images: the windows are $\Delta_2$ at one edge and $\Delta_1$ at the other, and with gate delays the phases have different widths. Forgetting that a phase falls at once: only the rising edges wait.

1. FN12-7: a local clock generator (15 points of 30)

You need

The NOR gate. A NOR’s output is high only when both inputs are low. If either input is 1, the output is 0, whatever the other input does: 1 is the NOR’s controlling value.

A delay block. A box Δ (an even number of inverters, so it does not invert) passes its input through unchanged, $\Delta$ later: its output at time $t$ is its input at $t - \Delta$Δ.

Why two non-overlapping phases (Chapter 14 §3). A flip-flop is two latches on two phases, the master on φ1 and the slave on φ2. If φ1 falls a little before φ2 rises, both phases are low for a moment, the non-overlap window: the receiving master closes before the launching slave opens, which protects hold, at the cost of that much dead time on the long path. A local generator makes the window from one global clock wire.

Chapter 14’s two-phase flip-flop pair (Lecture13 @ 24:39, redrawn): pulling φ1’s falling edge earlier opens the window $t_{overlap}$ in which both phases are low. Original figure ↗

The question (FN12-7, p10, in the paper’s words). Consider the “local clock generator” circuit shown below, used to generate two clock phases locally from a single-wire global clock. The delay blocks (labelled with $\Delta_1$ and $\Delta_2$Δ2​) could be implemented with an even number of inverters (for example).

FN12-7’s local clock generator (p10, redrawn): CG ≡ two NORs and an inverter. $\phi_1 = \text{NOR}(\phi, \Delta_1(\phi_2))$ and $\phi_2 = \text{NOR}(\overline\phi, \Delta_2(\phi_1))$NOR(ϕ​,Δ2​(ϕ1​)): each delay block takes the other phase. Below, the paper’s φ (50% duty, printed from half a period before its first rising edge to three periods), with empty rows for φ1 and φ2. The key’s handwritten notes are left out.

The exam’s own figure (FN12-7, p10)

FN12-7, p10 (source figure). The handwritten 1/0 notes on the wires are the key’s.

Part (a): sketch φ1 and φ2 (15 points)

FN12-7a, p10. Sketch the $\phi_1$ and $\phi_2$ waveforms for the $\phi$ waveform shown below. Ignore the gate delays of the inverter and NOR gates but indicate the $\Delta_1$ and $\Delta_2$ delays on your sketch. (15 points)

Hint

Each NOR goes high only when both its inputs are low. Right after φ rises, which input of φ2’s NOR is still high, and for how long?

What it asks. Two waveforms, drawn under the paper’s φ (a square wave, low first, with three high pulses): φ1 and φ2, with the two delays marked where they show. The word that sets the method is “ignore the gate delays”: every gate switches the instant its inputs allow, so the only times on the sketch are φ’s edges and those edges shifted by $\Delta_1$ or $\Delta_2$Δ2​. Nothing is computed; the 15 points are for getting each edge in the right place, with its reason.

The idea. Write each output as a Boolean function of its inputs, then walk the edges of φ one at a time. A NOR answers a 1 on any input at once, so each phase falls the instant its direct input (φ for φ1, φ̄ for φ2) goes high. It rises only when both inputs are low, and one of them is the other phase delayed. So a phase can rise only a delay after the other phase has fallen. That is what keeps them apart: there is always a gap in which both are low.

Why this formula. The two equations are read straight off the wires. The upper NOR takes φ directly and the output of $\Delta_1$Δ1​, whose input is the φ2 line, so $\phi_1 = \text{NOR}(\phi, \Delta_1(\phi_2))$NOR(ϕ,Δ1​(ϕ2​)). The lower NOR takes φ̄ from the inverter and the output of $\Delta_2$Δ2​, whose input is the φ1 line, so $\phi_2 = \text{NOR}(\overline\phi, \Delta_2(\phi_1))$NOR(ϕ​,Δ2​(ϕ1​)). A delay block’s output at time $t$ is its input at $t - \Delta$Δ: it is an even chain of inverters, so it does not invert, as the paper says. The NOR rule is all that is needed: output 1 exactly when both inputs are 0. Two conditions make the walk below valid. First, the gate delays are zero (the paper’s instruction); Variation 1 shows that with real gates each gap grows by one NOR delay. Second, each delay is shorter than the half period it falls in: $\Delta_2$ shorter than φ’s high time, $\Delta_1$ shorter than its low time, or the delayed phase would rise after φ had already changed again. The tempting shortcut, “φ1 is φ̄ and φ2 is φ, each delayed”, is wrong: a delayed copy would also be late at its falling edge, and that is the edge that does not wait here.

FN12-7a, edge by edge

1. Start before the first edge, with φ low. Because φ̄ = 1 is an input of φ2’s NOR, φ2 = 0. Then $\Delta_1(\phi_2) = 0$ and φ = 0, so both inputs of φ1’s NOR are low: φ1 = 1. The circuit sits in a steady state with φ1 high and φ2 low.
2. φ rises. Because φ is a direct input of φ1’s NOR, φ1 falls at once. At the same instant φ̄ falls, so φ2’s NOR has one low input; but its other input is φ1 delayed by $\Delta_2$Δ2​, and that copy still shows the old 1 for $\Delta_2$Δ2​. So φ2 rises $\Delta_2$ after φ rises. For those $\Delta_2$ both phases are low: the first window.
3. φ stays high. φ1 is held low by φ; φ2 stays high because φ̄ = 0 and the delayed φ1 is now 0.
4. φ falls. φ̄ rises, and it is a direct input of φ2’s NOR, so φ2 falls at once. φ1’s NOR now sees φ = 0, but its other input is φ2 delayed by $\Delta_1$Δ1​, still 1 for $\Delta_1$Δ1​. So φ1 rises $\Delta_1$ after φ falls. For those $\Delta_1$ both phases are low: the second window.
5. φ stays low, φ1 stays high, φ2 stays low, and the next rising edge of φ repeats step 2. Every cycle looks the same.
6. Draw it. Under each high pulse of φ: φ1 low for the whole pulse, and φ2 high from $\Delta_2$ after the rising edge to the falling edge. Under each low stretch of φ: φ2 low, and φ1 high from $\Delta_1$ after the falling edge until the next rising edge. Mark $\Delta_2$ as the gap after each rising edge of φ and $\Delta_1$ as the gap after each falling edge.

The answer, drawn in Chapter 14 for the same circuit added: φ1 high from $\Delta_1$ after each falling edge of φ to the next rising edge; φ2 high from $\Delta_2$ after each rising edge to the next falling edge. Drawn with $\Delta_1 = 0.10\,T$ and $\Delta_2 = 0.06\,T$0.06T, gate delays ignored. Original figure ↗

Check. Two independent tests. First, the never-both-high property: at every moment one of the two NORs has a 1 on its direct input (φ for the top one, φ̄ for the bottom one), so at most one phase can be high, and the sketch must never show both high; it doesn’t. Second, a limit: let both delays shrink to zero. The equations then give φ1 = NOR(φ, φ2) and φ2 = NOR(φ̄, φ1), whose steady states are φ1 = φ̄ and φ2 = φ, a plain complementary pair; the sketch, with its gaps shrunk to nothing, must turn into exactly that, and it does. A third, mechanical check: this page’s test runs the same circuit in an event-driven gate simulator, and the edges come out at $\Delta_2$ after φ rises and $\Delta_1$ after φ falls.

Answer: φ2 is high from $\Delta_2$ after each rising edge of φ until that pulse’s falling edge; φ1 is high from $\Delta_1$ after each falling edge of φ until the next rising edge. Each phase falls with an edge of φ at once; both are low for $\Delta_2$ after every rising edge and for $\Delta_1$ after every falling edge.

Remember. A NOR falls at once and rises late. In a cross-coupled generator, each phase waits a delay for the other one to be gone: read which phase feeds which delay, then walk the edges.

The answer key agrees

The key’s sketch (p10) has φ1 falling with each rising edge of φ and rising $\Delta_1$ after each falling edge, and φ2 rising $\Delta_2$ after each rising edge and falling with each falling edge, with the four gaps labelled.

The key’s sketch (FN12-7a, p10)

FN12-7a, p10: the printed φ (top) and the key’s handwritten φ1 and φ2, with the gaps $\Delta_1$ and $\Delta_2$ marked.

Variations: clock generation

Two added variations added, each a chain of dependent parts. Variation 1 puts the gate delays back into FN12-7’s generator and asks for a window, a hold repair, its cost and the fastest clock. Variation 2 swaps the NORs for NANDs: the phases then overlap, which is what two-phase domino wants and what a pair of latches must never see.

Variation 1: the generator with its gate delays (added)

Variation 1: the generator with its gate delays

The question added. FN12-7’s generator is built from real gates: each NOR takes $t_{NOR} = 30$ ps and the inverter $t_{inv} = 20$ ps; $\Delta_1 = 100$ ps and $\Delta_2 = 60$ ps. φ runs at 1 GHz with a 50% duty cycle and rises at $t = 0$0. The phases clock master–slave flip-flops, master on φ1 and slave on φ2, with $t_{clk\to Q} = 40$ ps, $t_{setup} = 20$ ps and $t_{hold} = 15$ ps. (a) Find every edge of φ̄, φ1 and φ2 in the first cycle. (b) Give the two non-overlap windows, in numbers and in terms of $\Delta$ and $t_{NOR}$tNOR​, and the two phases’ high times. (c) A receiving pair of flip-flops gets its phases 150 ps late, and the shortest logic between the pairs is none at all (a shift register). Does hold pass? If not, what $\Delta_2$ repairs it? (d) With that $\Delta_2$Δ2​, what is the longest logic allowed between two pairs on unskewed clocks at $T_{cycle} = 1$ ns, and between the late pair? (e) Each latch needs its clock high for at least 200 ps to be written reliably. With the $\Delta_2$ of (c), what is the shortest period of φ?

The generator and its ideal waveforms (Chapter 14 added): φ2 delayed by $\Delta_1$ feeds φ1’s NOR, φ1 delayed by $\Delta_2$ feeds φ2’s NOR. Original figure ↗

Hint

When a phase finally rises, which signal let it, and how many gates and delay blocks has that signal passed through since the edge of φ?

What it asks. The same circuit as FN12-7a with the gates no longer instantaneous, and then four consequences in a chain: the size of the windows, whether one of them is wide enough for a skewed shift register, what the repair costs the long path, and how fast φ may run before a phase gets too short. The word that decides the method is “edges”: every answer comes from a list of edge times, so build that list first, carefully, and read everything else off it.

The idea. The walk is the one of FN12-7a with each gate adding its delay to whatever passes through it. An edge of φ reaches each NOR by two routes, directly (or through the inverter) and the long way round, through the other NOR and a delay block. A NOR that falls does so one gate delay after a 1 arrives; a NOR that rises waits for its last input to fall. The window between the two phases is then the long route’s extra length: one delay block and one NOR. The hold and long-path questions are Chapter 14’s, with this window as $t_{overlap}$toverlap​.

Why this formula. Four relations, each with its reason.

• Edge times. A gate’s output changes $t_{gate}$ after the input change that decides it. For a NOR, a rising input decides at once (1 controls); a falling input decides only if it was the last one high. So φ1 falls at $t_{NOR}$ after φ rises, but φ2 rises at $\max(t_{inv},\ t_{NOR} + \Delta_2) + t_{NOR}$ after φ rises: its two inputs are φ̄ (low after $t_{inv}$tinv​) and the delayed φ1 (low after $t_{NOR} + \Delta_2$Δ2​). Here $t_{NOR} + \Delta_2 = 90 > 20$20, so the delayed φ1 is last.
• The windows. From φ1’s fall at $t_{NOR}$ to φ2’s rise at $t_{NOR} + \Delta_2 + t_{NOR}$ is $\Delta_2 + t_{NOR}$tNOR​: one block and the NOR that responds to it. The inverter drops out of the window, as long as it is faster than that route; it only shifts both edges at φ’s falling edge by $t_{inv}$tinv​.
• The hold window (Chapter 14 §3): with the master on φ1 and the slave on φ2, data launches when φ2 rises (the slave opens), and the receiving master closes when its φ1 falls, $t_{skew}$ late. The window moves that capture edge earlier relative to the launch: $t_{overlap} \ge t_{skew} + t_{hold} - t_{clk\to Q} - t_{logic}$tlogic​. The window that counts is the one from φ1’s fall to φ2’s rise, the master’s closing to the slave’s opening; widening the other one does nothing for this race.
• The long path: $t_{logic} \le T_{cycle} - (t_{clk\to Q} + t_{setup}) - t_{overlap}$toverlap​, Chapter 14’s board form without skew; a late capture clock adds its skew back.

Variation 1

1. (a) φ rises at 0. Because the inverter takes 20 ps, φ̄ falls at 20. Because φ is a direct input of φ1’s NOR and a 1 controls a NOR, φ1 falls one NOR delay later, at 30.
2. (a) φ2 rises. Its NOR needs both inputs low. φ̄ is low from 20; the delayed φ1 falls $\Delta_2$ after φ1, at $30 + 60 = 90$90, which is later. So φ2 rises one NOR delay after 90: at 120.
3. (a) φ falls at 500. φ̄ rises at 520, and a 1 controls φ2’s NOR, so φ2 falls at 550. φ1’s NOR has φ low from 500 and the delayed φ2 low from $550 + 100 = 650$650; the later one decides, so φ1 rises at $650 + 30 =$ 680. At the next rising edge, 1000, φ1 falls at 1030, and the cycle repeats.
4. (b) The windows. From φ1’s fall (30) to φ2’s rise (120): 90 ps $= \Delta_2 + t_{NOR}$tNOR​. From φ2’s fall (550) to φ1’s rise (680): 130 ps $= \Delta_1 + t_{NOR}$tNOR​.
5. (b) The high times. φ2: $550 - 120 =$ 430 ps $= T/2 + t_{inv} - t_{NOR} - \Delta_2$Δ2​. φ1: $1030 - 680 =$ 350 ps $= T/2 - t_{inv} - t_{NOR} - \Delta_1$Δ1​. The phases are unequal: φ1 loses its delay block, and the inverter shifts time from φ1 to φ2.
6. (c) What hold needs. Because the window must cover the skew and the hold time that the flip-flop’s own delay does not: $t_{overlap} \ge 150 + 15 - 40 - 0 = 125$ ps. The window after the master’s closing edge is 90 ps: hold fails by 35 ps.
7. (c) The repair. Because that window is $\Delta_2 + t_{NOR}$tNOR​, widen $\Delta_2$Δ2​: $\Delta_2 + 30 \ge 125$125, so $\Delta_2 \ge$ 95 ps. ($\Delta_1$Δ1​ would not help: it sits after the slave’s closing edge.)
8. (d) The cost. Because the window is dead time in every cycle, the long path between unskewed pairs loses it: $t_{logic} \le 1000 - (40 + 20) - 125 =$ 815 ps, against 940 ps with no window. Between the pair whose capture clock is 150 ps late, the late edge gives the time back: $815 + 150 =$ 965 ps.
9. (e) The shortest period. With $\Delta_2 = 95$95: φ1 is high for $T/2 - 150$150, which must be at least 200, so $T \ge 700$ ps; φ2 is high for $T/2 + 20 - 30 - 95 = T/2 - 105$105, so $T \ge 610$ ps. The narrower phase, φ1, sets it: $T \ge$ 700 ps, about 1.43 GHz, where φ1 is high for 200 ps and φ2 for 245 ps.

Variation 1’s edges added, computed from $t_{NOR} = 30$ ps, $t_{inv} = 20$ ps, $\Delta_1 = 100$ ps, $\Delta_2 = 60$ ps, φ at 1 GHz: each window is a delay block plus one NOR, 90 ps long after φ rises (30 to 120 ps) and 130 ps long after it falls (550 to 680 ps).

Check. Every instant of a period belongs to exactly one of four intervals: φ1 high, φ2 high, or one of the two windows (one NOR always has a 1 on its direct input, so the phases are never both high). A paper route for (c), walked on the timeline with $\Delta_2 = 95$ ps: the launching slave opens when φ2 rises, at $30 + 95 + 30 = 155$ ps, and the data reaches the late master $t_{clk\to Q} = 40$ ps later, at 195 ps. That master closes when its φ1 falls, $30 + 150 = 180$ ps, and needs its input held until $180 + 15 = 195$ ps: met exactly, as (c) says ✓. Independently, this page’s test runs the circuit in an event-driven gate simulator with these delays and finds the same six edges (20, 30, 120, 520, 550, 680 ps), and a 125 ps window after the change of $\Delta_2$Δ2​.

Answer: (a) φ̄ falls at 20 and rises at 520 ps; φ1 falls at 30 and rises at 680 ps; φ2 rises at 120 and falls at 550 ps. (b) Windows 90 ps ($\Delta_2 + t_{NOR}$Δ2​+tNOR​) and 130 ps ($\Delta_1 + t_{NOR}$Δ1​+tNOR​); φ2 high 430 ps, φ1 high 350 ps. (c) Hold needs 125 ps and fails by 35 ps; $\Delta_2 \ge 95$ ps. (d) 815 ps between unskewed pairs, 965 ps into the late pair. (e) $T \ge 700$ ps.

Remember. With real gates each window is the delay block plus one NOR, and the two phases come out unequal. For hold, widen the window that follows the master’s closing edge, then pay for it on the long path and check that the shorter phase is still long enough.

Variation 2: a NAND generator, whose phases overlap (added)

Variation 2: a NAND generator, whose phases overlap

The question added. Replace both NOR gates of FN12-7’s generator by NAND gates, keeping every wire: $\psi_1 = \text{NAND}(\phi, \Delta_1(\psi_2))$ and $\psi_2 = \text{NAND}(\overline\phi, \Delta_2(\psi_1))$NAND(ϕ​,Δ2​(ψ1​)). Gates are ideal; φ has $T = 1$ ns, 50% duty, rising at 0; $\Delta_1 = 30$ ps, $\Delta_2 = 50$ ps. (a) Sketch ψ1 and ψ2. (b) When are both high, and for how long? (c) The phases clock a two-phase domino pipeline, a block evaluating while ψ2 is high feeding a block evaluating while ψ1 is high, and the designer wants to drop the mid-cycle latch between them. The ψ1 block’s first stage takes 40 ps to evaluate, and 10 ps of margin is wanted. Is $\Delta_2$ enough? How long does the ψ2 block have to evaluate, and to precharge? (d) Someone instead clocks static master–slave flip-flops with these phases, master on ψ1 and slave on ψ2, $t_{clk\to Q} = 40$ ps and $t_{hold} = 15$ ps. What shortest logic does hold now demand, with no skew and with the receiving pair 60 ps late? (e) Which generator belongs with which design?

FN12-7’s generator, whose wiring this variation keeps: replace both NORs by NANDs and rename the outputs ψ1 and ψ2. Original figure ↑

Hint

A NAND’s output is 0 only when both inputs are 1. When φ rises, which NAND sees a 0 at once, and which has to wait?

What it asks. An unfamiliar circuit, read the same way as FN12-7, then two uses of its result: in a domino pipeline, where Chapter 15 wants the phases to overlap, and in a flip-flop, where Chapter 14 wants them apart. The words that decide the method are “both high”: with NANDs the danger and the benefit are overlaps, not gaps.

The idea. A NAND is a NOR turned inside out: 0 controls it, and its output is 1 as soon as any input is 0. So each phase now rises at once with its direct input and falls only a delay after the other phase has risen. Instead of two gaps per cycle, the generator makes two overlaps, one after each edge of φ, $\Delta_1$ and $\Delta_2$ long. Whether an overlap is wanted depends on what the phases clock.

Why this formula. The NAND rule: output 0 exactly when both inputs are 1. The edge walk is FN12-7a’s with the roles of 0 and 1 swapped. For the domino use, Chapter 15’s rule for dropping a mid-cycle latch is $\Delta_{12} \ge t_{eval,1}$ (Chapter 15 §10): the block that receives must start evaluating (its clock rises) before the block that sends starts precharging (its clock falls), for long enough that its first stage has discharged, because domino is monotonic and a discharged node stays down when its input goes away. For the flip-flop use, an overlap is a non-overlap window of negative length: in Chapter 14’s hold inequality the window enters with the opposite sign, $t_{clk\to Q} + t_{logic} \ge \delta + t_{hold} + t_{ov}$tov​, where $t_{ov}$ is the time from the launching slave’s opening to the receiving master’s closing. While both latches are open the data can run straight through the pair, and the race gets that much longer.

Variation 2

1. (a) Before the first edge, φ low. Because φ = 0 is a direct input of ψ1’s NAND, ψ1 = 1. φ̄ = 1 and the delayed ψ1 = 1, so ψ2 = 0.
2. (a) φ rises at 0. φ̄ falls, and a 0 controls ψ2’s NAND: ψ2 rises at once. ψ1’s NAND now has φ = 1, but the delayed ψ2 still shows 0 until $\Delta_1$Δ1​, so ψ1 falls at 30 ps.
3. (a) φ falls at 500. A 0 on ψ1’s direct input: ψ1 rises at once, at 500. ψ2’s NAND has φ̄ = 1, and the delayed ψ1 still shows 0 until 550, so ψ2 falls at 550 ps.
4. (b) The overlaps. Both are high on $[0, 30)$[0,30), 30 ps $= \Delta_1$ after φ rises, and on $[500, 550)$[500,550), 50 ps $= \Delta_2$ after φ falls; the next cycle repeats them from $[1000, 1030)$[1000,1030). ψ2 is high for 550 ps and ψ1 for 530 ps.
5. (c) The mid-cycle latch. The sending block is on ψ2, the receiving one on ψ1. ψ1 rises at 500 and ψ2 falls at 550, so $\Delta_{12} = \Delta_2 = 50$ ps. Because the receiving block’s first stage must evaluate while its input is still valid, it needs $40 + 10 = 50$ ps: just enough.
6. (c) The budgets. The ψ2 block starts evaluating at 0 and its result must be ready when ψ1 rises at 500: 500 ps, the full half cycle, because this generator stretches ψ2 instead of moving ψ1’s edge earlier (in Chapter 15’s example the overlap came out of the sending block’s budget). The price is its precharge: ψ2 is low only from 550 to 1000, 450 ps.
7. (d) The flip-flop race. Data launches when the slave opens, ψ2 rising at 0. The receiving master closes when ψ1 falls, at 30 ps. So $t_{ov} = 30$ ps, and hold demands $t_{logic} \ge \delta + t_{hold} + t_{ov} - t_{clk\to Q} = 0 + 15 + 30 - 40 =$ 5 ps with no skew, and $60 + 15 + 30 - 40 =$ 65 ps with the receiving pair 60 ps late. A shift register, with no logic, now fails even on perfect clocks.
8. (e) The match. The NOR generator keeps the phases apart: latches and flip-flops, whose hold it protects. The NAND generator makes them overlap: two-phase domino that drops its mid-cycle latches. Each delay block sets the length of the gap, or of the overlap, after one edge.

Variation 2’s NAND generator added: FN12-7’s wiring with NAND gates, and its phases computed for $T = 1$ ns, $\Delta_1 = 30$ ps, $\Delta_2 = 50$ ps, ideal gates. Each phase rises with an edge of φ and falls a delay after the other has risen, so both are high (shaded) for $\Delta_1$ after each rising edge of φ (0–30 and 1000–1030 ps) and for $\Delta_2$ after each falling edge (500–550 ps).

Check. At every instant one of the two NANDs has a 0 on its direct input (φ for ψ1, φ̄ for ψ2), so at least one phase is high, always. A second route, by De Morgan: $\text{NAND}(a, b) = \overline{\text{NOR}(\overline a, \overline b)}$NOR(a,b)​, so $\overline{\psi_2} = \text{NOR}(\phi, \Delta_2(\overline{\psi_1}))$ and $\overline{\psi_1} = \text{NOR}(\overline\phi, \Delta_1(\overline{\psi_2}))$NOR(ϕ​,Δ1​(ψ2​​)): FN12-7’s NOR generator, with $\overline{\psi_2}$ as its φ1, $\overline{\psi_1}$ as its φ2, and the two delays swapped. By FN12-7a, its φ2 rises $\Delta_1 = 30$ ps after φ rises and its φ1 rises $\Delta_2 = 50$ ps after φ falls: so ψ1 falls at 30 ps and ψ2 at 550 ps, and the NOR generator’s gaps are this one’s overlaps ✓. This page’s test also simulates the NAND circuit and finds ψ2 rising at 0 and falling at 550 ps, ψ1 falling at 30 and rising at 500 ps.

Answer: (a) ψ2 high from each rising edge of φ to 50 ps after the falling edge; ψ1 high from each falling edge to 30 ps after the next rising edge. (b) Both high for 30 ps after φ rises and 50 ps after φ falls. (c) Yes, exactly: 50 ps ≥ 40 + 10 ps; the ψ2 block keeps 500 ps to evaluate and has 450 ps to precharge. (d) $t_{logic} \ge 5$ ps without skew, 65 ps with the pair 60 ps late. (e) NOR generator for latches and flip-flops, NAND generator for two-phase domino.

Remember. Cross-coupled NORs make gaps (both low), cross-coupled NANDs make overlaps (both high), each as long as a delay block. Latches want gaps; domino that drops a latch wants an overlap.

How to approach a pulsed-latch question

Recognize it by a box CC (clock chopper, one-shot) that expands to an inverter, a delay block Δ and a NOR, feeding the clock input of a latch; by the phrases “clock-chopped flip-flops”, “the pulse width of the chopped clock”, “a hold time on the closed clock edge”; and, in a second part, by a driver with a load capacitance and the question “what will be the height of the pulse?”. FN19-5 is the type.

The moves.

1. Read the chopper. Find when both NOR inputs are low: for a NOR of the clock and a delayed, inverted copy, that is just after each falling clock edge, for as long as the delayed copy lags (Chapter 14 §5). The width is the chain’s delay; the papers call Δ the width and ignore the single inverter.
2. Put the launching pulse’s opening at $t = 0$ and the receiving pulse’s opening at $\delta$δ, the signed skew: negative if the receiving clock arrives earlier.
3. Hold. The pulsed latch is transparent until its pulse closes, so the earliest new data, $t_{clk\to Q} + t_{logic}$tlogic​, must arrive after $\delta + t_{pulse} + t_{hold}$thold​. Solve for the widest pulse.
4. The long path, if a period is given: the receiving latch takes data until its pulse closes, so one stage’s deadline moves $t_{pulse}$ later; but data that arrives inside the pulse leaves late by the same amount, so that time is borrowed from the next stage (Chapter 14 §4). For a pipeline of equal stages, use the limit that borrows nothing: the data reaches the receiving latch by its pulse’s opening.
5. Distribution. The pulse leaves through a driver whose delay into its load is $t_d = \tau_1\,C_L/C_{in}$τ1​CL​/Cin​. If $t_{pulse} < t_d$ the pulse does not reach half the swing: a runt. Its height is $1 - 2^{-t_{pulse}/t_d}$ of $V_{DD}$VDD​.

The formulas.

• Pulsed hold (Memorize, Chapter 14 §4): $t_{clk\to Q} + t_{logic} \ge \delta + t_{pulse} + t_{hold}$thold​, so $t_{pulse} \le t_{clk\to Q} + t_{logic,min} - t_{hold} - \delta$δ. It holds at the fast corner, with the shortest logic.
• A driver’s delay (Memorize, Chapters 7–8): $t_d = \tau_1 \times C_L/C_{in}$CL​/Cin​, its own drain capacitance ignored; the delay is the 50% point of the output’s swing.
• Runt height (Derive, Chapter 14 §6): an RC driven by a step reaches $1 - e^{-t/\tau_{RC}}$ of its swing; the 50% point at $t_d$ gives $\tau_{RC} = t_d/\ln 2$td​/ln2; so after $t_{pulse}$ the output has moved $1 - 2^{-t_{pulse}/t_d}$ of $V_{DD}$VDD​.

Decide on the way: the sign of the skew (an early receiving clock helps hold and allows a wider pulse); whether $t_{clk\to Q}$ is given (FN19-5 gives none: take it as zero and say so); and the runt convention (this guide uses Chapter 7’s 50%-point delay; say so on the paper).

Traps. Treating an early receiving clock as late, which caps the pulse 200 ps too low in FN19-5. Measuring hold from the pulse’s opening instead of its closing. Drawing the chopper’s pulse at the rising edge. Using $t_d$ itself as the time constant without saying so. Curing a runt by widening the pulse: hold caps the width.

2. FN19-5: a clock chopper and a runt pulse (22 points)

You need

The NOR clock chopper (Chapter 14 §5). A NOR of a clock and a copy of it delayed through an odd number of inverters gives one short high pulse per cycle, just after each falling clock edge: only then are both inputs low, the clock already low and the inverted copy not yet risen. The pulse is as wide as the chain’s delay; it does not depend on the clock’s period or duty cycle.

The clock chopper (Lecture13 @ 34:41, redrawn): lclk is high for the chain’s delay, $3t_{inv}$ here, after each falling edge of clk. Original figure ↗

A pulsed latch (Chapter 14 §4). One latch clocked by the short pulse acts almost like a flip-flop: it is transparent only while the pulse is high, and its setup and hold times are measured at the pulse’s closing edge.

A driver’s delay (Chapter 7’s model). An inverter whose FO1 delay is $\tau_1$ takes $\tau_1\,C_L/C_{in}$ to drive a load $C_L$CL​, where $C_{in}$ is its own input capacitance; this delay is measured at the 50% point of the swing.

The question (FN19-5, p11, in the paper’s words). Consider the clock chopper circuit shown below. The delay block (labelled $\Delta$Δ) can be implemented with an even number of inverters.

FN19-5’s figures (p11, redrawn). (a) The clock chopper: CC ≡ a NOR of φ and φ inverted and delayed by Δ, $\phi_{chopped} = \text{NOR}(\phi, \overline\phi \text{ delayed by } \Delta)$NOR(ϕ,ϕ​ delayed by Δ). (b) Two clock-chopped latches: each is clocked by its own chopper, from CLK1 and CLK2, with combinational logic between them.

The exam’s own figures (FN19-5, p11)

FN19-5, p11: the clock chopper.

FN19-5, p11: the two clock-chopped latches.

Part (a): the widest pulse (10 points)

FN19-5a, p11. Consider two clock-chopped flip-flops separated by combinational logic as shown below. Assuming that the combinational logic represents a fixed delay of 200 psec and there is skew between CLK1 and CLK2 such that CLK2 arrives 100 psec earlier than CLK1, what is the maximum value $\Delta$ (the pulse width of the chopped clock) can have and still ensure correct functionality? Assume that the latches have a hold time of 50 psec on their closed clock edge. (10 points)

Hint

While its pulse is high, the receiving latch is still taking in data. When does that pulse close, if CLK2 is 100 ps early, and when does the new data arrive?

What it asks. The largest pulse width for which the second latch is not corrupted: a hold question, because only the maximum Δ is asked and the pulse width is the thing that makes pulsed latches race. The words that set the numbers: “200 psec” is the logic’s delay, and “fixed” means it is also the shortest; “CLK2 arrives 100 psec earlier” is the sign of the skew; “hold time of 50 psec on their closed clock edge” says hold is measured from the end of the pulse. No clock-to-Q delay is given, so take $t_{clk\to Q} = 0$ and say so.

The idea. A pulsed latch is open for the whole pulse. The second latch must take the old data, the value launched one cycle earlier, until its pulse closes and for 50 ps after. Meanwhile the first latch opens and lets the new data race toward it through 200 ps of logic. A wider pulse keeps the second latch open longer, so at some width the new data gets in before it closes: that width is the answer. The early CLK2 helps: the receiving pulse opens, and therefore closes, 100 ps sooner.

Why this formula. The constraint is Chapter 14’s pulsed short path, $t_{clk\to Q} + t_{logic} \ge \delta + t_{pulse} + t_{hold}$thold​. Its left side is when the new data reaches the second latch’s D, measured from the first latch’s opening. Its right side is when the second latch stops caring about D: its pulse opens at $\delta$δ, stays open for $t_{pulse}$tpulse​, and needs $t_{hold}$ more. It applies because the two choppers are identical and pulse at the same edge of their clocks, so the pulses are offset by exactly the clocks’ skew; and because the logic is “fixed”, its shortest delay is 200 ps. The sign is the trap: with the capture clock early, $\delta = -100$ ps, and the skew loosens the constraint. Adding it as if it were late gives 50 ps. Hold is measured from the closing edge because a latch that is still transparent is still listening; measuring from the opening edge would ignore the pulse width, the very thing the question asks about.

Chapter 14’s pulsed hold check (Lecture13 @ 30:54, redrawn), drawn with a late capture clock: the new data must arrive after the receiving pulse has closed and $t_{hold}$ has passed. In FN19-5 the receiving pulse is early instead. Original figure ↗

FN19-5a

1. Read the chopper. $\phi_{chopped} = \text{NOR}(\phi, \overline\phi \text{ delayed by } \Delta)$NOR(ϕ,ϕ​ delayed by Δ). Because a NOR is high only when both inputs are low: just after φ falls, φ = 0, and the delayed φ̄ still shows the 0 it had while φ was high, for Δ. So each chopper pulses for Δ after each falling edge of its clock. (The inverter adds its own small delay to the width; the paper calls Δ the width, so it is ignored.)
2. Place the pulses. Because both choppers pulse at the same edge, the pulses are offset by the clocks’ skew. Put the first latch’s pulse at $[0, \Delta)$[0,Δ). CLK2 is 100 ps early, so the second latch’s pulse runs from $-100$ ps to $-100 + \Delta$Δ.
3. The new data. We need the earliest moment the second latch’s D can change. The first latch opens at 0 and, with no clock-to-Q delay given, its new output leaves at once; the logic takes 200 ps. So the new data reaches the second latch at 200 ps.
4. What the old data must cover. The second latch is transparent until $-100 + \Delta$ and needs D steady for 50 ps more: until $-100 + \Delta + 50$50.
5. Solve. Because the new data must not arrive before that: $200 \ge -100 + \Delta + 50$50, so $\Delta \le$ 250 ps.
6. Read the limit. At $\Delta = 250$ ps the second pulse closes at 150 ps, hold ends at 200 ps, and the new data arrives at exactly 200 ps: no margin left. A real design stays below.

FN19-5a at the limit added, computed from $\Delta = 250$ ps, $t_{logic} = 200$ ps, $t_{hold} = 50$ ps, CLK2 100 ps early and $t_{clk\to Q} = 0$0: the second latch’s pulse closes at 150 ps, its hold ends at 200 ps, and the new data reaches its D at exactly 200 ps.

Check. Two limits and a second constraint. Without skew, the second pulse would close at Δ and the bound would be $\Delta \le 200 - 50 = 150$ ps: the 100 ps of early capture clock buys exactly 100 ps of pulse, the right sign and size. With CLK2 100 ps late, the bound would fall to 50 ps, which is why the sign matters. The long path, the other side of “correct functionality”, cannot bite here: data launched at 0 arrives at 200 ps, and the second latch’s next pulse closes at $T - 100 + 250 = T + 150$ ps, so any period above 50 ps is fine.

Answer: $\Delta_{max} = 250$ ps (taking $t_{clk\to Q} = 0$0, which the paper does not give).

Remember. For a pulsed latch, hold is measured from the end of the receiving pulse: $t_{pulse} \le t_{clk\to Q} + t_{logic,min} - t_{hold} - \delta$δ. An early receiving clock ($\delta < 0$δ<0) allows a wider pulse.

The answer key agrees

FN19 has no official key. The unofficial proposed solution reaches 250 ps the same way (the receiving latch closes at $-100 + \Delta$Δ, the data arrives at 200 ps, latch delay neglected) and warns, as here, that reversing the skew’s sign gives the wrong bound.

Part (b): the chopped clock through a loaded inverter (12 points)

FN19-5b, p12. Assume that this chopped clock with the pulse width calculated in (a) is driven from an inverter with a load capacitance of 200 fF. The inverter is sized $4\ \mu\mathrm{m}\,/\,2\ \mu\mathrm{m}$ in a technology with a FO1 delay of $\tau_1=25\ \mathrm{psec}$25 psec. Assume a gate capacitance of $2\ \mathrm{fF}/\mu\mathrm{m}$2 fF/μm. Sketch the waveform of the clock as received by the latch. What will be the “height” of the pulse? What problems might this present? (12 points)

Chapter 14’s runt (Lecture13 @ 38:00, redrawn): a pulse shorter than the driver’s delay makes its output turn back before it has swung far. Panel (b) is FN19-5b’s case: the clock rises only part way, and it “may not even turn the latch on” (36:55). Original figure ↗

Hint

How long does this inverter take to drive 200 fF, and is the 250 ps pulse longer or shorter than that?

What it asks. Three things about the 250 ps pulse of (a) once it passes through a clock driver: the shape of the waveform at the latch, how far it swings (its “height”, the paper’s quotation marks hinting that it will not be full), and what that means for the latch. The numbers that decide it are the driver’s size, $4/2$ µm, the load, 200 fF, and the FO1 delay, 25 ps: together they give the driver’s delay, which is compared with the pulse. “This chopped clock … is driven from an inverter” is read as the inverter being the clock net’s driver: its output is the chopped clock, a high pulse commanded for 250 ps, and the latch receives that pulse, rounded by the 200 fF.

The idea. A driver needs time to swing its load: its 50% delay $t_d$td​. If the input pulse ends before the output has got that far, the output turns round halfway through its swing and never reaches the other rail. The pulse that arrives is a runt: shorter in height, and possibly too short to switch the latch’s clock at all. Here the pulse (250 ps) is shorter than the driver’s delay, so the runt is certain; the question is only how tall it is.

Why this formula. Two formulas, each with its conditions.

• The driver’s delay, $t_d = \tau_1\,C_L/C_{in}$τ1​CL​/Cin​. In the course’s model a stage’s delay is proportional to its load over its own input capacitance, and the FO1 delay is that ratio’s unit: an inverter driving a copy of itself has $C_L = C_{in}$ and takes $\tau_1$ (Chapter 7 §7). The inverter’s own drain capacitance is ignored (the paper gives none), and the 4/2 inverter is balanced in the course’s technology, where a PFET needs twice an NFET’s width for the same strength, so rising and falling take the same $t_d$td​.
• The height, $1 - 2^{-t_{pulse}/t_d}$2−tpulse​/td​. Model the output as an RC driven by a step: it moves the fraction $1 - e^{-t/\tau_{RC}}$ of its swing in a time $t$t. The course defines $t_d$ at the 50% point (Chapter 7 §1: the fitted $R$ already gives the 50% delay, so no extra 0.69), so $1 - e^{-t_d/\tau_{RC}} = \tfrac12$ and $\tau_{RC} = t_d/\ln 2$td​/ln2. Substituting, after $t_{pulse}$ the output has moved $1 - 2^{-t_{pulse}/t_d}$ of $V_{DD}$VDD​, and then it turns back. The condition is a step input and an output starting from rest at a rail; the driver’s input switches cleanly at the pulse’s start and end, which fits. The tempting alternative is to use $t_d$ itself as the time constant: that counts $\ln 2$ twice and gives a taller runt (the KeyNote has the number).

Chapter 14’s computed runt heights added: a pulse as long as $t_d$ just reaches $V_{DD}/2$VDD​/2; FN19-5’s pulse is $0.6\,t_d$0.6td​. Original figure ↗

FN19-5b

1. The driver’s input capacitance. Because one input drives both devices: $(4 + 2)\,\mu\mathrm{m} \times 2\,\mathrm{fF/\mu m} = 12$ fF.
2. Its load ratio. $200/12 = 16.7$16.7: it drives 16.7 copies of itself.
3. Its delay into the load. Because each copy costs one FO1 delay: $t_d = 25 \times 16.7 =$ 416.7 ps, the time the output takes to swing halfway.
4. Compare with the pulse. The pulse from (a) lasts 250 ps, $0.6\,t_d$0.6td​: it ends before the output reaches the middle of its swing. A runt.
5. The shape. Between pulses the chopped clock, the inverter’s output, sits at 0. When the pulse is commanded, the output rises along the RC curve, $v/V_{DD} = 1 - 2^{-t/t_d}$2−t/td​; when the pulse ends, 250 ps later, it turns round and decays back toward 0 with the same time constant, $\tau_{RC} = 416.7/\ln 2 = 601$ ps (the driver is balanced). So the latch sees a low, rounded bump instead of a square pulse: a runt.
6. The height. Because the output moves $1 - 2^{-t_{pulse}/t_d}$ of the swing: $1 - 2^{-0.6} = 1 - 0.660 =$ 0.34. The clock rises only to $0.34\,V_{DD}$0.34VDD​, and has decayed to about $0.04\,V_{DD}$ by 1.5 ns. (If the chopped pulse were instead the inverter’s input, the latch would see the same depth as a dip from $V_{DD}$ to $0.66\,V_{DD}$0.66VDD​, and the latch’s clock polarity would then be wrong as well.)
7. The problems. The received clock never crosses $V_{DD}/2$VDD​/2, so the latch’s clock input may never switch: the latch never opens and the data is lost, what the lecture calls a pulse that “may not even turn the latch on” (Lecture13, 36:55). If it switches partly, the latch opens weakly and late, and its window depends on process, voltage, temperature and noise, so setup and hold are no longer controlled.
8. The cure. The pulse cannot be widened: (a) caps it at 250 ps. So the driver must be faster: for $t_d \le 250$ ps, $C_{in} \ge 25 \times 200/250 = 20$ fF, a 10 µm inverter (6.67/3.33 µm), just to reach half the swing; for 90% of the swing, $t_d \le 250/\log_2 10 = 75.3$ ps, so $C_{in} \ge 66.4$ fF, 33.2 µm. Better still, put the chopper next to the latch it clocks (Chapter 14’s chopper in every flip-flop), so that the pulse never drives a large load.

FN19-5b’s chopped clock through the loaded inverter added, computed from $t_d = \tau_1 C_L/C_{in} = 416.7$ ps and the 250 ps pulse, with the 50%-point RC model. Dashed: the chopped pulse. Solid: the clock the latch receives, which rises as $1 - 2^{-t/t_d}$ for 250 ps, to $0.340\,V_{DD}$0.340VDD​, and then decays, to about $0.04\,V_{DD}$ by 1.5 ns. It never reaches $V_{DD}/2$VDD​/2.

Check. Chapter 14’s computed curves bracket the answer: a pulse of $0.5\,t_d$ reaches 0.29 of the swing and one of $1\,t_d$ reaches 0.5, so $0.6\,t_d$ must lie between, and 0.34 does. A second route to the same number: $e^{-250/601} = 0.660$0.660, the fraction of the swing still left to go when the pulse ends. And the conclusion survives the other convention: with $t_d$ taken as the time constant, the height is $1 - e^{-0.6} = 0.451$0.451, still short of half the swing.

Answer: The latch receives a rounded runt: the clock rises from 0 for 250 ps and decays with $\tau_{RC} \approx 600$ ps; its “height” is about $0.34\,V_{DD}$0.34VDD​, never $V_{DD}/2$VDD​/2, because the driver’s delay into 200 fF, 417 ps, is longer than the pulse. The latch may not open at all, or opens weakly and unpredictably; widening the pulse is not allowed by (a), so the driver must be about 10 µm or more, or the chopper local.

Remember. A pulse must be wider than the delay of whatever drives it, or it does not reach half the swing. Compute $t_d = \tau_1 C_L/C_{in}$ first; the height is $1 - 2^{-t_{pulse}/t_d}$2−tpulse​/td​.

The answer key differs

FN19 has no official key. The unofficial proposed solution has the same delay, 416.7 ps, but gives $0.451\,V_{DD}$ as its main height, using $t_d$ itself as the RC time constant; its alternative, with $t_d$ read as the 50% delay, is our $0.340\,V_{DD}$0.340VDD​. The course defines delay at the 50% point (Chapter 7), so this page takes 0.34. It draws the received clock as a positive pulse rising from 0, as this page reads it. Its conclusions match: below half the swing, the latch may never open, and widening the pulse is ruled out by (a).

Variations: pulsed latches

Two added variations added. Variation 3 takes a pulsed design from the hold limit through the chopper’s chain, the distribution runt and the driver it would need, to the clock period it buys. Variation 4 uses a chopper no past paper draws, an XOR that pulses at both clock edges, and asks what that does to hold, to the long path, to the duty cycle and to clock power.

Variation 3: a pulsed design, end to end (added)

Variation 3: a pulsed design, end to end

The question added. A design uses pulsed latches, each clocked by a NOR chopper whose chain has an odd number of inverters of $t_{inv} = 18$ ps. The latches have $t_{clk\to Q} = 35$ ps, $t_{setup} = 10$ ps and $t_{hold} = 12$ ps, setup and hold measured at the pulse’s closing edge. Between latches the shortest logic is 60 ps and the longest 900 ps, and the clock skew between any two latches is up to 25 ps either way. (a) What is the widest pulse that works on every chip? (b) How many inverters does the chopper’s chain get, and what pulse results? (c) To save area, one chopper is to clock 16 latches: each latch’s clock input is 10 fF and the wire adds 40 fF. The chopper drives this net through an inverter of 10 fF input capacitance and 15 ps FO1 delay. How tall is the pulse at the latches? (d) What driver input capacitance would bring the pulse to $V_{DD}/2$VDD​/2, and to $0.9\,V_{DD}$0.9VDD​? (e) With each latch’s chopper beside it, what is the shortest clock period for the 900 ps path, and how does it compare with flip-flops of $t_{clk\to Q} = 60$ ps and $t_{setup} = 30$ ps under the same skew?

The NOR chopper (Chapter 14): the pulse is as wide as the odd chain’s delay. Original figure ↗

Hint

Which sign of skew is worst for hold, and which for the long path? They are not the same.

What it asks. A design flow in five dependent steps: a hold limit sets the pulse, the pulse fixes the chain, the chain’s pulse meets a distribution network, the network demands a driver, and the latches’ small overhead finally buys back clock period. The words that matter: “on every chip” means the worst skew of each sign, chosen separately for each constraint; “odd number of inverters” restricts the pulse to multiples of 18 ps with an odd count.

The idea. Pulsed latches trade one latch’s overhead for a hold problem the pulse width makes worse. So the width comes from hold first, with the receiving clock late, the worst case for hold. Then it has to survive distribution: a pulse shorter than its driver’s delay arrives as a runt. And it pays off on the long path, with the receiving clock early, the worst case for setup: a pulsed latch’s overhead is only its $t_{clk\to Q}$tclk→Q​, because its setup time hides inside the pulse. The pulse itself is not free time: what one stage uses of it, the next stage loses.

Why this formula. Three formulas, all Chapter 14’s.

• Hold: $t_{clk\to Q} + t_{logic,min} \ge \delta + t_{pulse} + t_{hold}$thold​, because the receiving latch takes the old data until its pulse closes. The worst $\delta$ is the late one, $+25$ ps.
• Runt height: $1 - 2^{-t_{pulse}/t_d}$ with $t_d = \tau_1 C_L/C_{in}$τ1​CL​/Cin​: a step into an RC whose 50% point is the course’s delay, as in FN19-5b. It assumes the driver’s own drain capacitance is negligible.
• Long path with a pulse (Chapter 14 §4): data is captured if $t_{clk\to Q} + t_{logic,max} + t_{setup} \le T_{cycle} + \delta + t_{pulse}$tpulse​, the receiving pulse’s closing edge less the setup time. But data arriving after the pulse opens leaves that much late, borrowing from the next stage. A stage that borrows nothing needs $t_{clk\to Q} + t_{logic,max} \le T_{cycle} + \delta$ (with $t_{pulse} \ge t_{setup}$tsetup​, setup is then met inside the pulse). The worst $\delta$ is now the early one, $-25$ ps. A flip-flop has no pulse but a larger overhead: $t_{clk\to Q} + t_{logic} + t_{setup} \le T_{cycle} + \delta$δ.

Variation 3

1. (a) The widest pulse. Because hold is worst with the receiving clock late: $t_{pulse} \le 35 + 60 - 12 - 25 =$ 58 ps.
2. (b) The chain. The count must be odd so that the delayed copy is inverted. One inverter gives 18 ps, three give 54 ps, five give 90 ps, too wide. Three it is, with 4 ps of hold margin left ($35 + 60 - (25 + 54 + 12) = 4$35+4).
3. (c) The shared net. Its load is $16 \times 10 + 40 = 200$ fF, 20 times the driver’s input, so $t_d = 15 \times 20 = 300$ ps. The 54 ps pulse is $0.18\,t_d$0.18td​, and it reaches only $1 - 2^{-0.18} =$ 0.117 of the swing: a 12% bump, which no latch will see as a clock.
4. (d) The driver it would need. For half the swing, $t_d \le 54$ ps: $C_{in} \ge 15 \times 200/54 =$ 55.6 fF. For 90%, $t_d \le 54/\log_2 10 = 16.26$ ps: $C_{in} \ge$ 185 fF, nearly the load itself. And that driver has a large input of its own, which the chopper’s NOR would have to drive with the same 54 ps pulse. Sharing one chopper does not work for a pulse this short: the chopper goes beside each latch.
5. (e) The pulsed period. Because setup is worst with the receiving clock early, and every stage of the pipeline may be a 900 ps stage, use the limit that borrows nothing: $T_{cycle} \ge 35 + 900 + 25 =$ 960 ps (1.04 GHz). The 54 ps pulse covers the 10 ps setup. The capture limit alone would allow $35 + 900 + 10 + 25 - 54 = 916$ ps, but only if the next stage has $35 + 900 - (916 - 25) = 44$ ps of slack to lend.
6. (e) The flip-flop period. $T_{cycle} \ge 60 + 900 + 30 + 25 =$ 1015 ps (0.985 GHz). The pulsed latches are 55 ps faster: their clock-to-Q is 25 ps shorter, and they hide the setup time that costs the flip-flop 30 ps.

Check. The hold margin at the chosen pulse is positive, 4 ps, and a five-inverter chain would make it $-32$ ps: the choice is forced. The runt height sits below Chapter 14’s 0.29 for a pulse of half the driver’s delay, as a pulse of $0.18\,t_d$ must. And the 960 ps period can be walked on the timeline: data leaves at 35 ps, arrives at $35 + 900 = 935$ ps, exactly when the early receiving pulse opens ($960 - 25 = 935$960−935), and is 44 ps clear of the setup deadline, $935 + 54 - 10 = 979$ ps ✓; it leaves the receiving latch on time, so the next stage starts unborrowed.

Answer: (a) 58 ps. (b) Three inverters, a 54 ps pulse (hold margin 4 ps). (c) About $0.12\,V_{DD}$0.12VDD​: a runt that will not clock anything. (d) $C_{in} \ge 55.6$ fF for half the swing, 185 fF for 90%: impractical, so one chopper per latch. (e) $T_{cycle} \ge 960$ ps pulsed against 1015 ps for the flip-flops, 55 ps faster (916 ps only if the next stage lends 44 ps).

Remember. Hold sets the pulse with the late receiving clock; setup sets the period with the early one. Along a pipeline the pulse lends time to one stage by taking it from the next: the gain is the latch’s smaller overhead. A short pulse must be made where it is used: a shared driver turns it into a runt.

Variation 4: a double-edge chopper (added)

Variation 4: a double-edge chopper

The question added. A designer builds the chopper with an XOR instead of a NOR: lclk = XOR(clk, clk delayed through four inverters of 15 ps each). Pulsed latches on lclk have $t_{clk\to Q} = 30$ ps, $t_{setup} = 10$ ps and $t_{hold} = 10$ ps (at the pulse’s closing edge); the skew is up to 20 ps either way; clk runs at 1 GHz. (a) Sketch lclk and give its pulse width. (b) How often does a latch on lclk take data, and what clock would Variation 3’s single-edge chopper need for the same data rate? (c) What is the shortest logic between latches that hold allows? (d) The clock’s duty cycle is actually 45%. What is the longest logic per stage, and what was it at 50%? (e) The clock network is 50 pF at $V_{DD} = 0.9$ V. Compare its power with a single-edge design that reaches the same data rate.

Chapter 14’s NOR chopper. For this variation, replace the NOR by an XOR and use four inverters. Original figure ↗

Hint

An XOR is high when its inputs differ. After an edge of clk, how long do clk and its delayed copy differ, and does it matter which way the edge went?

What it asks. A chopper no past paper draws, read from its truth table, and then the consequences of pulsing twice per period: the data rate, hold, a long path that now depends on the duty cycle, and clock power. The word that decides the method is “XOR”: unlike a NOR, it does not care which way its inputs change, only whether they differ.

The idea. After any edge of clk, clk has its new value at once and the delayed copy still has the old one, for the chain’s delay; four inverters do not invert, so “old” and “new” really differ. An XOR is high exactly then. So every edge, rising or falling, makes one pulse: the latch takes data twice per clock period. That halves the clock frequency needed for a given data rate, at the price of making each stage’s time depend on where the falling edge sits.

Why this formula. The XOR rule: output 1 when the inputs differ. The chain is even, so its output is clk delayed by $4 \times 15 = 60$ ps, not inverted. (With a NOR and an even chain there would be no pulse at all, only a shortened copy of $\overline{\mathrm{clk}}$clk: Chapter 14’s trap.) Hold is Chapter 14’s pulsed short path, $t_{logic} \ge \delta + t_{pulse} + t_{hold} - t_{clk\to Q}$tclk→Q​, with the receiving clock late. The long path uses the gap between consecutive pulses, which with two pulses per period is a half period, the high time after a rising edge and the low time after a falling edge. A stage that borrows nothing from the next (Chapter 14 §4) needs its data at the receiving latch by that pulse’s opening, $t_{clk\to Q} + t_{logic} \le t_{gap} + \delta$δ, and setup before it closes, $t_{clk\to Q} + t_{logic} + t_{setup} \le t_{gap} + \delta + t_{pulse}$tpulse​; the first is the tighter here. The receiving clock is early. Clock power is the switching power $P = \alpha\,C\,V_{DD}^2\,f$ with $\alpha = 1$1: a clock net charges and discharges once per cycle (Chapter 15 §9).

Variation 4

1. (a) The pulses. Because the XOR is high while clk and its 60 ps copy differ: lclk is high for 60 ps after every edge, rising and falling, at 0–60, 500–560, 1000–1060 ps, and so on.
2. (b) The data rate. Two pulses per period: a latch on lclk takes data at 2 GHz from a 1 GHz clock. The NOR chopper pulses once per period, so it would need a 2 GHz clock.
3. (c) Hold. With the receiving clock 20 ps late: $t_{logic} \ge 20 + 60 + 10 - 30 =$ 60 ps.
4. (d) At 45% duty. clk rises at 0 and falls at 450 ps, so the pulses start at 0, 450, 1000, 1450 ps: the gaps alternate between 450 and 550 ps. Every stage must work in the shorter one. With the receiving clock early and nothing borrowed: $t_{logic} \le 450 - 20 - 30 =$ 400 ps (the capture limit, $450 - 20 + 60 - 30 - 10 = 450$ ps, is looser).
5. (d) At 50% duty. Every gap is 500 ps: $t_{logic} \le 500 - 20 - 30 =$ 450 ps. A 5% duty-cycle error costs 50 ps of logic in every stage. At 45% duty, borrowing can legitimately win it back, because the short gap is always followed by the long one: a 450 ps stage in the 450 ps gap arrives 50 ps into its pulse, exactly at its setup deadline, and the next stage, starting 50 ps late in a 550 ps gap, has $550 - 50 - 20 - 30 = 450$ ps without borrowing. (The NOR chopper’s pulses are one full period apart, so its duty cycle does not matter.)
6. (e) Clock power. At 1 GHz: $P = 1 \times 50\,\mathrm{pF} \times (0.9\,\mathrm{V})^2 \times 1\,\mathrm{GHz} =$ 40.5 mW. The single-edge design needs 2 GHz for the same data rate: 81 mW. The double-edge chopper halves the clock network’s power.

Variation 4’s double-edge chopper added: lclk = XOR(clk, clk delayed by four inverters). Computed for $T = 1$ ns, 50% duty and a 60 ps chain ($4 \times 15$4× ps): lclk pulses for 60 ps after every edge of clk, rising and falling.

Check. The gaps can be read straight off the clock’s edges: the pulse after the falling edge at $0.45 \times 1000 = 450$ ps follows the one at 0 by 450 ps, and the next rising edge at 1000 ps follows it by 550 ps. The simulator in this page’s test runs the XOR circuit and finds exactly four 60 ps pulses in two periods, starting at 0, 500, 1000 and 1500 ps, and with the duty at 45% at 0, 450, 1000 and 1450 ps. With the same four inverters and a NOR, it finds no pulse at all, only a high stretch from 560 to 1000 ps, which confirms why the XOR is needed with an even chain.

Answer: (a) A 60 ps pulse after every edge of clk. (b) Data at twice the clock rate, 2 GHz from 1 GHz; a single-edge chopper would need a 2 GHz clock. (c) $t_{logic} \ge 60$ ps. (d) 400 ps at 45% duty, against 450 ps at 50%, borrowing nothing (450 ps at 45% if each short gap borrows from the long one after it). (e) 40.5 mW against 81 mW.

Remember. Read any chopper by asking when its gate’s output is active: a NOR of clk and an inverted copy pulses once per period, an XOR of clk and a non-inverted copy pulses at every edge. Two pulses per period put the duty cycle into every stage’s long path.

How to approach a storage-cell question

Recognize it by a latch or flip-flop drawn at gate or transistor level (a pass transistor, inverters, a feedback inverter, clocked devices) with “he is unable to write the latch”, “what has gone wrong?”, “how can this be fixed?”, “which nodes are dynamic?”, “add one transistor”; or by a small sequential design: “design a counter”, “a synchronous reset”, “the fastest clock”. FN19-9 and PS5-Q2 are the types; the lecturer’s flagged TSPC question is Variation 5.

The moves.

1. Name every internal node (X for the storage node) and, for each clock phase, list the devices that conduct onto it. A node with something pulling it both ways is a fight; a node with nothing conducting is dynamic.
2. For a write, find the writer (the driver and the switch) and the holder (the feedback device that is on in the old state). Estimate the fight as a resistor divider and compare the node’s voltage with the forward inverter’s switching threshold $V_M$VM​. Do both directions: writing a 1 through an NFET is weaker, and it stops at $V_{DD} - V_T$VT​.
3. Fix by weakening the holder, strengthening the writer, or, best, switching the holder off while writing (gated feedback).
4. For a design, write the state table, the next-state equations and the gates; choose the flip-flop (its edge, whether its output is inverted, static or dynamic); treat a synchronous reset as one more data input, with its own setup and hold.
5. For a dynamic cell, walk the stages through each phase and data sequence, find the state with two floating nodes, and hold the inner one with a half latch gated by the output.

The formulas.

• The write fight as a divider (Derive, Chapter 13 §7): $V_X \approx V_{DD}\,R_{down}/(R_{down} + R_{up})$Rup​), with an NFET of width $W$ pulling down as $R/W$R/W, a PFET pulling up, or an NFET pulling up, as $2R/W$2R/W; writable if $V_X$ crosses $V_M$VM​, which at $V_M = V_{DD}/2$ means the writer’s resistance is the smaller. Rough: devices as linear resistors.
• A flip-flop’s long and short paths (Memorize, Chapter 13 §11 and Chapter 14 §2): $t_{clk\to Q} + t_{logic} + t_{setup} \le T_{cycle}$ and $t_{clk\to Q} + t_{logic,min} \ge t_{hold}$thold​.
• The half latch (Memorize, Chapter 11 §9): about one tenth of the strength of the network that must overpower it.
• A dynamic node’s slowest clock (Derive, Chapter 15 §1): $t_{hold,max} = C_s\,\Delta V_{max}/I_{leak}$ and $f \ge 1/(2t_{hold,max})$1/(2thold,max​).

Decide on the way: which write direction is worse; whether a fix must hold at every corner (a ratio fix is a gamble, gated feedback is not); for a design, the flip-flop’s polarity and whether its output is inverted.

Traps. Strengthening the forward inverter, which does not fight. Widening only the pass NFET, which is in series with the driver. Checking only one write direction. Building a synchronous reset that clears the stored node directly (that is an asynchronous reset). Reading an inverting flip-flop’s output as Q.

Chapter 13’s static (a) and dynamic (b) D latches (Lecture12 @ 44:46, redrawn): a switch, then storage. FN19-9 is (a) with a driver inverter in front. Original figure ↗

3. FN19-9: a latch that cannot be written (10 points)

You need

The static D latch (Chapter 13 §6). A pass NFET on clk connects the latch’s input to its storage node X; X drives a forward inverter, and a feedback inverter drives the forward inverter’s output back onto X. While clk = 1 the switch writes X; while clk = 0 the loop of two inverters holds it. The feedback inverter has no clock: it is always on.

Device strength as resistance (Chapter 13 §7). A turned-on NFET of width $W$ (µm) pulling down acts like $R/W$R/W; a PFET pulling up like $2R/W$2R/W; devices in series add. An NFET pulling up is weak: it loses overdrive as its source rises, acts like about $2R/W$2R/W, and stops at $V_{DD} - V_T$VT​.

The switching threshold. An inverter’s output flips when its input crosses $V_M$VM​, about $V_{DD}/2$ for a balanced inverter.

Chapter 13’s write fight (Lecture12 @ 46:54, redrawn) on FN19-9’s circuit: the driver and the pass NFET pull X down while the feedback inverter’s PFET holds it up. Chapter 13’s D is the driver’s output and its $\overline{Q}$ is FN19-9’s Y. Original figure ↗

The question (FN19-9, p21, in the paper’s words). Joe Engineer is designing a simple pass-transistor latch as shown below.

FN19-9’s pass-transistor latch (p21, redrawn): A drives an inverter, then a pass NFET on clk, then the storage node (unnamed on the paper; this page calls it X), which drives the forward inverter to Y. The feedback inverter, always on, returns Y to X.

The exam’s own figure (FN19-9, p21)

FN19-9, p21 (source figure).

What went wrong, and the fix (10 points)

FN19-9, p21. He finds that he is unable to write the latch; that is, when clk is high, Y is not affected by the value of A. What has gone wrong? How can this be fixed? (10 points)

Hint

While clk is high, which devices conduct onto the node between the pass transistor and the forward inverter, and which way does each one pull?

What it asks. A diagnosis and a cure, in words, for a latch whose output ignores its input while it should be transparent. “Unable to write” and “Y is not affected by the value of A” say the storage node never changes enough to flip the forward inverter. The paper gives no sizes, so the answer is an argument; a divider estimate with typical sizes makes it concrete.

The idea. The feedback inverter is not clocked, so it is still on while clk is high, and it drives X toward the old value. To write, the driver inverter must pull X the other way through the pass NFET, and win: pull X past the forward inverter’s threshold $V_M$ before clk falls. The writer is two devices in series, one of them a pass NFET (which is a weak pull-up); the holder is one device. With ordinary sizes the holder wins, X stalls on the old side of $V_M$VM​, Y never changes, and when clk falls the loop restores the old value completely. Nothing is wrong with the logic: with clk high, $Y = \overline{\overline{A}} = A$A, as a latch should be.

Why this formula. Treat each conducting device as a resistor (Chapter 13 §7). While the fight lasts, the same current flows from $V_{DD}$ through the pull-up side, X and the pull-down side to ground, so X sits where the resistances divide the supply: $V_X = V_{DD}\,R_{down}/(R_{down} + R_{up})$Rup​). Writing a 0 into X (A = 1) puts the driver’s NFET and the pass NFET in series on the pull-down side against the feedback inverter’s PFET; writing a 1 (A = 0) puts the driver’s PFET and the pass NFET, pulling up, in series against the feedback inverter’s NFET. The write succeeds only if $V_X$ crosses $V_M = V_{DD}/2$VDD​/2, that is, if the writer’s resistance is the smaller. The estimate is rough, since transistors are not linear resistors, but it compares strengths, which is all the question needs. Two facts make writing a 1 the worse direction: the pass NFET pulls up weakly (about $2R/W$2R/W), and it cannot lift X above $V_{DD} - V_T$ at all. The tempting fixes that fail: a stronger forward inverter (it does not fight, its input draws no current), or a wider pass NFET alone (the driver is in series with it).

Chapter 13’s divider added for writing a 0: the feedback PFET ($2R/W_{fb}$2R/Wfb​) above X against the pass NFET and the driver’s NFET ($R/W_{pass} + R/W_{drv}$R/Wpass​+R/Wdrv​) below it. Original figure ↗

FN19-9

1. The logic is right. With clk = 1, A passes through two inverters to Y, so Y should equal A. The failure must be electrical: X does not move far enough.
2. Who drives X while clk = 1. Three things touch X: the pass NFET (from the driver), the feedback inverter’s output, and the forward inverter’s gate (which draws no current). So two outputs fight over X: the driver through the pass NFET, and the always-on feedback inverter.
3. Sizes for an estimate added. The paper gives none; take Chapter 13’s “normal” sizes: every inverter 2/1 (PFET 2 µm, NFET 1 µm) and a 1 µm pass NFET.
4. Writing a 0 into X (the latch holds X = 1, Y = 0; A rises). The pull-down is the driver’s NFET and the pass NFET in series, $R/1 + R/1 = 2R$2R; the pull-up is the feedback PFET, gate Y = 0, $2R/2 = R$R. So $V_X = V_{DD} \cdot 2R/(2R + R) = \tfrac23 V_{DD}$32​VDD​, above $V_M$VM​: X never gets low enough, and Y stays 0.
5. Writing a 1 into X (the latch holds X = 0, Y = 1; A falls). The pull-up is the driver’s PFET, $2R/2 = R$R, in series with the pass NFET pulling up, $2R/1 = 2R$2R: $3R$3R. The pull-down is the feedback NFET, gate Y = 1, $R/1 = R$R. So $V_X = V_{DD} \cdot R/(R + 3R) = \tfrac14 V_{DD}$41​VDD​, far below $V_M$VM​: worse. And even with no fight the pass NFET could lift X only to $V_{DD} - V_T$ (for example, with this guide’s values $V_{DD} = 1.0$ V and $V_T = 0.3$ V, only to 0.7 V).
6. When clk falls, the pass NFET turns off and the feedback inverter pulls X back to its full old level. Y never follows A: exactly what Joe sees.
7. Fix 1: weaken the feedback inverter. Because the holder must lose in both directions: writing a 0 needs $2R/W_{fbp} > 2R$2R, a feedback PFET narrower than 1 µm; writing a 1 needs $R/W_{fbn} > 3R$3R, a feedback NFET narrower than 1/3 µm. Narrower than a minimum device, so in practice it is made long, or with a series device, as Chapter 11’s half latch is. Chapter 13’s 0.5/0.25 µm feedback inverter writes a 0 at $\tfrac13 V_{DD}$ and a 1 at $0.571\,V_{DD}$0.571VDD​: barely.
8. Fix 2: strengthen the write path. A wider driver, and a transmission gate instead of the lone pass NFET: its PFET pulls X up strongly and all the way to $V_{DD}$VDD​. This helps, but it is still a ratio: whether it wins depends on the sizes (Variation 6 shows a transmission gate alone is not enough against a 2/1 feedback inverter).
9. Fix 3, the robust one: gate the feedback. Put a second switch in the loop, on $\overline{\mathrm{clk}}$clk, so that the feedback is cut while clk = 1 and reconnected while clk = 0; make both switches transmission gates (Chapter 13 §8). Now nothing fights the write in either direction, full levels pass both ways, and no ratio has to hold at every corner. This is the standard-cell latch, at the cost of a few transistors.

The cure (Chapter 13, Lecture12 @ 48:35, redrawn): the input transmission gate conducts while clk = 1, the feedback transmission gate while clk = 0, so nothing fights the write. Original figure ↗

Check. Remove the feedback inverter altogether and the circuit becomes Chapter 13’s dynamic latch, which writes with no fight at all: so the feedback inverter, and nothing else, is what stops the write. The estimate also agrees with the lecture’s own words, given with no numbers: the write path’s NFET “has to overpower the PFET of this feedback path” (Lecture12, 44:43), or the latch “might not be writable” (45:19); and it agrees with Chapter 11’s half latch, a keeper made weak, about a tenth of the pull-down’s strength, for the same reason.

Answer: The feedback inverter is always on, so while clk is high it fights the write; the driver inverter through the pass NFET is too weak to pull the storage node past the forward inverter’s threshold, so Y keeps its old value and the loop restores it when clk falls. Writing a 1 is the worse case: the pass NFET pulls up weakly and only to $V_{DD} - V_T$VT​. Fixes: make the feedback inverter weak (narrow or long, about a tenth of the write path’s strength); strengthen the driver and use a transmission gate; or, best, gate the feedback with $\overline{\mathrm{clk}}$ (a clocked inverter or a transmission gate in the loop), so nothing fights the write.

Remember. An always-on feedback device must be overpowered by the write path, in both directions; the cure that does not depend on sizes is to switch the feedback off while writing.

The answer key agrees

FN19 has no official key. The unofficial proposed solution names the same cause (the always-on feedback inverter fights the write, made worse by the NFET’s degraded high) and the same fixes: a weak keeper or stronger write path, or, more robustly, clocked feedback through transmission gates. It adds that a transmission gate alone does not guarantee a write against a strong feedback inverter, which Variation 6 checks with numbers.

4. PS5-Q2: a two-bit counter with a synchronous reset

You need

An edge-triggered flip-flop (Chapter 13 §10). Two latches in a row on opposite clock phases. The flip-flop samples D when its master closes and shows it at Q when its slave opens, both at one clock edge. With the master transparent while clk = 0 and the slave while clk = 1, that edge is clk’s rising edge (Chapter 13’s drawing has the phases the other way round, a falling-edge flip-flop). A static master–slave flip-flop with gated feedback gives both Q and $\overline{Q}$Q​, and holds its state however slowly the clock runs.

Chapter 13’s master–slave flip-flop (redrawn from Lecture12): two latches on opposite phases. Swap clk and $\overline{\mathrm{clk}}$ for a rising-edge flip-flop. Original figure ↗

The flip-flop’s timing (Chapter 13 §3, §11). D must be stable from $t_{setup}$ before the edge until $t_{hold}$ after it; Q changes $t_{clk\to Q}$ after the edge. A path from one flip-flop’s output, through logic, to another’s input must fit in a cycle: $t_{clk\to Q} + t_{logic} + t_{setup} \le T_{cycle}$ (the long path), and must not change D too soon after the edge: $t_{clk\to Q} + t_{logic,min} \ge t_{hold}$ (the short path, here with one clock and no skew).

Counting in binary (Chapter 15 §11). Adding 1 to $Q_1Q_0$ flips $Q_0$ always, and flips $Q_1$ when the carry out of bit 0 is 1, that is when $Q_0 = 1$1.

The question (PS5-Q2, p3, in the handout’s words). This is a small design problem. Design a two-bit wrap-around counter. The counter counts from “00” to “11” and then begins again at “00.” The systems takes as input a single clock and a synchronous input reset which resets the counter back to “00” when active. You may assume that reset arrives 20 psec after the rising edge of the clock. The clock is 50% duty cycle with 20-psec rise and fall times. The outputs are the two bits of the counter. Design your circuit for the fastest clock frequency possible and verify this maximum frequency of operation with Spectre. You do not have to layout your design.

The problem set gives no points and no figure. The Spectre search is beyond a written exam and is left out (the plan’s scope): the two parts below are the logic and the reset’s timing, which a final could ask on paper. The state diagram is drawn from the words.

PS5-Q2’s counter as a state diagram added, drawn from the handout’s words: the states are $Q_1Q_0$Q1​Q0​, and R is the handout’s reset. With reset low ($\overline{R}$R) each rising clock edge counts 00 → 01 → 10 → 11 → 00; with reset high ($R$R) every state goes to 00.

Part (a): the counter’s logic

PS5-Q2, p3 (the logic). Design a two-bit wrap-around counter. The counter counts from “00” to “11” and then begins again at “00.” […] a synchronous input reset which resets the counter back to “00” when active.

Hint

Counting is adding 1. Which bit flips every cycle, and when does the other one flip?

What it asks. A circuit: two flip-flops holding $Q_1Q_0$ and the logic that computes their next values, so that each rising clock edge moves the count one step, 00 → 01 → 10 → 11 → 00, and a high reset sends it to 00 at the next edge instead. “Synchronous” is the word that sets the method: the reset acts through the flip-flops’ D inputs, at a clock edge, like any other data; it never reaches into the stored nodes.

The idea. A counter is a state machine whose state is the count. Write the state table (present state and reset → next state), read off one Boolean equation per bit, add the reset as an AND with $\overline{\mathrm{reset}}$reset, then turn the equations into the fewest gate levels, since the problem asks for the fastest clock. The flip-flops are two rising-edge static flip-flops on the one clock.

Why this formula. The equations come from binary addition, $Q^+ = Q + 1 \bmod 4$4. Adding 1 to the low bit always flips it: $Q_0^+ = \overline{Q_0}$Q0​​. The high bit takes the carry out of the low bit, which is $Q_0$Q0​: it flips exactly when $Q_0 = 1$1, so $Q_1^+ = Q_1 \oplus Q_0$Q0​. From 11 both bits flip, to 00: the wrap-around comes for free, with no extra term. A synchronous reset forces the next state to 00 whatever the present state, so each bit is ANDed with $\overline{\mathrm{reset}}$reset. For the gates, De Morgan does the work: $\overline{Q_0}\cdot\overline{\mathrm{reset}}$ is $\text{NOR}(Q_0, \mathrm{reset})$NOR(Q0​,reset), and $(Q_1 \oplus Q_0)\cdot\overline{\mathrm{reset}}$ is $\text{NOR}(\text{XNOR}(Q_1, Q_0), \mathrm{reset})$NOR(XNOR(Q1​,Q0​),reset). Why not a reset that clears the flip-flops directly? That would be asynchronous: it would act the moment reset arrives, 20 ps after an edge, in the middle of a cycle, which is not what “synchronous” asks for.

PS5-Q2(a)

1. The state table. Because the count is the state, list each present state with reset low and high:

   $Q_1Q_0$	next, reset = 0	next, reset = 1
   00	01	00
   01	10	00
   10	11	00
   11	00	00

2. Bit 0. It flips every cycle: $Q_0^+ = \overline{Q_0}$Q0​​; with the reset, $D_0 = \overline{Q_0}\cdot\overline{\mathrm{reset}} = \text{NOR}(Q_0, \mathrm{reset})$NOR(Q0​,reset). One NOR2.

3. Bit 1. It flips when $Q_0 = 1$1: $Q_1^+ = Q_1 \oplus Q_0$Q0​; with the reset, $D_1 = (Q_1 \oplus Q_0)\cdot\overline{\mathrm{reset}} = \text{NOR}(\text{XNOR}(Q_1, Q_0), \mathrm{reset})$NOR(XNOR(Q1​,Q0​),reset). An XNOR2 and a NOR2.

4. One gate level for bit 1 (for speed). Because the flip-flops give both $Q$ and $\overline{Q}$Q​, write $\overline{D_1} = \mathrm{reset} + Q_1Q_0 + \overline{Q_1}\,\overline{Q_0}$ and build $D_1$ as one complementary gate: a pull-down of reset in parallel with ($Q_1$Q1​ in series with $Q_0$Q0​) and ($\overline{Q_1}$Q1​​ in series with $\overline{Q_0}$Q0​​), and its dual as the pull-up. One stage instead of two, at the cost of a three-high PFET stack.

5. The flip-flops. Two rising-edge static master–slave flip-flops on the single clock, $Q_1$ and $Q_0$ as the outputs, $Q$ and $\overline{Q}$ both used by the logic. Static, so the counter keeps its state at any clock speed; a dynamic or TSPC flip-flop would be faster but would add a minimum frequency and, for TSPC, an inverted output (Variation 5).

PS5-Q2’s counter added: two rising-edge flip-flops on one clock, with R for reset. $D_0 = \text{NOR}(Q_0, R)$ and $D_1 = \text{NOR}(\text{XNOR}(Q_1, Q_0), R)$NOR(XNOR(Q1​,Q0​),R), so a high reset loads 00 at the next edge.

Check. Run the equations from 00 with reset low: $Q_0$ goes 0, 1, 0, 1, 0 and $Q_1$ takes $Q_1 \oplus Q_0$ each time: 00 → 01 → 10 → 11 → 00 ✓. With reset high, both NORs have a 1 on an input and give 0, so every state goes to 00 ✓. The single complex gate of step 4 agrees with the two-gate form on all eight rows of ($Q_1$Q1​, $Q_0$Q0​, reset); this page’s test checks all eight.

Answer: $D_0 = \text{NOR}(Q_0, \mathrm{reset})$NOR(Q0​,reset), $D_1 = \text{NOR}(\text{XNOR}(Q_1, Q_0), \mathrm{reset})$ (or one complex gate, $D_1 = \overline{\mathrm{reset} + Q_1Q_0 + \overline{Q_1}\,\overline{Q_0}}$reset+Q1​Q0​+Q1​​Q0​​​), feeding two rising-edge static flip-flops on the one clock.

Remember. A binary counter is “flip bit 0, flip bit $k$ when all lower bits are 1”; a synchronous reset is one more input to each bit’s logic, ANDed in as its complement.

The answer key agrees

PS5 has no official key. The agent-written solution in the problem set’s folder (a cross-check only) has the same equations and the same gates, $D_0 = \text{NOR}(R, Q_0)$ and $D_1 = \text{NOR}(R, \text{XNOR}(Q_1, Q_0))$NOR(R,XNOR(Q1​,Q0​)), with static master–slave flip-flops as its baseline.

Part (b): the reset and the clock

PS5-Q2, p3 (the timing). You may assume that reset arrives 20 psec after the rising edge of the clock. The clock is 50% duty cycle with 20-psec rise and fall times. […] Design your circuit for the fastest clock frequency possible […].

Hint

The reset is just another data input, one that changes 20 ps after each edge. Which edge does it miss, and which one must it make?

What it asks. When the reset takes effect, what timing it must meet, and what limits the clock. The handout’s numbers are the reset’s arrival, 20 ps after the rising edge, and the clock’s shape. It gives no device delays (Spectre was to find them), so the frequency below uses illustrative delays, stated as such; the method is what a written exam would test.

The idea. A reset that changes 20 ps after an edge behaves exactly like the output of a flip-flop with a 20 ps clock-to-Q delay: it is launched at one edge and captured at the next. So it must be steady through the current edge’s hold window (it is too late for that edge, which must not see it), and it must reach the flip-flops’ D inputs a setup time before the next edge. The fastest clock is set by the slowest of the three paths into a D input: the counter’s own two loops and the reset’s path.

Why this formula. Each path into a flip-flop obeys the long-path rule $t_{start} + t_{logic} + t_{setup} \le T_{cycle}$Tcycle​, where $t_{start}$ is when the signal leaves after the edge: $t_{clk\to Q}$ for the counter’s bits, 20 ps for reset. Each also obeys the short-path rule $t_{start} + t_{logic,min} \ge t_{hold}$thold​, with no skew because one clock drives both flip-flops. Why the reset misses the current edge: if reset reached D within the flip-flops’ hold time after the edge, the edge’s sample would be corrupted, so the design needs $20\,\mathrm{ps} + t_{NOR,min} \ge t_{hold}$thold​, which holds for any ordinary flip-flop. The tempting error is to think a reset “arriving after the edge” acts at that edge: then the count would change mid-cycle, which a synchronous design never does.

Part (a)‘s counter added: bit 1’s path runs through the XNOR and a NOR, bit 0’s through one NOR, and R (reset) enters both NORs directly. Original figure ↑

PS5-Q2(b)

1. When the reset acts. Because it is sampled like data: reset rises 20 ps after edge $k$k; edge $k$ has already sampled the old reset, so the counter takes its normal step there. The NORs see reset at once, D goes to 00, and edge $k+1$ loads 00, which appears $t_{clk\to Q}$ after edge $k+1$1. While reset stays high, every edge loads 00; after it falls (20 ps after some edge), counting resumes at the following edge, from 01.
2. The illustrative delays added. For example, with this guide’s values (the handout gives none): $t_{clk\to Q} = 60$ ps, $t_{setup} = 40$ ps, $t_{hold} = 15$ ps; a NOR2 35 ps, an XNOR2 60 ps.
3. The three paths. Bit 1: $60 + 60 + 35 + 40 = 195$ ps. Bit 0: $60 + 35 + 40 = 135$ ps. Reset: $20 + 35 + 40 = 95$ ps. Because the clock must accommodate the slowest: bit 1 is critical, $T_{cycle} \ge 195$ ps, about 5.13 GHz. The reset is not, because it leaves 40 ps before the flip-flops’ outputs do.
4. Speeding up bit 1. Because bit 1’s two gate levels set the clock, merge them into the one complex gate of part (a), for example 55 ps: $60 + 55 + 40 = 155$ ps, about 6.45 GHz. Bit 0 (135 ps) is now close behind.
5. The hold checks. The reset: $20 + 35 = 55$ ps after the edge, against $t_{hold} = 15$ ps, a 40 ps margin. The counter’s own shortest loop, $Q_0$ through the NOR: $60 + 35 = 95$ ps, an 80 ps margin. With one clock and no skew, hold is safe.
6. The clock’s shape. At a 50% duty cycle each latch of a master–slave flip-flop is transparent for half the period, and at $T = 155$ ps a half period is 77.5 ps, of which the 20 ps edges take a quarter. The clock waveform itself, not only the logic, starts to limit the frequency here: that is what the Spectre search would settle.

PS5-Q2’s counter under a reset pattern added, computed from the next-state equations, with R (reset) changing just after an edge (the handout’s 20 ps, drawn as 0.02 of a period) and $Q_1Q_0$ a little after each edge. The state before edge 0 is unknown (hatched). R rising after edge 5 leaves edge 5’s step alone; edge 6 is the first to see it and loads 00, edge 7 again 00, and edge 8 counts on to 01.

Check. Walk the pattern of the timing figure through the equations: reset high until 20 ps after edge 0, low until 20 ps after edge 5, high until 20 ps after edge 7. Edge 0 samples reset = 1: 00. Edges 1–5 count 01, 10, 11, 00, 01. Edge 6 is the first to see the second reset: 00, and edge 7 again 00. Edge 8 sees reset low: 01. The reset asserted after edge 5 left edge 5’s step alone and acted at edge 6, as step 1 says; this page’s test runs the same sequence. The paths also order sensibly: each ends in the same NOR and setup, so their differences are only their starts and first gates: bit 1’s XNOR (60 ps) against bit 0’s nothing, and $t_{clk\to Q}$ (60 ps) against the reset’s 20 ps.

Answer: The reset is sampled like data: asserted 20 ps after edge $k$k, it leaves edge $k$‘s step unchanged and loads 00 at edge $k+1$1. It must meet $20\,\mathrm{ps} + t_{NOR} + t_{setup} \le T_{cycle}$ and $20\,\mathrm{ps} + t_{NOR,min} \ge t_{hold}$thold​. The clock is limited by bit 1’s path, $t_{clk\to Q} + t_{XNOR} + t_{NOR} + t_{setup}$tsetup​: with the example delays 195 ps (5.13 GHz), or 155 ps (6.45 GHz) with bit 1’s logic merged into one gate.

Remember. Treat a synchronous input that arrives a fixed time after the edge as a flip-flop output with that clock-to-Q: it must meet the next edge’s setup and the current edge’s hold.

The answer key agrees

PS5 has no official key. The agent-written solution (a cross-check only) gives the same reset behaviour: an assertion 20 ps after edge $k$ leaves the state of edge $k$ and produces 00 at edge $k+1$1, with $T - 20$ ps available to the reset path; it gives no frequency, which it leaves to simulation.

Variations: storage cells

Two added variations added. Variation 5 is the question the lecturer flagged, “a very good exam question” (Lecture14, 27:02): half latches on the TSPC flip-flop, here made longer, with the flip-flop wired as PS5-Q2’s toggling bit and carried through to the half latch’s size and the slowest clock. Variation 6 gives Joe Engineer a transmission gate and asks, with numbers, whether that is enough.

Variation 5: half latches on a TSPC toggle flip-flop (added)

Variation 5: half latches on a TSPC toggle flip-flop

The question added. The TSPC flip-flop of Lecture 14 (Chapter 15 §6) has three stages. Stage 1: a PFET with gate D, a PFET with gate clk, and an NFET with gate D; output X. Stage 2: a PFET with gate clk from $V_{DD}$VDD​, and an NFET with gate X over an NFET with gate clk; output Y. Stage 3: a PFET with gate Y, an NFET with gate clk and an NFET with gate Y; output $\overline{Q}$Q​. Its output is wired straight back to D, to make bit 0 of a counter (no reset). Stage 2’s NFETs are 2 µm each, the minimum width is 0.4 µm, and a PFET has half an NFET’s strength at equal width. (a) On which edge does the bit change, and does it toggle? (b) With clk low on [0, 2), high on [2, 4), and so on, and $\overline{Q} = 1$ at the start, walk X, Y and $\overline{Q}$ through three cycles and find when two nodes float at once. (c) Add one transistor that removes that state, and say why it must be weak. (d) Size it by the one-tenth rule, using minimum-width devices. (e) $\overline{Q}$ floats while clk is low; it has 4 fF, leaks 0.8 nA, and is read correctly while it has drooped less than 0.1 V. What is the slowest clock? (f) The wiring changes D right after each edge. Is that a hold problem?

Chapter 15’s TSPC flip-flop (Lecture14 @ 27:24, redrawn), the circuit of this variation before its output is wired back to D: three stages on one clock, output $\overline{Q}$Q​. Original figure ↗

Hint

A node floats when neither of its networks conducts. In stage 1 while clk is high, what can still pull X, and in which direction?

What it asks. Six steps on one circuit: its function with the feedback wire, a walk through its clock phases, the lecturer’s half-latch question, the half latch’s size, the leakage limit on the clock, and a race. The unfamiliar part is the wiring: D is not an independent input but the flip-flop’s own output, so the data changes right after every edge, and that decides which states the flip-flop visits.

The idea. Walk the stages exactly as Chapter 15 does: in each phase, ask of each node whether its pull-up or its pull-down conducts. Stage 1 can only pull X down while clk is high (its clocked PFET is off); stage 2 can only pull Y down while clk is high and is precharged while clk is low; stage 3 inverts while clk is high and can only pull up while clk is low. With the output fed back, every edge that samples D = 1 is followed at once by D falling, which is the sequence that leaves X and Y both floating. A weak device that holds Y high, switched on by the output in exactly that state, removes it.

Why this formula. Four relations, each Chapter 15’s or Chapter 11’s.

• The function (Chapter 15 §6): $\overline{Q}^{\,+} = \overline{D}$ at each rising edge, a positive-edge, inverting flip-flop. With $D = \overline{Q}$Q​: $\overline{Q}^{\,+} = \overline{\overline{Q}}$Q​​, the bit flips at every edge. A designer who reads the output as Q and adds an inverter to make a toggle gets a bit that never changes.
• The half latch (Chapter 15 §5): the device that drives the floating inner node to the value it must keep (a PFET for a 1), gated by the output so that it is on exactly in the dangerous state.
• Its size (Chapter 11 §9): about one tenth of the strength of the network that must overpower it, because when Y has to discharge, stage 2 fights it until the output turns it off. Series devices add resistance, so two equal devices in series act like one of half the width.
• The slowest clock (Chapter 15 §1): a floating node droops by $I_{leak}t/C_s$Ileak​t/Cs​, so it holds for $t_{hold,max} = C_s\Delta V_{max}/I_{leak}$Cs​ΔVmax​/Ileak​; it floats for half a period at 50% duty, so $T_{cycle} \le 2t_{hold,max}$2thold,max​.

Variation 5

1. (a) The function. Because the flip-flop gives $\overline{Q}^{\,+} = \overline{D}$ at each rising edge and $D = \overline{Q}$Q​: the output toggles at every rising edge. It is a divide-by-two, bit 0 of a counter.
2. (b) clk low, [0, 2). $\overline{Q} = D = 1$1. Stage 1: the NFET with gate D is on, so X = 0, driven. Stage 2 precharges: Y = 1, driven. Stage 3: its PFET (gate Y = 1) and its clocked NFET are off, so $\overline{Q}$ floats at 1.
3. (b) Edge at 2. X = 0, so stage 2’s pull-down stays off and Y stays 1; stage 3 now inverts: $\overline{Q}$ falls to 0, driven. So D falls. In stage 1 the NFET turns off and the PFETs cannot conduct (the clocked one is off): X floats at 0. In stage 2 the precharge is off and the X-NFET is off: Y floats at 1. From 2 to 4, X and Y both float.
4. (b) clk low, [4, 6). D = 0, so stage 1 drives X = 1; Y is precharged, 1; $\overline{Q}$ floats at 0.
5. (b) Edge at 6. X = 1, so Y discharges to 0; stage 3’s PFET turns on: $\overline{Q}$ rises to 1, D rises, and stage 1’s NFET pulls X down to 0. Now Y’s pull-down is off again (X = 0) and its precharge is off: Y floats at 0, alone. From 6 to 8, one dynamic node.
6. (b) The pattern. [8, 10) repeats [0, 2), and the edge at 10 repeats the edge at 2: X and Y both float again on [10, 12). The two-node state comes in every other high phase, each time the bit falls from 1 to 0, so this counter visits it constantly.
7. (c) The half latch. In that state Y floats at 1 while $\overline{Q} = 0$0. A weak PFET from $V_{DD}$ to Y with its gate on $\overline{Q}$ is on exactly then and holds Y at 1, so only X floats. It must be weak because of the other edge (step 5): there $\overline{Q}$ is still 0 when Y must discharge, so the half latch is on and stage 2 must overpower it until $\overline{Q}$ rises and turns it off.
8. (d) Its size. Stage 2’s pull-down is two 2 µm NFETs in series: like one NFET of $1/(1/2 + 1/2) = 1$ µm. One tenth of that is a 0.1 µm NFET’s strength, and a PFET needs twice the width: 0.2 µm. That is below the 0.4 µm minimum, so use two minimum PFETs in series, which act like one of 0.2 µm: the one gated by $\overline{Q}$ at minimum size (it loads the output), the other with its gate tied to ground, always on (Chapter 11’s series device).
9. (e) The slowest clock. $t_{hold,max} = 4\,\mathrm{fF} \times 0.1\,\mathrm{V}/0.8\,\mathrm{nA} =$ 500 ns. Because $\overline{Q}$ floats for half of each period: $T_{cycle} \le 1\,\mu$s, so $f \ge$ 1 MHz. A clock stopped for testing or power saving loses the count.
10. (f) The race. D changes only when $\overline{Q}$ changes, and $\overline{Q}$ changes only after stage 2 has decided: at the edge at 2, Y never had to move, and D falling cannot raise X (its clocked PFET is off); at the edge at 6, D rises only because Y has already fallen far enough to switch stage 3. The feedback is self-timed, so no hold failure, provided Y falls well below stage 3’s threshold before X cuts the discharge off. The half latch slows that discharge, another reason it must be weak.

Variation 5(b)‘s walk added, computed from a switch-level model of the three stages with D wired to $\overline{Q}$Q​, ideal edges: $\overline{Q}$ toggles at each rising edge (2, 6, 10), and on [2, 4) and [10, 12), each time it falls, X and Y both float (shaded) unless a half latch holds Y.

Variation 5’s circuit with its answer to (c) and (d) added: Lecture 14’s TSPC flip-flop (Lecture14 @ 27:24) with $\overline{Q}$ wired back to D, stage 2’s NFETs 2 µm each, and the half latch on Y: two 0.4 µm PFETs in series from $V_{DD}$VDD​, the upper always on (gate to ground), the lower gated by $\overline{Q}$Q​. Widths in µm.

Check. The walk can be checked against Chapter 15’s table for the flip-flop, which lists the two-node state as “D was 1 at the edge, then fell to 0”: in the toggle wiring D falls right after every edge that samples a 1, so that row is visited at the edges at 2 and 10, and the row “D was 0 at the edge, then rose” (only Y dynamic) at the edge at 6 ✓. This page’s test runs a switch-level model of the three stages with D wired to $\overline{Q}$Q​: $\overline{Q}$ is 1, 0, 1, 0 after the edges; X and Y float together only on [2, 4) and [10, 12) without the half latch, and never with it. The size checks by resistance: two 0.4 µm PFETs in series, $2R/0.4 + 2R/0.4 = 10R$10R, against the stage-2 stack’s $R/2 + R/2 = R$R: one tenth ✓.

Answer: (a) Rising edge; it toggles. (b) X and Y both float on [2, 4) and [10, 12), every other high phase (whenever $\overline{Q}$ falls from 1 to 0); [6, 8) leaves only Y floating. (c) A weak PFET from $V_{DD}$ to Y, gate on $\overline{Q}$Q​; weak because stage 2 must overpower it whenever Y discharges. (d) 0.2 µm, built as two 0.4 µm PFETs in series. (e) $f \ge 1$ MHz. (f) No: the output, and so D, changes only after stage 2 has evaluated.

Remember. To place a half latch: walk the stages, find the phase and data sequence that leave two nodes floating, and hold the inner one at its value with a weak device gated by the output. An output fed back to the input chooses which sequences the circuit actually visits.

Variation 6: a transmission gate against an ungated feedback inverter (added)

Variation 6: a transmission gate against an ungated feedback inverter

The question added. Joe Engineer tries again. He keeps every inverter of FN19-9’s latch at 2/1 µm (driver, forward and feedback) and replaces the pass NFET by a transmission gate: an NFET of 1 µm on clk and a PFET of 2 µm on $\overline{\mathrm{clk}}$clk. Use the course’s resistor model: an NFET of width $W$ pulls down as $R/W$ and up as about $2R/W$2R/W; a PFET pulls up as $2R/W$ and down as about $4R/W$4R/W; $V_M = V_{DD}/2$VDD​/2. (a) Can he write a 0 now? A 1? (b) He shrinks the feedback inverter, keeping its 2:1 ratio (PFET $2k$2k, NFET $k$k). For a margin of $0.1\,V_{DD}$0.1VDD​, X reaching $0.4\,V_{DD}$ when writing a 0 and $0.6\,V_{DD}$ when writing a 1, how small must $k$ be? (c) Can he build it with a 0.4 µm minimum width? (d) How small would $k$ have to be in the original FN19-9 latch, with the lone 1 µm pass NFET? (e) Compare the transistor count with the gated-feedback standard cell, and say which he should use.

Variation 6’s latch added: FN19-9’s circuit with the pass NFET replaced by a transmission gate, an NFET of 1 µm on clk in parallel with a PFET of 2 µm on $\overline{\mathrm{clk}}$clk. Every inverter is 2/1 µm (PFET/NFET); the feedback inverter is still always on.

The write fight as a divider (Chapter 13 added): the writer’s series resistance against the holder’s. Original figure ↗

Hint

A transmission gate is two devices in parallel. Which one does most of the work when pulling X down, and which when pulling it up?

What it asks. Whether the transmission gate, which fixes the NFET’s weak high, also wins the fight; then the feedback size that makes the write work in both directions with a margin; then a comparison with the original latch and with the cure that removes the fight. The phrase “with a margin” turns a yes-or-no test into a sizing inequality.

The idea. A transmission gate helps both directions: in each, one of its devices is the strong one. But the write is still a ratio: the writer (driver plus gate, in series) against the holder (the feedback device that is on in the old state). Whether it wins depends on sizes, so the feedback inverter must be made weak enough, and the margin says how weak.

Why this formula. The divider of FN19-9: $V_X = V_{DD}\,R_{lower}/(R_{lower} + R_{upper})$Rupper​). Two more facts. Devices in parallel combine like resistors in parallel, $R_a R_b/(R_a + R_b)$Rb​), so the transmission gate’s resistance is that of its two devices together in each direction, each with its own strength for that direction (the course’s model, Chapter 11 §2). And a feedback inverter of width $k$ pulls with $R/k$ (its NFET, holding a 0) or $2R/2k = R/k$ (its PFET, holding a 1): the 2:1 ratio makes both the same. Setting the divider to the margin gives a closed form: writing against $R/k$ through a writer of resistance $R_w$ comes within $m\,V_{DD}$ of the new rail only if $k \le m/((1 - m)\,R_w/R)$m)Rw​/R), with $m = 0.4$ here. The model is rough, since devices are not linear resistors, which is exactly why a design adds a margin.

Variation 6

1. (a) The gate’s resistances. Pulling down: the NFET, $R/1 = R$R, in parallel with the PFET, $4R/2 = 2R$2R: $\tfrac23 R$32​R. Pulling up: the NFET, $2R/1 = 2R$2R, in parallel with the PFET, $2R/2 = R$R: also $\tfrac23 R$32​R.
2. (a) The write paths. Because the driver is in series with the gate: down, its NFET $R/1$ plus $\tfrac23 R$ is $\tfrac53 R$35​R; up, its PFET $2R/2 = R$ plus $\tfrac23 R$ is also $\tfrac53 R$35​R. The 2/1 feedback inverter holds with $R$ either way.
3. (a) The verdict. Writing a 0: $V_X = \tfrac53/(\tfrac53 + 1)\,V_{DD} = 0.625\,V_{DD}$0.625VDD​, above $V_M$VM​. Writing a 1: $V_X = 1/(1 + \tfrac53)\,V_{DD} = 0.375\,V_{DD}$0.375VDD​, below $V_M$VM​. Neither works: the transmission gate alone does not beat a full-size feedback inverter.
4. (b) The margin. Writing a 0, X must fall to $0.4\,V_{DD}$0.4VDD​: $\tfrac53/(\tfrac53 + 1/k) \le 0.4$0.4, so $k \le 0.4/(0.6 \times \tfrac53) =$ 0.4 µm. Writing a 1, X must rise to $0.6\,V_{DD}$ against the feedback NFET’s $R/k$R/k: the same writer resistance gives the same bound, $k \le 0.4$ µm.
5. (c) Buildable. A 0.8/0.4 µm feedback inverter is exactly minimum width: yes, with no margin to spare on the sizing.
6. (d) The original latch. Writing a 0 its path is $2R$2R: $k \le 0.4/(0.6 \times 2) =$ 0.333 µm. Writing a 1 it is $3R$ (the weak NFET pull-up): $k \le 0.4/(0.6 \times 3) =$ 0.222 µm, about half the minimum width, so a long or series feedback device would be needed. The transmission gate’s real gain is in the write-1 direction.
7. (e) The count. The transmission-gate input with ungated feedback: $2 + 4 =$ 6 transistors (plus the driver). The gated-feedback standard cell: $2 + 2 + 4 =$ 8, 10 with an output inverter. Two more transistors buy a write with no fight in either direction, no fight current, full levels, and no ratio that a slow corner can break. He should use the standard cell.

Check. At $k = 0.4$ µm the divider gives exactly the targets: writing a 0, $\tfrac53/(\tfrac53 + 2.5) = 0.4$ ✓; writing a 1, $2.5/(2.5 + \tfrac53) = 0.6$ ✓. The two directions come out equal because the writer is symmetric ($\tfrac53 R$35​R both ways) and the 2:1 feedback inverter is too; in the original latch the writer is not ($2R$2R down, $3R$ up), and the bounds differ. As a limit, with no feedback at all ($k \to 0$k→0) both directions reach the rail, as Chapter 13’s dynamic latch does.

Answer: (a) No: X reaches only $0.625\,V_{DD}$ writing a 0 and $0.375\,V_{DD}$ writing a 1. (b) $k \le 0.4$ µm in both directions: a 0.8/0.4 µm feedback inverter. (c) Yes, at minimum width. (d) $k \le 0.333$ µm (write 0) and 0.222 µm (write 1): below minimum. (e) 6 transistors against 8 (10 with an output inverter); the gated cell removes the fight and is the one to use.

Remember. A stronger switch narrows the fight but does not end it: an always-on feedback inverter must still be sized weak, for both directions, with margin. Gating the feedback ends it for two transistors.