FS2. Clocks, pulsed latches and storage cells: the exam way

This is the exam way of FS2: each part as you would write it on the paper, with what to recognize, the lines to write, what to draw, the trap to watch and the answer. Every part keeps the anchor it has on FS2, so the switch at the top of the page takes you to the same part’s full solution. The methods are three cards of the playbook: clock generation, pulsed latches and storage cells. The six harder variations stay on FS2 only, at the end of each family: clock generation, pulsed latches and storage cells.

The clock. The past finals gave 180 minutes: FN12 for 200 points, 0.9 min a point, and FN19 for 250 points, 0.72 min a point. So FN12-7a’s 15-point sketch has about 14 minutes, and a 10-point FN19 part about 7. (The midterms ran at 30 s a point.) PS5 is a problem set and gives no points: each of its two parts is budgeted here by analogy, as a 10-point design part on a final, about 8 minutes.

1. FN12-7: a local clock generator (15 points of 30)

FN12-7, p10. Consider the “local clock generator” circuit shown below, used to generate two clock phases locally from a single-wire global clock. The delay blocks (labelled with $\Delta_1$ and $\Delta_2$ ) could be implemented with an even number of inverters (for example).

Top left, a box CG with input φ and outputs φ1 and φ2, then an equivalence sign and its circuit: φ goes to the top input of an upper NOR whose output is φ1, and through a downward-pointing inverter to the bottom input of a lower NOR whose output is φ2. Two delay boxes sit between the NORs: Δ1 takes φ2 and drives the upper NOR's second input; Δ2 takes φ1 and drives the lower NOR's second input. Below, a timing diagram: φ low, then three high pulses of half a period; the φ1 and φ2 rows are empty. — FN12-7’s local clock generator (p10, redrawn): CG ≡ two NORs and an inverter. Each delay block takes the **other** phase: $\Delta_1$ takes φ2 into φ1’s NOR, $\Delta_2$ takes φ1 into φ2’s NOR. Below, the paper’s φ with empty rows for φ1 and φ2.

The exam’s own figure (FN12-7, p10)

FN12-7's figure: a box CG with input φ and outputs φ1 and φ2, equivalent to a circuit in which φ feeds the top input of an upper NOR whose output is φ1, and through an inverter the bottom input of a lower NOR whose output is φ2; a delay Δ1 takes φ2 and feeds the upper NOR's second input; a delay Δ2 takes φ1 and feeds the lower NOR's second input. Handwritten 1/0 notes from the key are on the wires. — FN12-7, p10 (source figure). The handwritten 1/0 notes on the wires are the key’s.

Part (a): sketch φ1 and φ2 (15 points)

FN12-7a, p10. Sketch the $\phi_1$ and $\phi_2$ waveforms for the $\phi$ waveform shown below. Ignore the gate delays of the inverter and NOR gates but indicate the $\Delta_1$ and $\Delta_2$ delays on your sketch. (15 points)

Hint

Each NOR goes high only when both its inputs are low. Right after φ rises, which input of φ2’s NOR is still high, and for how long?

Recognize. Clock generation: cross-coupled NORs with delay blocks, “sketch the waveforms … indicate the delays”. About 14 minutes (15 points at FN12’s 0.9 min a point); the walk takes five, the rest goes on a clean sketch.

On the paper.

$\phi_1 = \text{NOR}(\phi,\ \Delta_1(\phi_2))$ , $\phi_2 = \text{NOR}(\overline\phi,\ \Delta_2(\phi_1))$
NOR: any input 1 → 0 at once; 1 only when both inputs are 0
Start, φ = 0: $\overline\phi = 1$ → φ2 = 0 → φ1 = 1
φ ↑: φ1 ↓ at once; $\Delta_2(\phi_1)$ is still 1 for $\Delta_2$ → φ2 ↑ at $t_\uparrow + \Delta_2$
φ ↓: φ2 ↓ at once; $\Delta_1(\phi_2)$ is still 1 for $\Delta_1$ → φ1 ↑ at $t_\downarrow + \Delta_1$
Check: never both high (one NOR always has a 1 on its direct input); $\Delta \to 0$ gives φ1 = φ̄, φ2 = φ

Draw under the paper’s φ: φ1 low through each high pulse, φ2 high from $\Delta_2$ after each rising edge to the falling edge; φ2 low through each low stretch, φ1 high from $\Delta_1$ after each falling edge to the next rising edge. Label each gap after a rising edge $\Delta_2$ and each gap after a falling edge $\Delta_1$ .

Top, the generator: φ into an upper NOR whose output is φ1 and, through an inverter as φ-bar, into a lower NOR whose output is φ2; φ2 through Δ1 back to the upper NOR, φ1 through Δ2 to the lower NOR. Bottom, φ, φ1 and φ2: φ1 high while φ is low but starting Δ1 after φ falls; φ2 high while φ is high but starting Δ2 after φ rises. — What to draw (Chapter 14’s figure of the same circuit added, drawn with $\Delta_1 = 0.10\,T$ and $\Delta_2 = 0.06\,T$ ): each phase falls with an edge of φ and rises a delay after the other phase has fallen. Original figure ↗

Watch out. Only the rising edges wait: a phase is not a delayed copy of φ or φ̄, because it falls at once. And $\Delta_1$ sits after φ’s falling edge (it delays φ2, the phase φ1 waits for); swapping the labels loses the marks for them.

Answer: φ2 is high from $\Delta_2$ after each rising edge of φ to the falling edge; φ1 is high from $\Delta_1$ after each falling edge to the next rising edge. Both phases are low for $\Delta_2$ after every rising edge and for $\Delta_1$ after every falling edge.

Full solution

2. FN19-5: a clock chopper and a runt pulse (22 points)

FN19-5, p11. Consider the clock chopper circuit shown below. The delay block (labelled $\Delta$ ) can be implemented with an even number of inverters.

(a) A box CC with input φ and output φ-chopped, equivalent to a circuit where φ goes straight to a NOR's top input and, through an inverter and a delay box Δ, to its bottom input; the NOR's output is φ-chopped. (b) CLK1 enters a box φ CC whose output clocks a latch; D enters the latch from the left, its Q goes through a box labelled combinational logic to the D of a second latch, clocked by a second φ CC box from CLK2; the second latch's Q leaves to the right. — FN19-5’s figures (p11, redrawn). (a) The clock chopper: CC ≡ a NOR of φ and φ inverted and delayed by Δ. (b) Two clock-chopped latches, each clocked by its own chopper, from CLK1 and CLK2, with combinational logic between them.

The exam’s own figures (FN19-5, p11)

A box CC with input φ and output φ_chopped, equivalent to φ into a NOR directly and through an inverter and a delay Δ. — FN19-5, p11: the clock chopper.

CLK1 and CLK2 each drive a φ CC block clocking a latch; the left latch's Q passes through combinational logic to the right latch's D. — FN19-5, p11: the two clock-chopped latches.

Part (a): the widest pulse (10 points)

FN19-5a, p11. Consider two clock-chopped flip-flops separated by combinational logic as shown below. Assuming that the combinational logic represents a fixed delay of 200 psec and there is skew between CLK1 and CLK2 such that CLK2 arrives 100 psec earlier than CLK1, what is the maximum value $\Delta$ (the pulse width of the chopped clock) can have and still ensure correct functionality? Assume that the latches have a hold time of 50 psec on their closed clock edge. (10 points)

Hint

While its pulse is high, the receiving latch is still taking in data. When does that pulse close, if CLK2 is 100 ps early, and when does the new data arrive?

Recognize. Pulsed latches: “maximum value Δ … hold time … on their closed clock edge” is pulsed hold. About 7 minutes (10 points at FN19’s 0.72 min a point).

On the paper.

Chopper = NOR(φ, φ̄ delayed by Δ): a pulse Δ wide after each falling edge
Identical choppers, so the pulses are offset by the skew: $\delta = -100$ ps (CLK2 early)
No $t_{clk\to Q}$ given: take it as 0 (say so)
Hold at the closing edge: $t_{clk\to Q} + t_{logic} \ge \delta + \Delta + t_{hold}$
$0 + 200 \ge -100 + \Delta + 50$
$\Delta \le 250$ ps
Check: with no skew, $200 - 50 = 150$ ps; the early CLK2 buys exactly its 100 ps

Watch out. CLK2 early makes $\delta$ negative: adding the 100 ps as a late skew gives 50 ps. Hold counts from the pulse’s closing edge, not its opening.

Answer: $\Delta_{max} = 250$ ps (with $t_{clk\to Q} = 0$ , which the paper does not give).

Full solution

Part (b): the chopped clock through a loaded inverter (12 points)

FN19-5b, p12. Assume that this chopped clock with the pulse width calculated in (a) is driven from an inverter with a load capacitance of 200 fF. The inverter is sized $4\ \mu\mathrm{m}\,/\,2\ \mu\mathrm{m}$ in a technology with a FO1 delay of $\tau_1=25\ \mathrm{psec}$ . Assume a gate capacitance of $2\ \mathrm{fF}/\mu\mathrm{m}$ . Sketch the waveform of the clock as received by the latch. What will be the “height” of the pulse? What problems might this present? (12 points)

Hint

How long does this inverter take to drive 200 fF, and is the 250 ps pulse longer or shorter than that?

Recognize. Pulsed latches, the distribution move: a driver, a load and “the height of the pulse” mean a runt. About 9 minutes (12 points at 0.72 min a point).

On the paper.

$C_{in} = (4 + 2)\,\mu\mathrm{m} \times 2\,\mathrm{fF/\mu m} = 12$ fF
$t_d = \tau_1 C_L/C_{in} = 25 \times 200/12 = 416.7$ ps (50% point)
$t_{pulse}/t_d = 250/416.7 = 0.6 < 1$ : a runt
RC with its 50% point at $t_d$ : $\tau_{RC} = t_d/\ln 2 = 601$ ps
Height $= 1 - 2^{-0.6} = 1 - 0.660 = 0.34\,V_{DD}$
Shape: from 0, rises as $1 - 2^{-t/t_d}$ for 250 ps to $0.34\,V_{DD}$ , then decays with $\tau_{RC} \approx 600$ ps
Never crosses $V_{DD}/2$ : the latch may never open, or opens weakly and late
(a) caps the pulse, so speed the driver: $t_d \le 250$ ps needs $C_{in} \ge 25 \times 200/250 = 20$ fF (10 µm) for just $V_{DD}/2$ , about 66 fF (33 µm) for 90%; or chop at the latch

Draw the dashed 250 ps command pulse and, under it, the rounded bump that peaks at $0.34\,V_{DD}$ at 250 ps and decays; mark $V_{DD}/2$ to show it is never reached.

A plot of v over V_DD against time in ps. A dashed pulse goes from 0 to 1 at t = 0 and back to 0 at 250 ps. A thick solid curve starts at 0, rises during the pulse to 0.34 at 250 ps, then decays slowly toward 0, reaching about 0.04 at 1500 ps. A dotted line at 0.5 marks V_DD/2; the solid curve stays below it. — What to draw (FS2’s computed runt added, $t_d = 416.7$ ps, 250 ps pulse, 50%-point RC model): it peaks at $0.340\,V_{DD}$ and never reaches $V_{DD}/2$ . Original figure ↗

Watch out. Taking $t_d$ itself as the time constant gives $1 - e^{-0.6} = 0.451$ (the unofficial 2019 solution’s boxed number); the course’s delay is the 50% point, so $\tau_{RC} = t_d/\ln 2$ . Write your convention down. Widening the pulse is not a cure: (a) caps it.

Answer: The latch receives a rounded positive runt about $0.34\,V_{DD}$ high, because the driver’s delay into 200 fF (417 ps) is longer than the 250 ps pulse. It never reaches $V_{DD}/2$ , so the latch may not open at all, or opens weakly and unpredictably. Fix it with a faster driver (10 µm only just reaches $V_{DD}/2$ ; about 33 µm reaches 90%), or a chopper beside the latch.

Full solution

3. FN19-9: a latch that cannot be written (10 points)

FN19-9, p21. Joe Engineer is designing a simple pass-transistor latch as shown below.

A into an inverter, then an NFET drawn horizontally with its gate, clk, on top, into a node. The node drives an inverter whose output is Y. Above, a second inverter pointing left takes Y and drives the node. — FN19-9’s pass-transistor latch (p21, redrawn): A drives an inverter, then a pass NFET on clk, then the storage node (unnamed on the paper; called X here), which drives the forward inverter to Y. The feedback inverter, always on, returns Y to X.

The exam’s own figure (FN19-9, p21)

A into an inverter, a clk-gated NFET pass device, an inverter to Y, and a feedback inverter from Y back to the internal node. — FN19-9, p21 (source figure).

What went wrong, and the fix (10 points)

FN19-9, p21. He finds that he is unable to write the latch; that is, when clk is high, Y is not affected by the value of A. What has gone wrong? How can this be fixed? (10 points)

Hint

While clk is high, which devices conduct onto the node between the pass transistor and the forward inverter, and which way does each one pull?

Recognize. Storage cells: a latch at transistor level and “unable to write … what has gone wrong? how can this be fixed?” is a write fight. About 7 minutes (10 points at 0.72 min a point); the paper gives no sizes, so the numbers in lines 5–6 are an illustration you label as such.

On the paper.

clk = 1: $Y = \overline{\overline A} = A$ , so the logic is right; the fault is electrical
The feedback inverter has no clock: on while writing, it holds X at the old value
Writer: driver + pass NFET in series; holder: one feedback device
Divider: $V_X = V_{DD}R_{down}/(R_{down} + R_{up})$ ; writes only if $V_X$ crosses $V_M \approx V_{DD}/2$
For example, inverters 2/1, pass 1 µm. Write 0: down $R + R = 2R$ , up $2R/2 = R$ → $V_X = \tfrac23 V_{DD}$ ✗
Write 1: up $R + 2R/1 = 3R$ (NFET pulls up weakly), down $R$ → $V_X = \tfrac14 V_{DD}$ ✗, worse; and X stops at $V_{DD} - V_T$
clk ↓: the loop restores the old value; Y never follows A
Fix 1: feedback weaker than the writer both ways: PFET < 1 µm, NFET < 1/3 µm, so it is made long
Fix 2: stronger driver and a transmission gate (still a ratio)
Fix 3, robust: gate the feedback with $\overline{\mathrm{clk}}$ (a transmission gate or a clocked inverter in the loop)

Draw fix 3: the input switch on clk and a second switch on $\overline{\mathrm{clk}}$ in the feedback loop, both transmission gates.

D through a transmission gate on clk into X, an inverter to Q-bar, and the feedback inverter returning through a second transmission gate on clk-bar into X. — What to draw for fix 3 (Chapter 13, Lecture12 @ 48:35, redrawn): the feedback is cut while clk = 1, so nothing fights the write. Original figure ↗

Watch out. A stronger forward inverter does nothing: its gate draws no current. Check both directions: writing a 1 through an NFET is the worse one.

Answer: The always-on feedback inverter fights the write: the driver through the pass NFET cannot pull the storage node past the forward inverter’s threshold, so Y keeps its old value, and the loop restores it when clk falls. Writing a 1 is worse (the NFET pulls up weakly and only to $V_{DD} - V_T$ ). Fix it with a weak feedback inverter, a stronger driver with a transmission gate, or, best, feedback gated by $\overline{\mathrm{clk}}$ so nothing fights the write.

Full solution

4. PS5-Q2: a two-bit counter with a synchronous reset

PS5-Q2, p3. This is a small design problem. Design a two-bit wrap-around counter. The counter counts from “00” to “11” and then begins again at “00.” The systems takes as input a single clock and a synchronous input reset which resets the counter back to “00” when active. You may assume that reset arrives 20 psec after the rising edge of the clock. The clock is 50% duty cycle with 20-psec rise and fall times. The outputs are the two bits of the counter. Design your circuit for the fastest clock frequency possible and verify this maximum frequency of operation with Spectre. You do not have to layout your design.

The handout gives no points and no figure, and the Spectre search is beyond a written exam: the two parts below are the logic and the reset’s timing. The state diagram is drawn from the words.

Four circles at the corners of a rectangle: 00 top left, 01 top right, 10 bottom right, 11 bottom left. Arrows labelled R-bar run clockwise 00 to 01 to 10 to 11 and back to 00. Arrows labelled R run from 01, 10 and 11 to 00, and a loop labelled R returns 00 to itself. — PS5-Q2’s counter as a state diagram added, drawn from the handout’s words: the states are $Q_1Q_0$ , and R is the handout’s `reset`. With reset low ( $\overline{R}$ ) each rising clock edge counts 00 → 01 → 10 → 11 → 00; with reset high ( $R$ ) every state goes to 00.

Part (a): the counter’s logic

PS5-Q2, p3 (the logic). Design a two-bit wrap-around counter. The counter counts from “00” to “11” and then begins again at “00.” […] a synchronous input reset which resets the counter back to “00” when active.

Hint

Counting is adding 1. Which bit flips every cycle, and when does the other one flip?

Recognize. Storage cells, the small-design move: “design a counter … a synchronous reset”. About 8 minutes, by analogy with a 10-point design part (PS5 gives no points).

On the paper.

State table, R = 0: 00 → 01 → 10 → 11 → 00; R = 1: every state → 00
$Q_0^+ = \overline{Q_0}$ (flips every cycle)
$Q_1^+ = Q_1 \oplus Q_0$ (flips when the carry $Q_0 = 1$ ); the wrap from 11 is free
Synchronous reset: AND each bit with $\overline R$
$D_0 = \overline{Q_0}\,\overline R = \text{NOR}(Q_0, R)$
$D_1 = (Q_1 \oplus Q_0)\,\overline R = \text{NOR}(\text{XNOR}(Q_1, Q_0), R)$
Faster, one gate ( $\overline{Q}$ from the flip-flops): $D_1 = \overline{R + Q_1Q_0 + \overline{Q_1}\,\overline{Q_0}}$
Two rising-edge static master–slave flip-flops on the one clock
Check: from 00, R = 0 gives 01, 10, 11, 00 ✓; R = 1 gives a 1 into both NORs, so 00 ✓

Draw the two flip-flops on one clk, a NOR of $Q_0$ and R into $D_0$ , and an XNOR of $Q_1$ and $Q_0$ into a NOR with R into $D_1$ .

Two flip-flop boxes, FF1 above FF0, both clocked by one clk wire from the left. FF0's D comes from a NOR of Q0 and R. FF1's D comes from a NOR whose inputs are R and the output of an XNOR of Q1 and Q0. Q1 and Q0 leave at the right and are wired back to the gates. — What to draw (FS2’s counter added): two rising-edge flip-flops on one clock, $D_0 = \text{NOR}(Q_0, R)$ , $D_1 = \text{NOR}(\text{XNOR}(Q_1, Q_0), R)$ . Original figure ↗

Watch out. “Synchronous” means the reset enters through D and acts at a clock edge; wiring it to the stored nodes makes an asynchronous reset.

Answer: $D_0 = \text{NOR}(Q_0, \mathrm{reset})$ and $D_1 = \text{NOR}(\text{XNOR}(Q_1, Q_0), \mathrm{reset})$ , or one complex gate $D_1 = \overline{\mathrm{reset} + Q_1Q_0 + \overline{Q_1}\,\overline{Q_0}}$ , into two rising-edge static flip-flops on the one clock.

Full solution

Part (b): the reset and the clock

PS5-Q2, p3 (the timing). You may assume that reset arrives 20 psec after the rising edge of the clock. The clock is 50% duty cycle with 20-psec rise and fall times. […] Design your circuit for the fastest clock frequency possible […].

Two flip-flops, FF1 above FF0, on one clk wire. FF0's D is a NOR of Q0 and R; FF1's D is a NOR of R and an XNOR of Q1 and Q0. Q1 and Q0 are wired back to the gates. — Part (a)‘s counter added: bit 1’s path runs through the XNOR and a NOR, bit 0’s through one NOR, and R (`reset`) enters both NORs directly. Original figure ↗

Hint

The reset is just another data input, one that changes 20 ps after each edge. Which edge does it miss, and which one must it make?

Recognize. Storage cells: a synchronous input that “arrives 20 psec after the rising edge” is a flip-flop output with a 20 ps clock-to-Q; “the fastest clock” is the slowest path into a D. About 8 minutes, by analogy (no points given).

On the paper.

reset leaves 20 ps after edge $k$ : like $t_{clk\to Q} = 20$ ps
Edge $k$ has sampled the old reset: a normal step; edge $k+1$ loads 00
Hold at edge $k$ : $20 + t_{NOR,min} \ge t_{hold}$
Setup at edge $k+1$ : $20 + t_{NOR} + t_{setup} \le T$
Counter loops: $t_{clk\to Q} + t_{logic} + t_{setup} \le T$
For example (none given): $t_{clk\to Q} = 60$ , $t_{setup} = 40$ , $t_{hold} = 15$ , NOR2 35, XNOR2 60 ps
Bit 1: $60 + 60 + 35 + 40 = 195$ ; bit 0: $60 + 35 + 40 = 135$ ; reset: $20 + 35 + 40 = 95$ ps
Bit 1 is critical: $T \ge 195$ ps, 5.13 GHz
Bit 1 as one 55 ps gate: $60 + 55 + 40 = 155$ ps, 6.45 GHz
Hold: reset $20 + 35 = 55 \ge 15$ ; $Q_0$ loop $60 + 35 = 95 \ge 15$ : safe

Watch out. The reset does not act at the edge it follows: it is too late for that edge and must not disturb it (that is the hold check). The delays are not in the handout: label yours “for example”.

Answer: The reset is sampled like data: asserted 20 ps after edge $k$ , it leaves edge $k$ ‘s step alone and loads 00 at edge $k+1$ . It needs $20\,\mathrm{ps} + t_{NOR} + t_{setup} \le T_{cycle}$ and $20\,\mathrm{ps} + t_{NOR,min} \ge t_{hold}$ . Bit 1’s path, $t_{clk\to Q} + t_{XNOR} + t_{NOR} + t_{setup}$ , limits the clock: with the example delays 195 ps (5.13 GHz), or 155 ps (6.45 GHz) with bit 1’s logic merged into one gate.

Full solution