FN10: the 2010 final
The Fall 2010 final (200 points, ten questions). Work through it in order: each part gives its question in short and links to the page that solves it, and to its exam way where the page has one. The exam ways of F1–F4 come with their rebuild in early December.
22 parts: all solved in the guide, 11 with an exam way.
FN10-1 (10 points)
An inverter built to swing between 2.5 V and 5 V, with its body connections: how do its rising and falling delays compare with a regular 0–2.5 V inverter?
FN10-2
FN10-2a (10 points)
An inverter at V with nA and 80 mV/decade: the ratio.
FN10-2b (5 points)
Its delay into 10 fF at 0.2 V.
FN10-2c (10 points)
The lowest at which the inverter still swings from to , and there.
FN10-3 (10 points)
Find a test pattern that detects a stuck-at-1 fault at node X and propagates it to Z. Is it unique?
FN10-4
FN10-4a (10 points)
Four inverters with a 20 fF side load and W = 1 µm: the delay from A to B.
FN10-4b (10 points)
The dynamic energy of one transition through the chain.
FN10-5
FN10-5a (10 points)
An SRAM’s decode path: its delay in units of .
FN10-5b (10 points)
The read access delay, the bitline pulled from to , in units of .
FN10-5c (6 points)
With FO4 ≈ , the access time in FO4; why that is a challenge for a 12–15 FO4 cycle, and a remedy.
FN10-6
FN10-6a (10 points)
The supply sensitivity of a velocity-saturated inverter’s delay.
FN10-6b (10 points)
The same for a square-law device.
FN10-6c (8 points)
A 2 ns clock tree whose supply varies between 2.5 V and 2.0 V: the jitter.
FN10-6d (7 points)
With ps and ps, could this jitter cause a failure that a slower clock cannot fix?
FN10-7
FN10-7a (10 points)
What logic function does a pass-transistor network perform?
FN10-7b (10 points)
Build a static CMOS network with the same function.
FN10-8
FN10-8a (10 points)
The Elmore delay of a wire tree from A to B, with 100 fF at receivers B and C.
FN10-8b (10 points)
The same with two more 200 fF loads, 1000 µm from each receiver.
FN10-9
FN10-9a (10 points)
A dynamic gate followed by static gates: the A-rising-to-E-rising delay in evaluate with every width 1 µm.
FN10-9b (14 points)
Keep µm and resize for minimum delay, with every β ratio between 0.25 and 4.
FN10-10
FN10-10a (4 points)
A 4k × 16 memory: how many address bits?
FN10-10b (6 points)
With the array organized as 256 × 256, how many address bits go to column multiplexing? Explain.