FM1. SRAM, decoders and memory addressing: the exam way

This is the exam way of FM1: each part as you would write it on the paper, with what to recognize, the lines to write, the trap to watch and the answer. Every part keeps the anchor it has on FM1, so the switch at the top of the page takes you to the same part’s full solution. The methods are three cards of the playbook: the SRAM access path for FN10-5, memory addressing for FN10-10 and FN12-10d, and the dynamic row decoder for FN17-6. FM1’s six harder variations stay on FM1 only, at the end of each family: the access path, addressing and decoders and the dynamic row decoder. Work them there, against the budgets their titles give.

The clock. The past finals gave 180 minutes. FN10 and FN12 had 200 points, 0.9 min a point, so FN10-5’s 10, 10 and 6 points have about 9, 9 and 5 minutes, FN10-10’s 4 and 6 points about 4 and 5, and FN12-10d’s 9 points about 8; FN17 had 250, 0.72 min a point, so FN17-6’s two 8-point parts have about 6 minutes each.

Conventions. Delays are in $\tau_1$τ1​, the paper’s fan-out-of-one delay (the guide’s $\tau_{inv}$τinv​), and FO4 $\approx 3\,\tau_1$3τ1​, as FN10-5c states. Loads are counted in µm of gate at $C_g = 2$ fF/µm, so $C$ fF is $C/2$ µm. A stage’s delay is its gain: its load over the input of the inverter that drives as hard, $3W_{eq}$ for a pull-down of equivalent width $W_{eq}$ (devices in series combine like resistors, $W_{eq} = 1/\sum 1/W_i$1/∑1/Wi​), $1.5W_p$ for a rising edge through a PFET of $W_p$Wp​. $\phi_2$ high is precharge, $\phi_1$ high is the access, and $t_{NO}$ is the gap from $\phi_2$ falling to $\phi_1$ rising.

FN10-5: the SRAM decode path, the bitline and the access time (26 points)

FN10-5, p7. As you learned in the design project, the access time of an SRAM is determined by the delay through the decode path as well as the time to perform the bitline access. Let’s consider these two components of the delay for a memory with 256 rows (8 bits of row address).

Consider the decode path shown above. Sixteen (16) domino NOR gates produce 16 precoded lines that then fanout two 256 race-based wordline decoders. Assume that the wordline drives 256 SRAM cells with $1\mu m$ access transistors and 100 fF of wire capacitance. Also assume that transistor gate cap is $2fF/\mu m$2fF/μm. All devices are minimum length. $V_{DD}=2.5V$2.5V.

FN10-5’s decode path (Final 2010, p7, redrawn without the key’s handwriting). Widths in µm. The numerals I–V are this guide’s stage names; the load at the right is the paper’s “wordline load”, $C_{WL}$CWL​. “Precoded” and “fanout two” are printed so: read “predecoded” and “fan out to”.

Part (a): the decode path’s delay (10 points)

FN10-5a, p7. Estimate the delay of the decode path shown above (for the critical evaluation edge) as a multiple of the fanout-of-one (FO1) delay, $\tau_1$τ1​. (10 points)

Hint

On each stage’s critical edge, which devices conduct, and whose gates does its output have to charge? How many gates hang on the word line from one cell?

Recognize. The SRAM access path, with the gain rule of path sizing: a chain of transistor stages with widths, “as a multiple of $\tau_1$τ1​”, “critical evaluation edge”. About 9 minutes: five divisions, and the marks are in the loads.

On the paper.

1. Gain = load / input: falling, $3W_{eq}$ (input NFET and foot in series); rising, $1.5W_p$
2. Drain capacitance ignored; worst case, one NOR input high
3. I ↓: $W_{eq} = 1/(1/20 + 1/20) = 10$10; load II, $100 + 15 = 115$115: $115/30 = 3.83$
4. II ↑: load $256 \times 4 = 1024$ (the printed 256X): $1024/150 = 6.83$
5. III ↓: $W_{eq} = 2$2, input 6; load IV’s NFET only: $20/6 = 3.33$
6. IV ↓: $W_{eq} = 10$10, input 30; load V, 115: $115/30 = 3.83$
7. Word line, 2 access gates a cell: $C_{WL} = 100 + 256 \times 2 \times 1 \times 2 = 1124$ fF $= 562$ µm
8. V ↑: $562/150 = 3.75$
9. Sum: $3.83 + 6.83 + 3.33 + 3.83 + 3.75 = 21.57\,\tau_1$
10. (I–III, $13.99$13.99, before $\phi_1\!\uparrow$ϕ1​↑; IV–V, $7.58$7.58, after it)
11. Note: by the predecoder’s topology each line feeds 64: II 1.71, path $16.45\,\tau_1$16.45τ1​; say which you used

What to write (FM1’s gains): each stage’s edge, input, load and gain, split at $\phi_1\!\uparrow$ϕ1​↑. Original figure ↗

Watch out. One access gate per cell gives 612 fF, stage V 2.04 and $19.86\,\tau_1$19.86τ1​: the key’s slip. A 6T cell has two access NFETs on its word line. The precharge PFETs are off on evaluation: they add neither drive nor load.

Answer: about $21.6\,\tau_1$ ($3.83 + 6.83 + 3.33 + 3.83 + 3.75 = 21.57\,\tau_1$3.83+21.57τ1​), with the word line at $100 + 256 \times 2 \times 1 \times 2 = 1124$ fF.

Full solution

Part (b): the bitline’s delay (10 points)

FN10-5b, p8. Estimate the delay of the read access of an SRAM cell (as a multiple of $\tau_1$τ1​) assuming that the bitline must be pulled from $V_{DD}$ to $V_{DD}/2$ for detection. To do this, assume that the nFETs of the 6-T SRAM cell have $1\mu m$ width and that the total capacitance of the bitline is 250 fF. (10 points)

Hint

Which two of the cell’s NFETs carry the bitline’s charge to ground, and how are they connected?

Recognize. The SRAM access path, the bitline: “read access of an SRAM cell”, “from $V_{DD}$ to $V_{DD}/2$VDD​/2”, a total bitline capacitance. About 9 minutes for a few lines: spend the spare on the size check.

On the paper.

1. Read: the cell’s 0 side pulls its bitline down through access and pull-down, in series
2. $W_{eq} = (1 \times 1)/(1 + 1) = 0.5$ µm; input $3 \times 0.5 = 1.5$ µm
3. Load: $250/2 = 125$ µm of gate (the total: nothing added for drains)
4. $V_{DD} \to V_{DD}/2$ is the 50 % point, so the gain is the delay
5. $t_{BL} = 125/1.5 = 83.3\,\tau_1$
6. Size: about 4 times the decode path’s 21.57; the bitline dominates

The read column (Chapter 19 §7): the precharged bitline falls through the selected cell’s access and pull-down NFETs. Original figure ↗

Watch out. The access NFET alone gives $125/3 = 41.7\,\tau_1$41.7τ1​, half the answer: the pull-down is in series with it.

Answer: about $83\,\tau_1$ ($125/1.5 = 83.3\,\tau_1$125/1.5=83.3τ1​).

Full solution

Part (c): the access time, the cycle and a remedy (6 points)

FN10-5c, p8. If the fanout-of-four delay (FO4), $\tau_4\cong3\tau_1$3τ1​, what is the approximate memory access time as a multiple of $\tau_4$τ4​? If a typical processor has a cycle time of 12-15 FO4, with most cycles including a memory access, why might this be a challenge? Name one technique for improving SRAM access time. (6 points)

Hint

What happens in a read between the address arriving and the data being seen, and how many cycles of 12–15 FO4 is that?

Recognize. The SRAM access path, the total: “access time as a multiple of $\tau_4$τ4​”, “cycle time of 12-15 FO4”, “name one technique”. Three questions in about 5 minutes: a line or two each for the number, the reason and the remedy.

On the paper.

1. The bitline starts when the word line is up: $t_{access} \approx t_{decode} + t_{BL}$
2. $21.57 + 83.33 = 104.9\,\tau_1$ (detector at $V_{DD}/2$VDD​/2; its own delay left out)
3. $\tau_4 \approx 3\,\tau_1$3τ1​, the paper’s: $104.9/3 = 35.0$ FO4
4. $35.0/15 = 2.3$ to $35.0/12 = 2.9$ cycles
5. An access in most cycles: slow the clock about 3 times, or pipeline the access over about 3 cycles
6. Bitline $83.3/104.9 = 79\,\%$79%: attack the bitline
7. Sense amplifier at 50–100 mV instead of 1.25 V: the bitline term ÷ 12.5 at 100 mV
8. Others: banks (shorter bitlines), a skewed detector, self-timing

The access against the cycle (FM1’s budget): the bitline is most of the bar, and the bar is more than twice a 15 FO4 cycle. Original figure ↗

Watch out. FO4 $= 4\,\tau_1$ holds only with no drain capacitance; the paper fixes 3. Carry 5a’s 21.57, not the key’s 19.86 (which gives its 34 FO4), and answer all three questions: the key gives only the number.

Answer: about 35 FO4 ($21.57 + 83.33 = 104.9\,\tau_1$21.57+104.9τ1​, divided by 3). That is 2.3–2.9 cycles of 12–15 FO4, so a processor that reads memory in most cycles must slow its clock about threefold or pipeline each access over about three cycles. One technique: a sense amplifier that fires at a 50–100 mV swing, which cuts the dominant bitline term more than tenfold (others: banking, a skewed detector, self-timing).

Full solution

FN10-10: address bits for a 4k × 16 memory (10 points)

FN10-10, p17. Assume that I have a memory with a logical organization of $4k\times16bits$16bits.

FN10-10 prints no figure. This is the array it asks about: Chapter 18’s SRAM array (Lecture17 @ 57:57, redrawn). Its numbers are Chapter 18’s example, not FN10-10’s: a 1024 × 32 memory stored as 256 rows of 128 columns, its 10 address bits split 8 to the row decoder and 2 to the column multiplexer, 32 bits out.

Part (a): the address bits (4 points)

FN10-10a, p17. How many bits of address do I need? (4 points)

Hint

How many different words must an address be able to name?

Recognize. Memory addressing: “logical organization of $4k\times16$ bits”, “how many bits of address”. About 4 minutes.

On the paper.

1. One address names one word: bits $= \log_2(\text{words})$
2. 4k $= 4 \times 1024 = 4096$ words
3. $4096 = 2^{12}$212: 12 bits
4. Check: 1k $= 2^{10}$ takes 10 bits; 4k is 4 times as many, two bits more: 12

Watch out. The word width never enters. $4096 \times 16 = 65{,}536 = 2^{16}$ counts bits, and “16 bits” would name each bit on its own; the memory returns 16 at a time.

Answer: 12 address bits ($4096 = 2^{12}$4096=212).

Full solution

Part (b): the column-multiplexing bits (6 points)

FN10-10b, p17. If the internal array is organized to be $256\times256$256, how many bits of the address are needed for column multiplexing? Explain. (6 points)

Hint

How many 16-bit words fit on one row of 256 cells, and how many choices does that leave after the row is chosen?

Recognize. Memory addressing: “internal array organized to be $256\times256$256”, “column multiplexing”, “explain”. About 5 minutes; the explanation is the division.

On the paper.

1. It fits: $256 \times 256 = 65{,}536 = 4096 \times 16$
2. Rows: $\log_2 256 = 8$ bits to the row decoder
3. A row holds $256/16 = 16$ words of 16 bits
4. Pick one of 16: a 16:1 column multiplexer, $\log_2 16 = 4$ bits
5. Check: $8 + 4 = 12$12, part (a)‘s count

What to draw (FM1’s split): 8 bits pick the row, 4 pick one of its 16 words. Original figure ↗

Watch out. $\log_2 256 = 8$ “column bits” picks single columns: $8 + 8 = 16$ bits would name $2^{16}$ things, 16 times too many. The multiplexer picks words, not bits.

Answer: 4 bits for column multiplexing. 8 bits pick one of the 256 rows; each row holds $256/16 = 16$ sixteen-bit words, so a 16:1 column multiplexer driven by the other $\log_2 16 = 4$ bits picks the word ($8 + 4 = 12$8+12).

Full solution

FN12-10d: a decoder-driven ROM table (9 points)

FN12-10, p17. In this problem, we consider some of the combinational logic circuit styles we studied in the course.

FN12-10d’s circuit (Final 2012, p17, redrawn). Each NFET’s gate sits on the row that selects it; its drain is on a column and its source on the ground line between two rows.

The table (9 points)

FN12-10d, p17. For the following circuit, complete the logic table shown below. (9 points)

Hint

For a given input, how many of the eight ANDs are high, and what can the devices on the other rows do while their row is low?

Recognize. Memory addressing, a decoder-driven ROM: bubbled ANDs into rows, pseudo-NMOS columns under grounded-gate PFETs, “complete the logic table”. Read the columns as a PLA’s NOR plane. About 8 minutes, a minute a row of the table.

On the paper.

1. An AND is high when its bubbled inputs are 0: the rows decode 000 to 111 top to bottom, $x_1$ the MSB
2. One row high; each column a pseudo-NMOS NOR: a device on the selected row makes 0, else 1
3. Each device belongs to the row its gate crosses; the ground line is only its source
4. Devices: 000 $y_1y_2$y1​y2​; 010 $y_1y_3$y1​y3​; 100 $y_1$y1​; 101 $y_3$y3​; 110 $y_1$y1​; 111 $y_2$y2​; 001, 011 none
5. $x_1x_2x_3 \to y_1y_2y_3$y1​y2​y3​: 000 → 001, 001 → 111, 010 → 010, 011 → 111
6. 100 → 011, 101 → 110, 110 → 011, 111 → 101
7. Check: 8 devices, 8 zeros
8. Check: $y_1$‘s devices are on the rows with $x_3 = 0$0, so $y_1 = x_3$

What to write on the figure (FM1’s reading): each row’s output word at its right, a 0 for each device. Original figure ↗

Watch out. A device makes a 0, not a 1: it pulls its column low against the PFET. Read each device by the row its gate crosses, not by the row its drain sits beside.

Answer:

$x_1$	$x_2$	$x_3$	$y_1$	$y_2$	$y_3$
0	0	0	0	0	1
0	0	1	1	1	1
0	1	0	0	1	0
0	1	1	1	1	1
1	0	0	0	1	1
1	0	1	1	1	0
1	1	0	0	1	1
1	1	1	1	0	1

Full solution

FN17-6: the dynamic row decoder and its column (about 16 points)

FN17-6, p13. Nearly all of you designed and implemented static row decoders for your SRAM array in the design project. Many of you found that these were pretty big (lots of pFETs) and difficult to pitch match in layout to the SRAM array. Some groups decided to implement this with a more area-efficient dynamic decoder, similar to that shown below. We show only one column of the SRAM.

FN17-6’s decoder and one column (Final 2017, p13, redrawn). The bars on $x_1$ at W0 and W2 (†) are hidden under drain wires on the scan; they are read in, since only that reading gives one row per address. $X$ and $Y$ are this guide’s names for each decoder’s stage-1 and stage-2 nodes.

Part (a): the waveforms (8 points)

FN17-6a, p15. For the input waveforms shown, find the waveforms at $W_0$W0​, $B$B, $\overline B$B, and data_out. (8 points; the value is overwritten on the scan and uncertain)

FN17-6a’s input waveforms (Final 2017, p15, redrawn without the key’s traces). The four empty rows are the answer.

Hint

With $x_0 = x_1 = 1$1, which of the four NORs has both inputs low? Then, in each phase, which devices on the column are on?

Recognize. The dynamic row decoder: race-based NORs on $\bar\phi_2$ and $\phi_1$ϕ1​, one column with write stacks, given waveforms, “find the waveforms at”. About 6 minutes: find the row first, then go phase by phase.

On the paper.

1. Read W0 = NOR($\bar x_0$xˉ0​, $\bar x_1$xˉ1​), W2 = NOR($x_0$x0​, $\bar x_1$xˉ1​): the only reading with one row per address
2. $x_0 = x_1 = 1$1: only W0 has both inputs 0, in every cycle; W1–W3’s stage 1 falls in the gap
3. W0 rises at each $\phi_1\!\uparrow$ (stage 2’s foot opens on a high stage-1 node)
4. Stage 2’s PFET is on $\bar\phi_2$ϕˉ​2​: W0 falls only at the next $\phi_2\!\uparrow$
5. $\phi_2$ high: $B$ and $\bar B$ precharged high
6. Cycle 1, write = data_in = 1: $B$‘s stack pulls $B$ low fast; the cell stores 0 on its $B$ side
7. Later cycles, write = 0: reads; the cell pulls $B$ low, more slowly
8. $B$ stays low until $\phi_2\!\uparrow$ restores it
9. $\bar B$ high throughout, so data_out $= \overline{\bar B} = 0$ throughout

What to draw (FM1’s waveforms): a fast fall of $B$ on the write, slower falls on the reads, and the word line held until $\phi_2$ rises. Original figure ↗

Watch out. W0 does not fall with $\phi_1$ϕ1​: the lecture’s stage 2 precharges on $\phi_1$ϕ1​, this one on $\bar\phi_2$ϕˉ​2​. data_out is not data_in: this column returns the complement.

Answer: W0 is selected (the only NOR whose inputs, $\bar x_0$ and $\bar x_1$xˉ1​, are both low). W0 rises after each $\phi_1$ rise and falls after the next $\phi_2$ rise. $B$B: high in each precharge; pulled low in the first $\phi_1$ (the write of data_in = 1), discharged by the cell in each later $\phi_1$ (reads), and restored at each $\phi_2$ rise. $\bar B$Bˉ: high throughout. data_out: low throughout.

Full solution

Part (b): the non-overlap criterion (8 points)

FN17-6b, p16. What criterion does the dynamic decoder put on the nonoverlap window of phi1 and phi2? (8 points)

Hint

On an unselected row, what is stage 1’s node doing at the moment $\phi_1$ opens stage 2’s foot?

Recognize. The dynamic row decoder: “criterion”, “nonoverlap window of phi1 and phi2”. About 6 minutes: name the gap, the delay it must cover, and why.

On the paper.

1. Stage 1 (foot on $\bar\phi_2$ϕˉ​2​) evaluates from $\phi_2\!\downarrow$ϕ2​↓: unselected rows’ nodes fall
2. Stage 2 (foot on $\phi_1$ϕ1​) evaluates from $\phi_1\!\uparrow$ϕ1​↑: it fires on any row whose stage-1 node is still high
3. A precharged node drives a dynamic gate directly (no domino inverter): a race
4. If $\phi_1$ comes first, a wrong row’s stage 2 falls and cannot recover before precharge: a second word line
5. Criterion: $t_{NO} = t(\phi_1\!\uparrow) - t(\phi_2\!\downarrow) \ge t_{eval}$ of the stage-1 NOR
6. Worst case: one input high, through one NFET and the foot; add margin for skew
7. The other gap, $\phi_1\!\downarrow$ to $\phi_2\!\uparrow$ϕ2​↑: no race; the word line just stays up

The race-based NOR’s timing (Chapter 19 §12): an unselected row’s stage-1 node must fall within $t_{NO}$tNO​. Original figure ↗

Watch out. The condition is on the gap before $\phi_1$ϕ1​, not the one after it. Give the reason, the race onto a second word line: the key states only the condition.

Answer: The non-overlap window from $\phi_2$ falling to $\phi_1$ rising must be longer than the evaluation time of the decoder’s stage-1 NOR, $t_{NO} \ge t_{eval}$teval​, with margin for skew. Every unselected row’s stage-1 node must have fallen before $\phi_1$ opens stage 2’s foot; otherwise stage 2 discharges on a wrong row and raises a second word line.

Full solution