8. Logical effort and path sizing

Lecture 7 ended with one gate: its delay is its gain $g \cdot h$ times $\tau_{inv}$τinv​. Lecture 8 strings gates together into a path and asks the designer’s question: given the load at the end and the gate at the start, how big should every gate in between be, so that the path is as fast as possible? The answer is short and powerful. Multiply the gains together and you get a number, the path effort $F$F, that does not depend on the sizes at all; the delay is smallest when every stage has the same gain, $F^{1/N}$F1/N. From there the lecture finds the best number of stages (a gain of about 3 to 4 per stage, the reason FO4 is the industry’s yardstick), works a full example from 6.86 ns down to 756 ps, and then shows what breaks when a path branches. It closes with the reason, promised in Lecture 7, why the device at the bottom of a stack is slow.

After this chapter you can:

1. find any gate’s gain by replacing it with its normalized inverter and dividing its load by that inverter’s input;
2. write a path’s delay as $\sum g_i h_i\,\tau_{inv}$ and its path effort as $F = \prod g_i h_i = G \cdot H$H;
3. explain why $F$ is fixed when the input and output capacitances are fixed and nothing branches, and why the delay is then smallest with equal gains $F^{1/N}$F1/N;
4. choose the number of stages (a gain near $e$e, in practice 3–4 per stage) and say where added inverters belong and why;
5. size a path backwards from the load for equal gains, and estimate its delay before and after;
6. compute the branching effort, explain why it makes $F$ depend on the sizes, and retune a path around a branch;
7. explain why the device furthest from the output in a stack switches slowest, and use it to choose pins.

Boxes and equations marked board were written in the lecture. Parts marked added are explanations or examples this guide adds.

Symbols

Symbol	Meaning	Unit	First appears
$\tau_{inv}$	the fan-out-of-one delay: a balanced inverter driving a copy of itself; $3R_{nfet}C_g$ for a 2W/W inverter	ps	Before you start
$R_{nfet}$Rnfet​, $R_{pfet}$	the “resistance” of a 1 µm NFET or PFET; a device of width $W$ has $R/W$	kΩ·µm	Before you start
$C_g$	gate capacitance per micron of width	fF/µm	Before you start
$W$	a device width; “2.4/1.2” is a PFET 2.4 µm over an NFET 1.2 µm	µm	§1
$g$	logical effort: a gate’s input capacitance over that of an inverter with the same drive	—	§1
$h$	electrical effort: the capacitance a stage drives over its own input capacitance	—	§1
$f_i = g_ih_i$	the gain (stage effort) of stage $i$i; the stage’s delay is $f_i\,\tau_{inv}$	—	§1
$C_{in}$	the input capacitance of the whole path (fixed)	fF or µm of gate	§2
$C_{in2}, C_{in3}, \dots$Cin2​,Cin3​,…; $C_j$	the input capacitance of stage 2, 3, …; of gate $j$	fF or µm of gate	§2; §3
$C_L$CL​, $C_{out}$	the load at the end of the path	fF or µm of gate	§2
$F$	path effort, $\prod f_i$	—	§2
$G$G, $H$	$\prod g_i$∏gi​; $C_L/C_{in}$	—	§2
$N$ (or $n$n)	the number of stages	—	§3
$f = F^{1/N}$	the equal gain that minimizes the delay	—	§3
$\alpha$	the gain per stage of an inverter chain	—	§4
$C_x$	a capacitance hanging off the path (a branch)	fF	§8
$b$b, $B$	branching effort of one node; the product over all branches	—	§8

Before you start

You need these ideas from Chapter 7. Each is restated here.

• The delay model. A pull-down of width $W$ has “resistance” $R_{nfet}/W$ (kΩ), a gate input of width $W$ has capacitance $C_gW$ (fF), and delay = resistance × load capacitance (1 kΩ × 1 fF = 1 ps). Drain capacitance is ignored.
• The unit of delay. $\tau_{inv} = 3R_{nfet}C_g$3Rnfet​Cg​, the delay of a 2W/W inverter driving a copy of itself, whatever $W$ is.
• Loads as widths. Every gate input is $C_g$ per micron, so a load $C$ “is” $C/C_g$ microns of gate. At 2 fF/µm, 1 pF is 500 µm.
• The stack rule. $n$ devices in series, each $n$ times wider, have the strength of one device.
• Logical effort, electrical effort and gain. A gate sized for an inverter’s drive has a larger input: $g_{inv} = 1$1, $g_{NAND2} = 4/3$4/3, $g_{NOR2} = 5/3$5/3. Its electrical effort is $h = C_{out}/C_{in}$Cout​/Cin​. Its delay is $g \cdot h \cdot \tau_{inv}$τinv​.

Notation. A size written “2.4/1.2” means a PFET 2.4 µm and an NFET 1.2 µm wide, as on the boards. $f_i = g_ih_i$ is the gain (the board also says “stage effort”) of stage $i$i, and $F$ the path effort. $C_{in}$ is the input capacitance of the whole path, $C_{in2}, C_{in3}, \dots$ those of later stages, and $C_L$ the final load. $G = \prod g_i$∏gi​, $H = C_L/C_{in}$ and $B$ (Section 8) are the names in Sutherland and Sproull’s book; the boards write the products out.

1. A gate’s gain from its normalized inverter

The idea. Replace the gate by the inverter that has the same drive, its normalized inverter. The gate’s gain is the capacitance it drives divided by that inverter’s input capacitance.

Lecture08 @ 04:14The recap: a NAND (all 2 µm) and its normalized inverter, 2 µm/1 µm (circled, bottom left); driving two NANDs, delay = (2)(4/3) τ_inv, h times g, the gain or stage effort.

The recap

The lecture opens with Lecture 7’s NAND (00:26) board: every device 2 µm, so the two series NFETs act like one 1 µm NFET and each PFET alone matches a 2 µm PFET. It has the drive of a 2/1 µm inverter. Driving one NAND of the same size it sees 4 µm of gate; the 2/1 inverter’s input is 3 µm; the delay is $\tfrac43\,\tau_{inv}$ (01:24). Driving two such NANDs (02:00):

$$\text{delay} = (2)\left(\tfrac43\right)\tau_{inv} = \tfrac83\,\tau_{inv}.$$

The 2 is the electrical effort $h$h, the capacitance driven divided by the gate’s own input capacitance, $8/4$8/4; the $\tfrac43$ is the logical effort $g$g. Their product is the gain, also called the stage effort (03:00) board. (At 02:13 the lecturer calls the 2 “the logical effort”; the board, and his definition a few seconds later, put $h$ under the 2.)

The quick way: the normalized inverter

“A quick and easy way to calculate the gain of a stage” (03:15): replace the gate by its normalized inverter, the inverter with the same drive strength, and divide the total capacitance the gate drives by that inverter’s input capacitance.

The NAND driving two NANDs, in one shot (03:15–04:08)

1. Normalized inverter of the NAND: a 2/1 µm inverter, input $2 + 1 = 3\,\mu\mathrm{m}$3μm.
2. Total load: two NAND inputs, $(2 + 2) + (2 + 2) = 8\,\mu\mathrm{m}$8μm.
3. Gain $= 8/3$8/3, delay $\tfrac83\,\tau_{inv}$38​τinv​: the same answer as $g \cdot h = \tfrac43 \times 2$2.

Why it works added: the gate pulls down like the normalized inverter’s NFET, $R_{nfet}/W$Rnfet​/W, so its delay is $(R_{nfet}/W)\,C_{out}$(Rnfet​/W)Cout​. With $\tau_{inv} = 3R_{nfet}C_g$ that is $C_{out}/(3WC_g)\cdot\tau_{inv}$τinv​: the load over the normalized inverter’s input. You never need $g$ and $h$ separately.

How to find the normalized inverter. added Find the strength of each network for a single input switching (the worst case), using the stack rule:

• NAND: the NFETs are in series, so $n$ NFETs of width $W'$ act like one of $W'/n$W′/n; a PFET alone acts like itself.
• NOR: a single NFET acts like itself; the PFETs are in series, so $n$ of width $W'$ act like $W'/n$W′/n.
• A balanced gate’s normalized inverter is then “2W/W”: its input is $3W$3W, with $W$ the equivalent NFET width.

Worked example. added A NAND with all four devices 3 µm drives 20 µm of gate. The two NFETs in series act like 1.5 µm; one PFET is 3 µm: the normalized inverter is 3/1.5, input 4.5 µm. Gain $= 20/4.5 = 4.44$4.44. Check with $g \cdot h$h: the NAND’s input is $3 + 3 = 6\,\mu\mathrm{m}$6μm, so $h = 20/6 = 3.33$3.33, and $\tfrac43 \times 3.33 = 4.44$4.44.

Equal-strength technologies. added Some exams state that the NFET and PFET have the same drive. Then the balanced inverter is W/W (input $2W$2W), $\tau_{inv} = 2R_{nfet}C_g$2Rnfet​Cg​, a NAND2 is NFETs $2W$2W, PFETs $W$ ($g = 3/2$g=3/2), and a NOR2 is NFETs $W$W, PFETs $2W$ ($g = 3/2$g=3/2). The normalized-inverter rule is the same; divide by $2W$ instead of $3W$3W.

Common mistakes.

• Dividing by the gate’s own input capacitance. That gives $h$h, not the gain; the gate’s input is larger than its normalized inverter’s by the factor $g$g.
• Counting only the on-path load. The gain uses everything the output drives (Section 8).

Check yourself A gate's pull-down is two series pairs of NFETs, the pairs in parallel (A·B + C·D); its pull-up is two parallel pairs of PFETs in series. Every NFET is W and every PFET 2W, with R_pfet = 2R_nfet. Find its normalized inverter, its logical effort, and its gain when it drives a 2-input NAND whose devices are all W.

This is the AOI22 of Chapter 7. A single input switching sees a stack of two in either network: the NFETs act like $W/2$W/2, the PFETs like $2W/2 = W$W. The normalized inverter is $W$ over $W/2$W/2, input $1.5W$1.5W. One input drives an NFET $W$ and a PFET $2W$2W: $3W$3W, so $g = 3W/1.5W = 2$2. The NAND’s input is $W + W = 2W$2W, so the gain is $2W/1.5W = 1.33$1.33. (MT17-5 uses exactly this gate as its second stage.)

2. Path delay and path effort

The idea. A path’s delay is the sum of its gains. Their product, the path effort $F$F, depends only on the gate types and on the capacitances at the two ends of the path, not on how the gates in between are sized.

The board’s four-gate path (redrawn from Lecture08 @ 09:59): an inverter, a NOR, a NAND and an inverter between $C_{in}$ and $C_L$CL​, each gate driving only the next. $C_{in}$ is the path’s input capacitance; $C_{in2}$Cin2​, $C_{in3}$ and $C_{in4}$ are those of gates 2, 3 and 4.

The board (Lecture08 @ 09:59)

Lecture08 @ 09:59Delay = Σ g_i h_i τ_inv; the path effort F = Π g_i · Π h_i, and Π h_i telescopes to C_L/C_in (right).

Fair copy of the board above (Lecture08 @ 09:59), mark for mark in its own layout. Black is the blue pen. Magenta is the pink pen, the second layer: the ellipse and “constant” round $F$F, the circle round $\prod h_i$∏hi​, and the telescoping product it leads to at the right. The circuit is read from 11:12, where the lecturer doesn’t block it.

Posing the problem

The question (04:20): for a path through combinational logic, how should the gates be sized for the minimum delay? Only delay for now; power matters too, and the lecture comes back to it (04:47). The example path (05:09) board: an inverter, a NOR, a NAND, an inverter, and a final load $C_L$CL​, with no fan-out: every gate drives exactly one gate (05:39).

Two capacitances must be fixed for the question to make sense (06:09):

• the load at the end, $C_L$CL​;
• the input capacitance of the path, $C_{in}$Cin​. Otherwise you could make every gate enormous and push a huge capacitance onto the path’s input, which is “kind of fake, because somebody’s gonna have to drive that large capacitance” (06:30).

Delay and path effort

Each stage has a logical effort $g_i$ and an electrical effort $h_i$hi​, so board

$$\text{Delay} = \sum_{i=1}^{n} g_ih_i\,\tau_{inv}.$$

Now multiply the stage efforts instead of adding them (07:18). The product is the path effort $F$ board:

The path effort is a constant (board, 07:35–09:59)

1. $F = \prod_i g_ih_i = \prod_i g_i \cdot \prod_i h_i$∏i​hi​.
2. $\prod g_i$ depends only on which gates are in the path: here $1 \times \tfrac53 \times \tfrac43 \times 1$1. It is a constant board.
3. Each $h_i$ is the capacitance stage $i$ drives over its own input capacitance. Without fan-out, stage $i$ drives exactly stage $i + 1$‘s input.
4. So $\prod h_i = \dfrac{C_L}{C_{in4}} \times \dfrac{C_{in4}}{C_{in3}} \times \dfrac{C_{in3}}{C_{in2}} \times \dfrac{C_{in2}}{C_{in}}$ board: “cancel, cancel, cancel” (09:30).
5. $\prod h_i = C_L/C_{in}$ board, fixed because both ends are fixed.
6. So $F$ is a constant: resize the gates in between however you like, and $F$ stays the same (09:59).

(At 09:15 the lecturer says the electrical effort is “the capacitance that I’m driving times my own input capacitance”; he means divided by, as the board’s fractions show.)

Path delay and path effortboard

$$\text{Delay} = \tau_{inv}\sum_i g_ih_i$$$$F = \prod_i g_ih_i = G\,H$$$$G = \prod_i g_i, \qquad H = \frac{C_L}{C_{in}}$$

Holds when: every gate drives only the next one (no fan-out); C_in and C_L fixed; gate loading only. The names G and H are added

Worked example. added For the board’s path (inverter, NOR, NAND, inverter), $G = 1 \times \tfrac53 \times \tfrac43 \times 1 = \tfrac{20}{9} = 2.22$2.22. If $C_L$ is 64 times $C_{in}$Cin​, then $F = 2.22 \times 64 = 142$142, whatever the sizes of the NOR, NAND and second inverter.

Common mistakes.

• Forgetting that $H$ is $C_L$ over the input of the first gate, not of the last.
• Using $F = GH$ when a gate drives anything besides the next gate. Then $\prod h_i$ no longer telescopes (Section 8).

Check yourself A path is a NAND2 whose devices are all 2 µm (its input fixed at 4 µm), then a NOR2, then an inverter, then a load of 360 µm of gate. R_pfet = 2R_nfet. What are G, H and F?

$G = \tfrac43 \times \tfrac53 \times 1 = \tfrac{20}{9}$920​, $H = 360/4 = 90$90, $F = \tfrac{20}{9} \times 90 = 200$200.

3. Equal gains minimize the delay

You need

A path and its gains. A path is a chain of gates from a fixed input capacitance $C_{in}$ to a fixed load $C_L$CL​, each gate driving only the next one, like the board’s four-gate path below. Stage $i$‘s gain is $f_i = g_ih_i$gi​hi​. The logical effort $g_i$ is 1 for an inverter, $\tfrac43$ for a NAND2 and $\tfrac53$ for a NOR2 when $R_{pfet} = 2R_{nfet}$2Rnfet​. The electrical effort $h_i = C_{out}/C_{in}$ is the capacitance the stage drives over its own input capacitance. The quick way to get a gain is the load divided by the input of the gate’s normalized inverter (Section 1).

Path delay. Stage $i$ takes $f_i\,\tau_{inv}$fi​τinv​, where $\tau_{inv}$ is the fan-out-of-one delay of an inverter, so the path takes $\text{Delay} = \tau_{inv}\sum_i f_i$τinv​∑i​fi​. This section minimizes that sum.

Path effort. The product of the gains is $F = \prod f_i = \prod g_i \cdot \prod h_i$∏hi​. Because each gate drives only the next, $\prod h_i = \dfrac{C_{in2}}{C_{in}}\cdot\dfrac{C_{in3}}{C_{in2}}\cdots\dfrac{C_L}{C_{inN}} = \dfrac{C_L}{C_{in}}$Cin​CL​​: every inner capacitance cancels. So $F = G \cdot H$H, with $G = \prod g_i$ and $H = C_L/C_{in}$CL​/Cin​, whatever the sizes of the gates in between. That needs three conditions: nothing branches off the path; $C_{in}$ is fixed (otherwise you could make every gate huge and push the delay onto whatever drives the path); and $C_L$ is fixed. This section uses $F$ as the constraint: the gains can be traded against each other, but their product cannot change.

The board’s four-gate path (Lecture08 @ 09:59, redrawn): an inverter, a NOR, a NAND and an inverter between $C_{in}$ and $C_L$CL​, each gate driving only the next. Original figure ↑

The question. Between a fixed input and a fixed load you may resize every gate, but the product of the gains will not move. How should that fixed product $F$ be split among the stages so that their sum, the delay, is as small as possible? The lecture’s answer (10:44–12:08): split it equally.

Two stages

The lecture starts with the smallest case (10:44) board: two inverters, $g = 1$ each, between a fixed $C_{in}$ and a fixed $C_L$CL​.

Two inverters between a fixed input $C_{in}$ and a fixed load $C_L$ (redrawn from the board, Lecture08 @ 13:36). The only free choice is $C_{in2}$Cin2​, the second inverter’s input: it is stage 1’s load and stage 2’s strength.

The board (Lecture08 @ 13:36)

Lecture08 @ 13:36Two stages: f₁ f₂ = F, Delay = F/f₂ + f₂, and setting the derivative to zero gives f₁ = f₂ = √F; for n stages, ⁿ√F (top).

Fair copy of the board above (Lecture08 @ 13:36), mark for mark in its own layout. Black is the blue pen. Magenta is the pink pen, the later layer: the box and the ellipse over the left-hand equations and the whole two-stage derivation at the right. The board’s row Delay $= f_1 + f_2$ is partly rubbed out at 13:36; it is restored here from 12:27.

Two stages (board, 10:44–12:08)

1. Write the two gains. Stage 1 drives inverter 2’s input, so $f_1 = C_{in2}/C_{in}$Cin2​/Cin​. Stage 2 drives the load, so $f_2 = C_L/C_{in2}$CL​/Cin2​. The delay is $(f_1 + f_2)\,\tau_{inv}$ board.
2. See what is fixed. The only free choice is the size of inverter 2, that is, $C_{in2}$Cin2​. Making inverter 2 bigger makes it stronger, so $f_2$ falls; but inverter 2 is then a bigger load for inverter 1, so $f_1$ rises by the same factor. Their product $f_1f_2 = C_L/C_{in} = F$ does not depend on $C_{in2}$ board.
3. Eliminate $f_1$f1​. Because the product is fixed, $f_1 = F/f_2$ board, and the delay has one variable left: $\text{Delay} = \left(\dfrac{F}{f_2} + f_2\right)\tau_{inv}$ board.
4. Set the derivative to zero board. $\dfrac{d}{df_2}\left(\dfrac{F}{f_2} + f_2\right) = -\dfrac{F}{f_2^2} + 1 = 0$0, so $f_2 = \sqrt F$F​. The board writes only “= 0”; the derivative is written out here. The second derivative, $2F/f_2^3$2F/f23​, is positive, so this is a minimum added.
5. Then $f_1$f1​. $f_1 = F/\sqrt F = \sqrt F$ board: the two gains are equal.
6. In sizes added. $f_1 = \sqrt F$ means $C_{in2}/C_{in} = \sqrt{C_L/C_{in}}$CL​/Cin​​, so $C_{in2} = \sqrt{C_{in}\,C_L}$Cin​CL​​: the middle inverter’s input is the geometric mean of the two fixed ends.

The delay against the split

The derivative says where the minimum is. A plot shows how much an unequal split costs added. Take a concrete chain: inverter 1 is 2/1 µm, so its input is $C_{in} = 3\,\mu\mathrm{m}$ of gate (fixed), and the load is $C_L = 48\,\mu\mathrm{m}$ of gate. Then $F = 48/3 = 16$16, and three sizes for inverter 2 give three points of the curve:

Inverter 2’s input $C_{in2}$	$f_1 = C_{in2}/3$	$f_2 = 48/C_{in2}$	Delay
3 µm (a 2/1 inverter)	1	16	$17\,\tau_{inv}$
6 µm (4/2)	2	8	$10\,\tau_{inv}$
12 µm (8/4)	4	4	$8\,\tau_{inv}$

The two-stage delay against the split, computed from $\text{Delay}/\tau_{inv} = F/f_2 + f_2$ with $F = 16$ added. The marked points are the table’s three sizings and their mirror images; the minimum, 8, is at $f_2 = \sqrt F = 4$4.

Reading the curve.

• The bottom is at $f_2 = 4 = \sqrt{16}$16​, where $f_1 = 4$ too: $8\,\tau_{inv}$8τinv​. That is the 12 µm inverter, and $\sqrt{3 \times 48} = 12$12, the geometric mean of step 6.
• The curve is symmetric on the log axis. $f_2 = 2$ and $f_2 = 8$ both give $10\,\tau_{inv}$10τinv​: they are the same split with the two stages swapped. A second inverter that is too big costs as much as one that is too small by the same factor.
• It is flat near the bottom and steep far from it. $f_2 = 3$ (inverter 2’s input 16 µm) costs $8.33\,\tau_{inv}$8.33τinv​, only 4% more than the best. The split 2 and 8 costs 25% more, and 1 and 16 more than twice the best (17 against 8). Rough balance is nearly as good as exact balance; a badly unbalanced path is very slow.
• Why the steep side. Going from the balanced 4 and 4 to 2 and 8 saves $2\,\tau_{inv}$ in stage 1 but costs $4\,\tau_{inv}$ in stage 2. Halving one gain doubles the other, and the doubled gain is the larger one, so it always loses more than the halved one gains.

With the lecture’s $\tau_{inv} = 48$ ps (Section 5), the three sizings take 816, 480 and 384 ps.

Any number of stages

“In general, if I have $n$ stages … I want to take the $n$-th root of the path effort” (12:08) board. The lecture states the rule for $n$ stages without proof; here the number of stages is written $N$N. The argument below needs nothing beyond the two-stage case added.

Resize one gate, here gate 3, and only two gains move added: $f_2$f2​, because gate 3 is stage 2’s load, and $f_3$f3​, because gate 3 is stage 3’s strength. Their product $f_2f_3$ stays fixed. The stages are inverters ($g = 1$g=1), so the product is $C_{in4}/C_{in2}$Cin4​/Cin2​; with other gates it is $g_2g_3\,C_{in4}/C_{in2}$g2​g3​Cin4​/Cin2​, still fixed.

Why every gain must be equal (added)

1. Resize one inner gate and nothing else. Gate $j$‘s input capacitance $C_j$ appears in exactly two gains. It is on top in $f_{j-1} = g_{j-1}C_j/C_{j-1}$gj−1​Cj​/Cj−1​, because gate $j$ is stage $j-1$‘s load. It is underneath in $f_j = g_jC_{j+1}/C_j$gj​Cj+1​/Cj​, because gate $j$‘s size is stage $j$‘s strength. Every other stage keeps its load and its size, so its gain does not move.
2. That pair has a fixed product. $f_{j-1}f_j = g_{j-1}g_j\dfrac{C_j}{C_{j-1}}\cdot\dfrac{C_{j+1}}{C_j} = g_{j-1}g_j\dfrac{C_{j+1}}{C_{j-1}}$gj−1​gj​Cj−1​Cj+1​​, and $C_j$ has cancelled. Resizing gate $j$ is therefore exactly the two-stage problem, and the pair’s sum is smallest when $f_{j-1} = f_j$fj​.
3. The same fact without calculus. For two gains $a$ and $b$ with a fixed product $P$P, $a + b - 2\sqrt P = (\sqrt a - \sqrt b)^2 \ge 0$0, and it is zero only when $a = b$b. So any unequal neighbouring pair can be made faster by resizing the gate between them, and the rest of the path does not notice.
4. So at the best sizing every neighbouring pair is equal. If one pair were unequal, step 3 would lower the delay. So $f_1 = f_2$f2​, $f_2 = f_3$f3​, and so on: all $N$ gains are equal. They multiply to $F$F, so each is $F^{1/N}$F1/N.
5. The minimum delay is $N$ stages of $F^{1/N}$ each: $N\,F^{1/N}\,\tau_{inv}$NF1/Nτinv​.

What it means physically. In this model a stage’s delay is its gain times $\tau_{inv}$τinv​, so equal gains mean equal stage delays: no stage is a bottleneck. Every inner gate sits at the size where making it bigger would slow its driver by as much as it speeds up itself.

An example of step 4. A four-stage path with gains 2, 8, 4 and 4 has $F = 256$ and takes $18\,\tau_{inv}$18τinv​. Resize gate 2 only: $f_1f_2 = 16$ stays fixed, and rebalancing gives 4 and 4. The delay falls to $16\,\tau_{inv}$16τinv​, which is $4 \times 256^{1/4} = 16$16: this path is now at its minimum.

The rule to keep

Minimum delay for a fixed number of stagesboard

$$f = F^{1/N}$$$$\text{Delay}_{min} = N\,F^{1/N}\,\tau_{inv}$$

Holds when: F fixed: every gate drives only the next (no branch), and C_in and C_L are fixed; N, the number of stages, is fixed; every width may take any value; only gate capacitance counts

What breaks it.

• A branch. If a gate also drives something off the path, $F$ contains the sizes, and the best gains are no longer equal (Sections 8–9).
• A limit that binds. A gate that would have to be narrower than the minimum width, or a cap on how far a gate may be skewed (FN19-8, FN10-9), takes a width out of your hands.
• A free $N$N. If you may add inverters, choose the number of stages too (Section 4: a gain of about 3–4 per stage).

Memorize or derive. Memorize $f = F^{1/N}$ and $\text{Delay}_{min} = N\,F^{1/N}\,\tau_{inv}$NF1/Nτinv​, with their three conditions. Derive the reason when a question asks you to show it. It takes three lines:

1. Two stages with $f_1f_2 = F$F: $\text{Delay}/\tau_{inv} = f_2 + F/f_2$F/f2​.
2. $\dfrac{d}{df_2} = 1 - \dfrac{F}{f_2^2} = 0$0, so $f_2 = \sqrt F = f_1$f1​.
3. $N$ stages: resizing the gate between stages $j-1$ and $j$ keeps $f_{j-1}f_j$ fixed, so every neighbouring pair is equal, and $f = F^{1/N}$F1/N.

A worked example: the lecture’s path

The lecture’s own example (20:01–29:52) board, the path that Sections 5–7 estimate, resize and extend. It runs from a fixed inverter, 2.4/1.2 µm, through a NAND2 and a NOR2 to a 1 pF load. $R_{pfet} = 2R_{nfet}$2Rnfet​, $C_g = 2\,\mathrm{fF/\mu m}$ and $R_{nfet} = 8\,\mathrm{k\Omega\cdot\mu m}$8kΩ⋅μm.

The lecture’s example path at gate level (from the board, Lecture08 @ 29:52): a fixed inverter, $C_{in} = 3.6\,\mu$m (its devices are 2.4/1.2 µm), a NAND2 and a NOR2 driving 1 pF $= 500\,\mu$m of gate. The logical efforts are for $R_{pfet} = 2R_{nfet}$2Rnfet​.

The best delay of the lecture's path (board, 27:40–29:52)

1. The gate types give $G$G. With $R_{pfet} = 2R_{nfet}$2Rnfet​, $G = 1 \times \tfrac43 \times \tfrac53 = \tfrac{20}{9} = 2.22$2.22.
2. The two fixed ends give $H$H. The load in microns of gate is $1\,\mathrm{pF}/(2\,\mathrm{fF/\mu m}) = 500\,\mu\mathrm{m}$500μm, and the fixed inverter’s input is $2.4 + 1.2 = 3.6\,\mu\mathrm{m}$3.6μm: $H = 500/3.6 = 138.9$138.9.
3. The path effort. $F = GH = 308.6$308.6; the board writes 308 board. Nothing about the NAND’s or the NOR’s sizes went into it.
4. Equal gains. Three stages share it equally: $f = \sqrt[3]{308.6} = 6.76$ board.
5. The delay. $3 \times 6.76 = 20.3\,\tau_{inv}$20.3τinv​. The technology’s $\tau_{inv} = 3R_{nfet}C_g = 3 \times 8 \times 2 = 48$ ps, so the delay is 973 ps board.

Check. As drawn on the board, the gains were 0.667, 3.33 and 138.9. Their product is also 308.6, because $F$ does not depend on the sizes; but their sum is $142.9\,\tau_{inv} = 6.86$ ns. Equal gains make the same three gates about seven times faster. Section 6 then finds the widths that give those equal gains (the NAND all 12.2 µm; the NOR’s NFETs 24.7 µm and PFETs 98.8 µm), and Section 7 adds stages.

Traps.

• Equalizing the wrong thing. The rule equalizes the gains $g_ih_i$gi​hi​, not the sizes, not the electrical efforts $h_i$ and not the stage capacitances. In the worked example, at equal gains of 6.76 (6.758 unrounded) the inverter’s $h$ is 6.76, the NAND’s $6.758/\tfrac43 = 5.07$ and the NOR’s $6.758/\tfrac53 = 4.05$4.05: a gate with a larger logical effort gets a smaller electrical effort.
• Using $F^{1/N}$ with a branch. It assumes $F$ is fixed. A side load makes $F$ depend on the sizes (Section 8), and the best gains are unequal (Section 9).
• Speeding up one stage on its own. Enlarging the gate of the slowest stage lowers its gain but raises the gain of the stage before it by the same factor. In the 2, 8, 4, 4 path, making gate 2 four times bigger turns the first two gains into 8 and 2: still $18\,\tau_{inv}$18τinv​. Balance the pair instead.
• Resizing the first gate. Its input capacitance is $C_{in}$Cin​, the constraint that makes the problem well posed. It is given, not chosen.

Check yourself Two inverters sit between a fixed input of 2 µm of gate and a load of 200 µm of gate. What input should the second inverter have, and what is the delay in τ_inv? What is the delay if its input is 10 µm instead?

$F = 200/2 = 100$100, so each gain should be $\sqrt{100} = 10$10. The second inverter’s input is the geometric mean, $\sqrt{2 \times 200} = 20\,\mu\mathrm{m}$20μm, and the delay is $10 + 10 = 20\,\tau_{inv}$20τinv​. With 10 µm, the gains are $10/2 = 5$ and $200/10 = 20$20: $25\,\tau_{inv}$25τinv​, 25% slower.

Check yourself A path is a NAND2 whose devices are all 2 µm (its input, 4 µm, is fixed), then a NOR2, then an inverter, then a load of 360 µm of gate, with R_pfet = 2R_nfet. What gain should each stage have, and what is the minimum delay? A designer instead sizes the NOR and the inverter so that the first two gains are both 4. What is the third gain, and how much slower is the path?

$G = \tfrac43 \times \tfrac53 \times 1 = \tfrac{20}{9}$ and $H = 360/4 = 90$90, so $F = 200$200. Equal gains: $f = 200^{1/3} = 5.85$5.85, and the delay is $3 \times 5.85 = 17.5\,\tau_{inv}$17.5τinv​. With the first two gains at 4, the product still has to be 200, so the third gain is $200/16 = 12.5$12.5. The delay is $4 + 4 + 12.5 = 20.5\,\tau_{inv}$20.5τinv​, 17% slower.

Check yourself A four-stage path without branches has gains 2, 8, 4 and 4. You may resize only the second gate. What are the best first two gains, and the new delay? Is the path then at its minimum?

Resizing gate 2 moves only $f_1$ and $f_2$f2​, and their product $2 \times 8 = 16$ stays fixed, so the best split is 4 and 4. The delay falls from 18 to $16\,\tau_{inv}$16τinv​. $F = 2 \times 8 \times 4 \times 4 = 256$ and $4 \times 256^{1/4} = 16$16: yes, all four gains are now $256^{1/4} = 4$4.

4. How many stages?

The idea. When the load is large, adding inverters (logical effort 1) lowers the gain each stage must provide. The best gain per stage is $e \approx 2.7$2.7; with drain capacitance it moves toward 4. That is why designers aim for 3–4 per stage, and why FO4 is the standard yardstick.

Lecture08 @ 18:26N inverters of gain α from C_in to C_out: Delay = ln(C_out/C_in) α τ_inv / ln α, minimized at ln α = 1, α = e; 'α ≈ 3', pushed toward 4 (right).

Adding stages can help

So far $N$ was fixed. But you can add stages, and with a very large load that can reduce the delay (12:39). The stages to add are inverters: their logical effort is 1, so they don’t increase $G$ (13:07). For the analysis the lecturer uses a chain of inverters only; the result carries over to any path (13:59).

The best gain per stage (board, 14:21–17:37)

1. $N$ inverters from $C_{in}$ to $C_{out}$Cout​, each with the same gain $\alpha$ (the best choice, Section 3) board.
2. All $g = 1$1, so $F = \alpha^N = C_{out}/C_{in}$ board.
3. Take logs: $N\ln\alpha = \ln(C_{out}/C_{in})$ln(Cout​/Cin​), so $N = \dfrac{\ln(C_{out}/C_{in})}{\ln\alpha}$ board.
4. The delay is $N\alpha\,\tau_{inv}$ board. Substitute $N$N: $\text{Delay} = \ln\!\left(\dfrac{C_{out}}{C_{in}}\right)\dfrac{\alpha}{\ln\alpha}\,\tau_{inv}$ board.
5. Only $\alpha/\ln\alpha$ depends on $\alpha$α. Its derivative is $\dfrac{\ln\alpha - 1}{(\ln\alpha)^2}$ added; setting it to zero board: $\ln\alpha = 1$1, $\alpha = e \approx 2.7$2.7.

“So basically alpha is around three” (17:25). Two refinements (17:37–18:58):

• The analysis ignores drain capacitance. With it, the best gain “creeps up to be something closer to four”, and that is why FO4 is the metric: in a delay-optimized design, each stage has a gain of about four board (“α ≈ 3 ↑ 4”).
• The minimum is shallow: 3.5, 4 or even 4.2 make little difference. Tune each stage’s gain to roughly 3–4, then choose the number of stages that achieves it.

How shallow? added The factor $\alpha/\ln\alpha$ is 2.72 at $\alpha = e$e, 2.73 at 3, 2.89 at 4 (6% more) and also 2.89 at 2, but 3.35 at 6 (23% more). Too few stages costs more than one too many.

In practice. added With $\alpha = e$ the best count is about $N = \ln F$lnF. Then pick a count the logic allows: inverters added to a path must come in pairs, or the function is inverted. Compare $N F^{1/N}$ for the candidates; the widget of Section 6 plots this curve for the lecture’s example.

Check yourself An inverter chain must drive a load 1000 times its input capacitance. How many stages minimize the delay, what is the gain per stage, and how much slower are 4 stages?

$\ln 1000 = 6.9$6.9, so about 7 stages. With 7: gain $1000^{1/7} = 2.68$2.68, delay $7 \times 2.68 = 18.8\,\tau_{inv}$18.8τinv​. With 6: $6 \times 3.16 = 19.0$19.0; with 8: $8 \times 2.37 = 19.0$19.0; with 4: $4 \times 5.62 = 22.5\,\tau_{inv}$22.5τinv​, 20% slower. Near the optimum the curve is flat.

5. A worked example: estimating a path

The idea. The lecture’s example path, sized arbitrarily: compute each stage’s gain from its normalized inverter, add them, and multiply by $\tau_{inv}$τinv​. One badly sized stage dominates.

Lecture08 @ 29:52The example as drawn: inverter 2.4/1.2 (fixed), NAND all 1.2 µm, NOR 1.2/4.8 µm, 1 pF = 500 µm; delay = τ_inv{500/3.6 + 6/1.8 + 2.4/3.6} = 6.86 ns; F = 308, ∛F = 6.76, and 3(6.76)τ_inv = 973 ps (top).

Fair copy of the board above (Lecture08 @ 29:52), mark for mark in its own layout. Black is the circuit: the blue pen, with the device widths in pink. Teal is the cyan pen, the working laid over the circuit: the circle and “Fixed → $C_{in}$Cin​”, the stage numbers, the normalized inverters drawn beside the NAND and the NOR, the FO1 pair at the bottom left that sets $\tau_{inv}$τinv​, the delays, $F$ and $f$f. The inverter and the NAND, which the lecturer blocks at 29:52, are read from 29:07 and 30:44. † The board truncates $F = 308.6$ to 308; $\sqrt[3]{F} = 6.76$ either way.

The circuit

The path (20:01–21:52) board:

1. an inverter 2.4/1.2 µm. Its size is fixed: it sets the path’s input capacitance $C_{in}$ (21:48);
2. a NAND with all four devices 1.2 µm;
3. a NOR with NFETs 1.2 µm and PFETs 4.8 µm (twice 2.4 µm, because they are a stack of two);
4. a load of 1 pF.

“These are just random size choices, and we’ll see how they’re terrible” (21:33).

The gains

“If this were a normal class, the first thing I would be asking is what does one picofarad convert to in microns” (22:10). At $C_g = 2\,\mathrm{fF/\mu m}$2fF/μm, 1 pF is 500 µm of gate board.

Gains from the normalized inverters (board, 23:11–25:05)

1. NOR (stage 3). Its NFETs (1.2 µm, one at a time) and its PFET stack (two 4.8 µm devices act like 2.4 µm) give the normalized inverter 2.4/1.2, input 3.6 µm board. It drives 500 µm: gain $f_3 = 500/3.6 = 138.9$138.9.
2. NAND (stage 2). Its NFET stack (two 1.2 µm act like 0.6 µm) and one PFET (1.2 µm): normalized inverter 1.2/0.6, input 1.8 µm board. It drives one NOR input, $4.8 + 1.2 = 6\,\mu\mathrm{m}$6μm: gain $f_2 = 6/1.8 = 3.33$3.33.
3. Inverter (stage 1). It is already an inverter, input 3.6 µm. It drives one NAND input, $1.2 + 1.2 = 2.4\,\mu\mathrm{m}$2.4μm: gain $f_1 = 2.4/3.6 = 0.667$0.667.

The delay

The technology (25:20) board: $C_g = 2\,\mathrm{fF/\mu m}$ and $R_{nfet} = 8\,\mathrm{k\Omega\cdot\mu m}$8kΩ⋅μm, so $R_{pfet} = 16\,\mathrm{k\Omega\cdot\mu m}$ for a perfect 2:1 ratio. The FO1 delay doesn’t depend on the inverter’s size (“a 2000 over 1000 or 2 over 1, fan out of 1 is fan out of 1”, 26:15):

$$\tau_{inv} = C_g(3)\frac{R_{nfet}}{1} = 3R_{nfet}C_g$$ $$\tau_{inv} = 3 \times 8 \times 2 = 48\,\mathrm{ps}.$$

Delay as drawn (board, 26:51–27:13)

1. Sum of the gains: $138.9 + 3.33 + 0.667 = 142.9$142.9.
2. Delay $= 142.9 \times 48\,\mathrm{ps} = 6.86\,\mathrm{ns}$ board.

The last term dominates (27:13): the NOR “is struggling to drive this 500 microns. It just doesn’t have the drive strength.” This is a poorly tuned path.

Common mistakes.

• Forgetting to convert the load to microns of gate (or to µm at the right $C_g$Cg​).
• Using the NOR’s own input (6 µm) instead of its normalized inverter’s (3.6 µm) for its gain.

Check yourself In the lecture's path, make only the NOR 10 times larger (NFETs 12 µm, PFETs 48 µm). What are the three gains and the delay?

NOR: normalized inverter 24/12, input 36 µm, gain $500/36 = 13.9$13.9. NAND: it now drives $48 + 12 = 60\,\mu\mathrm{m}$60μm, gain $60/1.8 = 33.3$33.3. Inverter: still $0.667$0.667. Total $47.9\,\tau_{inv} = 2.30\,\mathrm{ns}$2.30ns: much better than 6.86 ns, but the NAND is now the bottleneck. Every stage has to grow together.

6. Resizing for equal gains

The idea. Compute $F$F, take its $N$-th root, and size the gates one at a time from the load back to the fixed first gate, giving each the same gain.

The target

The path effort can be computed two ways (27:40–29:25) board: as the product of the three gains, or as $G \cdot H$H:

$$F = f_1f_2f_3 = \left(\frac{500}{3.6}\right)\left(\frac43\right)\left(\frac53\right) = 308.$$

added The product of the gains as drawn, $138.9 \times 3.33 \times 0.667$0.667, is also 308.6: $F$ doesn’t depend on the sizes. Each stage should have the gain board

$$f = \sqrt[3]{F} = 6.76,$$

and the delay becomes $3(6.76)\,\tau_{inv} = 973\,\mathrm{ps}$ board: “from almost seven nanoseconds all the way down to less than one nanosecond” (29:52). (At 28:58 the lecturer says “the cube root of this winds up being 308”; 308 is $F$ itself.)

Lecture08 @ 35:35Resizing from the load back: NOR NFETs 24.7 µm, PFETs 98.8 µm; NAND all 12.2 µm; the check 6.76 = 2(12.2 µm)/3.6 µm (left).

Working back from the load

“We’re gonna do this by starting from the last stage in the path and working our way back” (30:27). For each stage, size its normalized inverter for a gain of 6.76, then translate that into the gate’s devices.

Resizing (board, 31:37–35:29)

1. NOR. Its normalized inverter must have input $500/6.76 = 74.0\,\mu\mathrm{m}$74.0μm. A third of that is the NFET board: $\dfrac{500}{(6.76)(3)} = 24.7\,\mu\mathrm{m}$24.7μm, with a 49.3 µm PFET.
2. Translate to the NOR: its NFETs have the normalized inverter’s pull-down strength, 24.7 µm each; its PFETs are a stack of two, so each is twice 49.3, 98.8 µm (“4 times 24.7”) board.
3. NAND. It now drives one NOR input: $24.7 + 98.8 = 123.5\,\mu\mathrm{m}$ board. Its normalized NFET is $\dfrac{123.5}{(6.76)(3)} = 6.1\,\mu\mathrm{m}$ (PFET 12.2 µm) board.
4. Translate: the NAND’s NFETs are a stack of two, so each is twice 6.1, 12.2 µm; each PFET matches the normalized PFET, 12.2 µm. All four devices are 12.2 µm board.
5. The inverter. “Trick question. I don’t” resize it (34:56): its input capacitance is fixed.
6. Check board: the inverter drives one NAND input, $2(12.2) = 24.4\,\mu\mathrm{m}$24.4μm, and its own input is 3.6 µm: $24.4/3.6 = 6.78 \approx 6.76$6.76. “If it’s not, I did something wrong” (35:29).

added Without rounding: NOR NFETs 24.66 µm, PFETs 98.65 µm; NAND 12.16 µm; the check gives exactly 6.758. The NOR grew 20 times and the NAND 10 times: the gate driving the big load had to grow, so the gate driving it had to grow too (35:29).

Try it: start from “as drawn”, then press “sized, 3 stages”. Change the load and watch every width follow it while the fixed first inverter stays put.

as drawn (20:01)sized, 3 stagessized, 5 stagessized, 7 stagessized, 9 stages

added inverters:next to the loadafter the first inverter

load C_L (lecture: 1 pF)

1.0 pF

stage	gate	widths, µm (P/N)	gain
1 (fixed)	inverter	2.40/1.20	0.67
2	NAND2	all four 1.20	3.33
3	NOR2	N 1.20, P 4.80	138.89
load			500 µm

path effort F = G·H

308.6

F^1/N with N = 3

6.758

delay Σ gains

142.89 τ_inv

delay at τ_inv = 48 ps

6859 ps

total transistor width

20 µm

Dots are the stage counts the path can have (3 plus pairs of inverters); the curve is the delay if every stage had the same gain F^1/N. "As drawn" sits far above it: its gains are unequal. F doesn't change with sizing or with where the inverters go, so the sized delay is the same in either place; the total width is not. Gate loading only, as in the lecture.

What to notice.

• As drawn, the gains are 0.67, 3.33 and 138.9: far from equal. Sized, all three are 6.76, and the delay drops from 142.9 to 20.3 $\tau_{inv}$τinv​.
• $F$ is 308.6 in every sizing: only the gate types and the two end capacitances set it.
• The dots on the curve are the delays you can actually have with 3, 5, 7 or 9 stages (Section 7).

Common mistakes.

• Resizing the first gate. Its input capacitance is the constraint that makes the problem well posed.
• Dividing by 3 and stopping. That gives the normalized inverter’s NFET; a stacked network then doubles (NAND NFETs, NOR PFETs).
• Starting from the input end. You only know each gate’s load once the next gate is sized, so work back from the load.

Check yourself Size the path of the check in Section 2 (NAND2 all 2 µm, fixed; NOR2; inverter; 360 µm of gate) for minimum delay. Give the inverter's and the NOR's devices, and check the NAND's gain.

$f = 5.85$5.85. Inverter: input $360/5.85 = 61.6\,\mu\mathrm{m}$61.6μm, so 41.0/20.5 µm. NOR: it drives 61.6 µm, so its normalized input is $61.6/5.85 = 10.5\,\mu\mathrm{m}$10.5μm, NFET $3.51\,\mu\mathrm{m}$3.51μm; the NOR’s NFETs are 3.51 µm and its PFETs $4 \times 3.51 = 14.0\,\mu\mathrm{m}$14.0μm; its input is 17.5 µm. NAND: normalized inverter 2/1 µm (input 3 µm), so its gain is $17.5/3 = 5.85$5.85. ✓ Delay $3 \times 5.85 = 17.5\,\tau_{inv}$17.5τinv​.

Check yourself Equal-strength technology: τ_inv = 50 ps, C_g = 1 fF/µm. A path is an inverter 1/1 µm (fixed), a NAND2, an inverter, and 400 fF. Find F, the stage gain, the delay, and the sizes.

With equal strengths the normalized inverter is W/W and $g_{NAND2} = 3/2$3/2. $H = 400\,\mu\mathrm{m}/2\,\mu\mathrm{m} = 200$200, $F = \tfrac32 \times 200 = 300$300, $f = 300^{1/3} = 6.69$6.69, delay $3 \times 6.69 \times 50 = 1004\,\mathrm{ps}$1004ps. Last inverter: input $400/6.69 = 59.8\,\mu\mathrm{m}$59.8μm, so 29.9/29.9 µm. NAND: normalized input $59.8/6.69 = 8.93\,\mu\mathrm{m}$8.93μm, so $W = 4.46\,\mu\mathrm{m}$4.46μm: NFETs $2W = 8.93$8.93, PFETs $4.46\,\mu\mathrm{m}$4.46μm, input 13.4 µm. Check: $13.4/2 = 6.69$6.69. ✓ (MT23-5b works in this convention; its key prints “1244.7 ns” for about 1.24 ns.)

7. Adding stages, and where to put them

The idea. With a gain of 6.76 the path has too few stages. Two more inverters bring the gain to 3.15 and the delay to 756 ps. Where they go doesn’t change the delay, but next to the load they save a great deal of transistor width.

Lecture08 @ 40:25F = 308, ∛F = 6.76, ⁵√F = 3.15; Delay = 5(3.15) τ_inv = 756 ps, with the two added inverters drawn next to the 1 pF load.

Five stages

The gain 6.76 is “certainly higher than 3 to 4” (36:19). The path effort is still 308; it didn’t change during the resizing (36:55). Take the fifth root instead (37:01) board:

$$\sqrt[5]{F} = 3.15$$ $$\text{Delay} = 5(3.15)\,\tau_{inv} = 756\,\mathrm{ps}.$$

More than 200 ps faster than three stages, by adding two inverters (37:18). added Unrounded, $\sqrt[5]{308.6} = 3.147$ and the delay is 755 ps. Comparing stage counts for this $F$F: 3 stages 973 ps, 5 stages 755 ps, 7 stages 762 ps, 9 stages 817 ps. Five is the best count the logic allows; $\ln 308.6 = 5.7$ is where the gain would be exactly $e$e.

Where the inverters go

“From a delay point of view, I could have put them either place” (38:19): next to the load, or between the first inverter and the NAND. $F$ and $N$ are the same, so the delay is the same. But next to the load is “vastly superior … from a power perspective” (39:06):

• the gates closest to the big load are the largest;
• if those are inverters, they are single devices; if they are the NAND and NOR, their big devices come in stacks, doubled in width;
• so the total device width is smaller with the inverters at the load, and with it the area and, above all, the dynamic power of switching the path (40:05).

added The widget above has the numbers: choose “sized, 5 stages” and switch between the two placements. The total transistor width is 289 µm with the inverters next to the load and 805 µm with them after the first inverter, for the same 755 ps. added (Fall 2026 adds the other side of the same trade: a path with slack can be made smaller to save power.)

Sizing the five stages

Lecture08 @ 42:25The board's sizing of the added inverters: 500/((3.15)(3)) = 16.8 µm, then 3(16.8 µm)/((3.15)(3)) = 5.32 µm. The first division is an arithmetic slip: 500/9.45 = 52.9 µm (see the steps).

The procedure is the same as before: work back from the load, each normalized NFET being (load)/(3.15 × 3). The board starts the chain but has an arithmetic slip (41:26): $500/((3.15)(3))$ is 52.9 µm, not 16.8 µm. The board’s 16.8 µm is in fact the NFET of the next inverter back, and its 5.32 µm the NOR’s normalized NFET. The corrected chain:

Five stages, corrected (board procedure, 40:46–42:36)

1. Last inverter: NFET $\dfrac{500}{(3.15)(3)} = 52.9\,\mu\mathrm{m}$52.9μm, so 105.8/52.9 µm; its input is 158.7 µm.
2. The inverter before it: NFET $\dfrac{3(52.9)}{(3.15)(3)} = 16.8\,\mu\mathrm{m}$16.8μm, so 33.6/16.8 µm; input 50.4 µm.
3. NOR: normalized NFET $\dfrac{3(16.8)}{(3.15)(3)} = 5.33\,\mu\mathrm{m}$ (the board’s 5.32); NFETs 5.33 µm, PFETs $4 \times 5.33 = 21.3\,\mu\mathrm{m}$21.3μm; input 26.7 µm.
4. NAND: normalized NFET $\dfrac{26.7}{(3.15)(3)} = 2.82\,\mu\mathrm{m}$2.82μm; all four devices $2 \times 2.82 = 5.64\,\mu\mathrm{m}$5.64μm; input 11.3 µm.
5. Check: the fixed inverter’s gain is $11.3/3.6 = 3.13 \approx 3.15$3.15. ✓

“And I can keep repeating this … you can figure out how to do the rest” (42:36). The lecture moves on before finishing the chain; the steps above finish it. The widget of Section 6 (“sized, 5 stages”) uses the unrounded gain 3.147, so its widths differ in the last digit: 106/53.0, 33.7/16.8, NOR 5.35/21.4, NAND 5.66 µm.

Common mistakes.

• Adding an odd number of inverters: the path’s logic function flips.
• Dividing by the gain twice (the board’s slip). Each step divides the stage’s load by $f$ once, then by 3 for the NFET.

Check yourself HW3-3 has a path with F = 555.6 and τ_inv = 24 ps. Compare 3, 5, 7 and 9 stages. Which is best?

$N F^{1/N}$NF1/N: 3 stages $3 \times 8.22 = 24.7$24.7, 5 stages $5 \times 3.54 = 17.7$17.7, 7 stages $7 \times 2.47 = 17.3$17.3, 9 stages $9 \times 2.02 = 18.2\,\tau_{inv}$18.2τinv​. In picoseconds: 592, 425, 414 and 436 ps. Seven stages (four added inverters) is best, at a gain of 2.47 per stage, close to $e$e; $\ln 555.6 = 6.3$6.3. (HW3-3b; its 7-stage row prints 555.7 and “× 3”, typos for 555.6 and × 7.)

8. Branching effort

The idea. When a gate also drives something off the path, the product of the electrical efforts no longer telescopes. A branching factor appears, and because it contains the sizes of the gates, the path effort is no longer fixed.

Lecture08 @ 47:38A capacitance C_x off stage 2's output: Π h_i = (C_L/C_in) × (C_in3 + C_x)/C_in3, the branching effort.

So far every gate drove exactly one other gate, and that is what made $F$ a constant (43:05). With fan-out, “when we resize, we’re actually gonna change … the path effort” (43:52).

The branching effort (board, 44:13–46:41)

1. The same path, now with a capacitance $C_x$ (the fan-out) also hanging off stage 2’s output board.
2. Stage 2 drives $C_{in3} + C_x$Cx​, so $h_2 = (C_{in3} + C_x)/C_{in2}$Cx​)/Cin2​.
3. $\prod h_i = \dfrac{C_L}{C_{in4}} \times \dfrac{C_{in4}}{C_{in3}} \times \dfrac{C_{in3} + C_x}{C_{in2}} \times \dfrac{C_{in2}}{C_{in}}$ board.
4. Everything cancels except one factor board: $\prod h_i = \dfrac{C_L}{C_{in}} \times \dfrac{C_{in3} + C_x}{C_{in3}}$Cin3​Cin3​+Cx​​.
5. The extra factor is the branching effort (46:41) board, in “the Sutherland and Sproull formalism”.

The trouble (46:58): the branching effort depends on the sizing. It contains $C_{in3}$Cin3​, the size of stage 3. So $F$ is no longer a constant, and the gains of the best design are no longer all equal (47:24). If $C_x \to 0$ the factor becomes 1 and we are back to Sections 2–7.

Branching effortboard

$$b = \frac{C_{in3} + C_x}{C_{in3}} = \frac{C_{on} + C_{off}}{C_{on}}$$$$F = G\,H\,B, \qquad B = \prod b$$

Holds when: one off-path load C_x at the output of the stage that drives C_in3; gate loading only. The general product B over every branch is added

Worked example. added Take the 3-stage path of Section 6 as sized (NAND all 12.16 µm, NOR NFETs 24.66 µm, PFETs 98.65 µm) and hang 100 µm of extra gate on the NAND’s output. The NAND now drives $123.3 + 100 = 223.3\,\mu\mathrm{m}$ against a normalized inverter of $3 \times 6.08 = 18.25\,\mu\mathrm{m}$18.25μm: its gain jumps from 6.76 to 12.24. The others are unchanged: delay $6.76 + 12.24 + 6.76 = 25.8\,\tau_{inv} = 1.24\,\mathrm{ns}$1.24ns, up from 973 ps. The branching effort is $223.3/123.3 = 1.81$1.81, and $F = 308.6 \times 1.81 = 559$559.

Common mistakes.

• Leaving the branch out of the stage’s load. The gain uses the total capacitance the stage drives.
• Taking $F^{1/N}$ with $F$ from the old sizes and treating it as exact. It is a reasonable first guess, but $F$ moves as soon as you resize the stage after the branch.

Check yourself In a path, a stage drives the next gate's input of 20 µm and also a 100 µm branch. What is its branching effort? If the next gate is made 30 µm, what does it become?

$b = (20 + 100)/20 = 6$6. With 30 µm: $b = 130/30 = 4.33$4.33. Making the on-path gate bigger makes the branch a smaller fraction of the load, so $b$ (and $F$F) falls. These are the numbers of the lecture’s example in Section 9.

9. Retuning a path with a branch

The idea. With a heavy branch, equal gains are not the best. Enlarge the gate just after the branch: its gain drops a lot, while the gate driving the branch, whose load is mostly the branch, slows only a little. Then rebalance the neighbours.

Lecture08 @ 50:33The branch example: NOR (NFETs 5, PFETs 20), inverter 26/13 with a 200 fF (100 µm) branch, NOR (NFETs 4, PFETs 16), inverter 22.2/11.1, and a 200 fF (100 µm) load.

The circuit, with every gain about 3

The example (48:34–50:20) board, at $C_g = 2\,\mathrm{fF/\mu m}$2fF/μm:

1. a NOR, NFETs 5 µm, PFETs 20 µm (fixed);
2. an inverter 26/13 µm, whose output also drives a 200 fF branch, 100 µm of gate;
3. a NOR, NFETs 4 µm, PFETs 16 µm;
4. an inverter 22.2/11.1 µm, driving 200 fF, 100 µm.

The sizes were chosen so that every gain is about 3, “and this is 2.7, close to 3” (50:20). “With all the analysis I’ve done today”, that should be optimal, yet it isn’t, “because of the presence of this branching” (50:48). The board’s delay is 11.7 τ_inv.

The gains as drawn (added, from the board's widths)

1. Inverter 4: drives 100 µm; its input is $22.2 + 11.1 = 33.3\,\mu\mathrm{m}$33.3μm: gain $100/33.3 = 3.00$3.00.
2. NOR 3: drives 33.3 µm; normalized inverter 8/4 (PFET stack of two 16 µm acts like 8 µm), input 12 µm: gain $33.3/12 = 2.78$2.78.
3. Inverter 2: drives NOR 3’s input, $4 + 16 = 20\,\mu\mathrm{m}$20μm, plus the 100 µm branch: $120/39 = 3.08$3.08.
4. NOR 1: drives inverter 2’s 39 µm; normalized inverter 10/5, input 15 µm: gain $39/15 = 2.60$2.60.
5. Sum: $2.60 + 3.08 + 2.78 + 3.00 = 11.45\,\tau_{inv}$11.45τinv​. The board’s 11.7 is $2.7 + 3 + 3 + 3$3, each gain rounded.

Step 1: enlarge the gate after the branch

“If I size this guy up” (51:42) board: NOR 3’s NFETs 4 → 6 µm, PFETs 16 → 24 µm. Its input grows from 20 to 30 µm, but inverter 2’s load only grows from 120 to 130 µm, because most of it is the branch.

Stage	Board	As drawn (added)
NOR 3: $33.3/18$	3 → 1.83	2.78 → 1.85
inverter 2: $130/39$	3 → 3.25	3.08 → 3.33
delay	11.7 → 10.74 τ_inv	11.45 → 10.79 τ_inv

“I’m able to drop this gain far more than I increase this gain” (52:00). How far you can go depends on the branch compared with the on-path input; you could do it “analytically and exactly”, but “usually you just sort of look at it” (52:20–53:19).

Step 2: rebalance

Now NOR 3 (1.85) and inverter 4 (3.00) are unequal, with nothing branching between them, so balance them (53:19) board: inverter 4 from 22.2/11.1 to 30/15 µm. Its input is 45 µm, so NOR 3’s gain rises to $45/18 = 2.50$ and inverter 4’s falls to $100/45 = 2.22$2.22. The delay drops a little further, to 10.63 τ_inv on the board, 10.66 with the widths as drawn. (The board and the speech say 2.27 for inverter 4; $100/45 = 2.22$2.22, and the board’s 10.63 itself uses 2.22.)

Lecture08 @ 55:06Both steps: NOR 3 to 24/6, then inverter 4 to 30/15; gains 3 → 3.25, 3 → 1.83 → 2.5, 3 → 2.27 (2.22); delays 11.7 → 10.74 → 10.63 τ_inv.

“Whenever I have a fan-out like this … I have the ability now to size this up, reducing its gain substantially without increasing the gain of this by very much … then if I created situations where the gains have become more unequal here, I can resize to balance those out” (54:22). That is the recipe. The lecture gives no exact method (54:22), and neither does this chapter; the widget shows how far it can go.

added The board’s gains 3.25 and 2.7 fit inverter 2 taken as 26.7/13.3 µm (input 40 µm, the size for a gain of exactly 3 on its 120 µm load: $130/40 = 3.25$3.25, $40/15 = 2.67$2.67) rather than the 26/13 it writes, and its totals are sums of rounded gains: $2.66 + 3.25 + 1.83 + 3 = 10.74$ and $2.66 + 3.25 + 2.5 + 2.22 = 10.63$10.63. Either way the lesson is the same.

board start (50:20)step 1: NOR → 24/6 (51:42)step 2: inverter → 30/15 (53:46)best (added)

inverter 2, NFET (PFET 2×)

13.0 µm

NOR 3, NFETs (PFETs 4×)

4.0 µm

inverter 4, NFET (PFET 2×)

11.1 µm

branch C_x at inverter 2

100 µm

delay Σ gains

11.45 τ_inv

branching b = (C_in3 + C_x)/C_in3

6.00

path effort F = G·H·b

66.7

4F^1/4 (equal gains at this F)

11.43 τ_inv

best possible, first NOR fixed (added)

9.81 τ_inv

G = (5/3)(1)(5/3)(1) and H = 100 µm/25 µm stay fixed; only the branching factor b moves, so F moves with the NOR's size. The board rounds its gains: it writes 11.7, 10.74 and 10.63 τ_inv where the widths as drawn give 11.45, 10.79 and 10.66. Gate loading only, R_pfet = 2R_nfet.

What to notice.

• Press the two steps in turn: the orange bar (the stage driving the branch) barely moves while the NOR’s bar collapses.
• Keep enlarging NOR 3: the delay keeps falling until about NFETs 9.3 µm (10.55 τ_inv), then rises again; “at some point it’s not going to work anymore” (53:19).
• The branching factor falls as NOR 3 grows, and with it $F$F: unlike Sections 2–7, $F$ is not a constant here.
• “Best” added lets every gate after the first move at once: 9.81 τ_inv, with inverter 2 grown to 34/17 µm. The best gains are not equal (3.43, 3.43, 1.48, 1.48): the two stages before the branch share one value, the two after it a smaller one.
• Set the branch to 0: $b = 1$1, $F$ returns to $G \cdot H = 11.1$11.1, and “best” gives four equal gains, $4 \times 11.1^{1/4} = 7.30\,\tau_{inv}$7.30τinv​, as in Section 3.

Common mistakes.

• Equalizing all the gains anyway. With a branch, equal gains are no longer optimal.
• Resizing the stage that drives the branch so that its own gain is back to normal, and stopping there. Its input grows, so the gain moves to the stage before it; the total barely changes (MT17-5d’s trap; next check).
• Forgetting that resizing a gate changes its predecessor’s load: recompute both gains after every change.

Check yourself In the lecture's branch example (start sizes), make NOR 3's NFETs 8 µm (PFETs 32 µm) instead of 6. What are the new gains and delay? And with 12 µm?

8 µm: NOR 3’s input is 40 µm, normalized 24 µm. Inverter 2: $140/39 = 3.59$3.59; NOR 3: $33.3/24 = 1.39$1.39; the others 2.60 and 3.00. Total $10.58\,\tau_{inv}$10.58τinv​, better than the 6 µm step. 12 µm: inverter 2 $160/39 = 4.10$4.10, NOR 3 $33.3/36 = 0.93$0.93, total $10.63\,\tau_{inv}$10.63τinv​: worse again. The best single change is near 9.3 µm (10.55).

Check yourself A chain of four inverters has inputs 3, 12, 48 and 192 µm (the first fixed) and drives 768 µm: every gain is 4. A 96 µm branch is added at the second inverter's output. What is the delay? A designer resizes the second inverter so that its gain is 4 again. What is the delay now? What would help?

With the branch the second inverter drives $48 + 96 = 144\,\mu\mathrm{m}$144μm: gain 12, total $4 + 12 + 4 + 4 = 24\,\tau_{inv}$24τinv​. Resizing it to gain 4 makes its input $144/4 = 36\,\mu\mathrm{m}$36μm, so the first inverter’s gain becomes $36/3 = 12$12: still 24. The excess just moved one stage back. Better: balance the first two stages, input $x = \sqrt{3 \times 144} = 20.8\,\mu\mathrm{m}$20.8μm, gains 6.93 and 6.93, total $21.9\,\tau_{inv}$21.9τinv​. Letting the later gates grow too, as the lecture does, reaches about $21.5\,\tau_{inv}$21.5τinv​. (MT17-5d’s key falls into this trap.)

10. Stacks: why the bottom device is slow

The idea. The delay model describes the device at the top of a stack, nearest the output. A device lower down must first discharge the internal node above it before the output can move, and the penalty grows roughly as the square of the stack height.

Lecture08 @ 58:54A NAND with single input changes: A switching with B = 1 behaves like an inverter; with the bottom device switching, the internal node starts near V_DD − V_T and the top device is cut off. Delay ∼ n².

Everything so far assumes single input changes (55:44) board, and “all of this delay modelling … really only applies to the top device in the stack” (55:13). Take a NAND pulling its output Y down through its two NFETs.

Two ways to pull the NAND down (board, 55:57–58:33)

1. B = 1, A switches 0 → 1 (A is the top device, nearest Y). The bottom device is already on; A turns on and discharges Y with its saturated current, then in triode. “That’s very similar to the inverter”: the delay model is accurate (56:17).
2. A = 1, B switches 0 → 1 (B is the bottom device). Before the switch, the node between them was charged through A from the high output. An NFET stops conducting when its gate is only $V_T$ above its source, so the node sits near $V_{DD} - V_T$ and A is cut off board (57:20).
3. When B turns on it must first pull the internal node below $V_{DD} - V_T$VT​. Only then does A turn on and start discharging Y (57:42).
4. So the bottom device’s delay includes discharging the internal node first: it is slower.

The further down the stack, the slower: “that delay degradation of the bottom device on the stack will go something like the square of the height of the stack” (58:33) board, written Delay ∼ n². The lecture gives no derivation, and neither does this guide. That is why stacks are “yucky” (56:47): two is fine and unavoidable for complex functions, three deserves “a bit of an askance glance”, and beyond three you should break the gate up.

Back to Chapter 7. added This is the reason Lecture 7 promised (Chapter 7, pin swapping): the device nearest the output switches fastest, so a late-arriving signal should drive the input nearest the output. The early inputs have already set the lower devices, and the internal nodes are already discharged when the late signal arrives.

Check yourself A 4-input NAND has inputs A (nearest the output) to D (nearest ground). Three inputs are already 1 and the fourth rises. Which input gives the longest delay, and why? Which should get the latest signal?

D, at the bottom. With A, B and C at 1, the three internal nodes above D have been charged to about $V_{DD} - V_T$ through the conducting devices, while D was off. When D rises it must discharge all three nodes before the output can fall; the penalty grows roughly as $n^2$n2. The latest signal should go to A: with B, C and D already on, the nodes below A are already at ground and A switches like an inverter. (MT17-3d asks for this explanation.)

Check yourself Why does the internal node of the NAND sit near V_DD − V_T, and not at V_DD, when A = 1 and B = 0?

It is charged through the top NFET from the output at $V_{DD}$VDD​. The NFET’s source is the internal node; as that node rises, the device’s gate-to-source voltage $V_{DD} - V_X$ shrinks, and when it reaches $V_T$ the device turns off. The node stops near $V_{DD} - V_T$ (Chapter 5’s body effect raises $V_T$ a little, so it stops slightly lower).

What comes next (59:06). Lecture 9 turns to layout: design rules and stick diagrams (Chapter 9).

On the exam

Path sizing is on every past paper: Question 5 of three midterms (MT23, MT21 and MT17: 40, 35 and 40 of 150 points) and one question on each of the four finals (20 to 35 points of 200 or 250). Each part below links its full solution; the exam-way twin and the path-sizing card exist so far for MT23-5.

Section	Past-paper parts (points)	What they ask
§1 gain from the normalized inverter; §5 estimating a path	MT23-5a (10), MT17-5a (10), FN19-8a (10), FN10-9a (10), FN12-8a (15)	the delay of a path as drawn: every gain, then $\tau_{inv}$ times their sum
§2 path delay and path effort; §3 equal gains; §6 resizing	MT23-5b (10), MT17-5b (10), MT21-5a (15), FN17-7a (8 or 10, illegible), FN19-8b (15), FN10-9b (14), FN12-8b (15); with Chapter 12, MT24-5c (20)	$F = GH$GH, $f = F^{1/N}$F1/N, the widths sized back from the load, the new delay
§4 how many stages; §7 adding stages	HW3-3b (homework); M7 Question 5c (10, practice)	compare $NF^{1/N}$ for the stage counts the logic allows
§8 branching effort	MT23-5c (10), MT17-5c (10), FN19-8c (10)	the delay with a side load at fixed sizes: only the gain of the stage driving that node changes
§9 retuning around a branch	MT23-5d (10), MT17-5d (10), MT21-5b (20), FN17-7b (12)	rebalance the overloaded pair, then trade the two sides of the branch
§10 stacks	MT17-3d (8)	why the bottom device of a stack is slow, and which input gets the late signal

Memorize.

• Gain $=$ the load $\div$ the normalized inverter’s input $= g \cdot h$h. With $R_{pfet} = 2R_{nfet}$2Rnfet​: $g_{inv} = 1$1, $g_{NAND2} = \tfrac43$34​, $g_{NOR2} = \tfrac53$35​. With equal strengths: $g_{NAND2} = g_{NOR2} = \tfrac32$23​. AOI22 and OAI22: $g = 2$ either way.
• $\text{Delay} = \tau_{inv}\sum f_i$τinv​∑fi​; $F = \prod f_i = GH$ when nothing branches, $F = GHB$ when something does.
• $f = F^{1/N}$ and $\text{Delay}_{min} = N\,F^{1/N}\,\tau_{inv}$NF1/Nτinv​, when $F$ is fixed (no branch, $C_{in}$ and $C_L$ fixed).
• The best gain per stage is about $e$e, 3–4 in practice; about $\ln F$ stages; add inverters in pairs, next to the load.
• $b = (C_{on} + C_{off})/C_{on}$Coff​)/Con​. A branch makes $F$ depend on the sizes, and the best gains are then unequal.
• The bottom device of a stack is the slowest (Delay $\sim n^2$n2); the latest signal goes to the input nearest the output.

Derive (each in about three lines).

• The gain from the normalized inverter. The gate pulls down like its normalized inverter’s NFET, $R_{nfet}/W$Rnfet​/W, so its delay is $(R_{nfet}/W)\,C_{out}$(Rnfet​/W)Cout​. With $\tau_{inv} = 3R_{nfet}C_g$ that is $C_{out}/(3WC_g) \cdot \tau_{inv}$τinv​: the load over the normalized input $3W$ (Section 1).
• Equal gains. Two stages: $\text{Delay}/\tau_{inv} = f_2 + F/f_2$F/f2​; the derivative is zero at $f_2 = \sqrt F = f_1$f1​; for $N$ stages each neighbouring pair keeps a fixed product when the gate between them is resized, so all gains are equal (Section 3).
• The best gain per stage. $N = \ln(C_{out}/C_{in})/\ln\alpha$ln(Cout​/Cin​)/lnα, so $\text{Delay} = \ln(C_{out}/C_{in})\,\dfrac{\alpha}{\ln\alpha}\,\tau_{inv}$ln(Cout​/Cin​)lnαα​τinv​; the derivative of $\alpha/\ln\alpha$ is zero at $\ln\alpha = 1$1, $\alpha = e$ (Section 4).
• Sizing back from the load. The last stage’s normalized NFET is $C_{out}/(3f)$Cout​/(3f); double each device that sits in a stack of two; the result is the next stage’s load (Section 6).

Method card. Every path-sizing question follows the path-sizing card of the playbook: recognize the picture, tabulate the stages, then (a) the delay as drawn, (b) equal gains sized back from the load, (c) the side load on one stage, (d) a retuning by pairs.

Formulas to remember

Formula	Meaning
gain $= C_{out}/C_{in,\,\text{norm. inv.}} = g \cdot h$	the normalized inverter has the gate’s drive; input $3W$ ($2W$2W for equal strengths)
$\text{Delay} = \tau_{inv}\sum g_ih_i$	path delay: sum of the gains
$F = \prod g_ih_i = G H$GH, $G = \prod g_i$∏gi​, $H = C_L/C_{in}$	path effort; constant if $C_{in}$Cin​, $C_L$ fixed and nothing branches
$f = F^{1/N}$F1/N, $\text{Delay}_{min} = N F^{1/N}\tau_{inv}$	equal gains minimize the delay
$\text{Delay} = \ln(C_{out}/C_{in})\,\dfrac{\alpha}{\ln\alpha}\,\tau_{inv}$ln(Cout​/Cin​)lnαα​τinv​, best $\alpha = e$	stage count; 3–4 per stage in practice (drain cap); $N \approx \ln F$lnF; add inverters in pairs
size back from the load: $W_n = C_{out}/(3f)$Cout​/(3f), then double stacked devices	equal-gain sizing; the first gate stays fixed
added inverters next to the load	same delay, less total width and dynamic power
$b = (C_{on} + C_{off})/C_{on}$Coff​)/Con​, $F = GHB$	branching effort; depends on the sizes, so $F$ is not fixed
enlarge the gate after a heavy branch, then rebalance	retuning around fan-out; equal gains are no longer optimal
bottom of a stack: Delay ∼ $n^2$	internal nodes at $V_{DD} - V_T$ must discharge first; late signal on top

The lecture’s boards

Lecture08 @ 04:14 recap: g, h, gain; the normalized inverter

Lecture08 @ 09:59 Delay = Σ g_i h_i τ_inv; path effort F

Lecture08 @ 13:36 equal gains: √F, n-th root

Lecture08 @ 18:26 stage count: α = e, about 3 to 4

Lecture08 @ 29:52 example: 6.86 ns; F = 308; 973 ps

Lecture08 @ 35:35 resizing: 24.7/98.8, 12.2 µm

Lecture08 @ 40:25 five stages: 3.15, 756 ps

Lecture08 @ 42:25 sizing the inverters (16.8 is a slip for 52.9)

Lecture08 @ 47:38 branching effort

Lecture08 @ 50:33 branch example: the circuit

Lecture08 @ 55:06 retuning: 11.7 → 10.74 → 10.63 τ_inv

Lecture08 @ 58:54 stacks: V_DD − V_T, Delay ∼ n²