11. Dynamic and domino logic

Static CMOS gives the right answer whatever its sizes, but it pays for that with a PFET for every NFET: extra input capacitance on every gate. Ratioed logic (Chapter 10) drops the PFETs and pays with static current. Lecture 11 finishes those two families, then builds a third: dynamic logic, in which the output node is charged up on one phase of a clock and conditionally discharged on the other. It is fast, because the evaluation is done by NFETs alone and fights nothing. But its output node is connected to nothing for part of the time, and the second half of the lecture is a tour of everything that can disturb a node like that, and of the circuits that protect it.

After this chapter you can:

1. state the two problems of ratioed logic and why IDDQ testing needs its pull-ups switched off;
2. size a complementary pass transistor together with its driving inverter, using the lecture’s R, 2R, 4R model;
3. explain precharge and evaluate, the dynamic node, the collision and the footer that prevents it, and read the function of a dynamic gate;
4. explain the race between two cascaded dynamic gates, and how the inverter of domino logic removes it; say why domino logic is non-inverting and why it is fast;
5. compute the evaluate delay of a footed dynamic stack with the delay model of Chapter 7;
6. explain leakage, charge-sharing, coupling and power-supply noise on a dynamic node, and size a half latch by the one-tenth rule;
7. estimate a charge-sharing droop and name the babysit devices that prevent it.

Boxes and equations marked board were written in the lecture. Parts marked added are explanations or examples this guide adds.

Before you start

You need these ideas from earlier chapters. Each is restated here.

• Static, ratioed, dynamic (Chapter 7). A static CMOS gate has a pull-up network of PFETs and a pull-down network of NFETs, and for any settled inputs exactly one of them is on. Both on is ratioed logic; neither on is dynamic logic.
• The delay model (Chapter 7). A transistor of width $W$ is a “resistance” $R/W$R/W, with $R_{nfet}$ and $R_{pfet} \approx 2R_{nfet}$ in kΩ·µm; a gate input is $C_g$ per µm of width; delay $= (R/W)\,C_{load}$(R/W)Cload​. Devices in series add: a stack of $n$ needs each device $n$ times wider for the strength of one. $\tau_{inv} = 3R_{nfet}C_g$ (or $2R_{nfet}C_g$ when a problem says the NFET and PFET have equal strength).
• Pass transistors and the half latch (Chapter 10). An NFET passes a good 0 but a high only up to $V_{DD} - V_T$VT​; a PFET passes a good 1 but a low only down to $|V_T|$∣VT​∣. A complementary pass transistor puts one of each in parallel, driven by complementary signals. A half latch is a weak PFET wrapped around an inverter that pulls a degraded high up to $V_{DD}$VDD​. Transistors connected through their sources and drains form one channel-connected component (CCC).
• Pseudo-NMOS (Chapter 10). A PFET with its gate grounded as an always-on load over an NFET pull-down network.
• Noise margins and the switching threshold (Chapter 6). An inverter with a stronger PFET switches at a higher input voltage.
• Subthreshold leakage (Chapter 4). An NFET with its gate at 0 still conducts a small current.

Notation. Sizes such as “4/2” mean a PFET 4 µm wide and an NFET 2 µm wide, as in Chapter 7. “clk” is the clock; $\overline{\text{clk}}$ its complement. The board first calls the dynamic node Y (17:08); once the lecture adds an inverter after it, this chapter calls the dynamic node X and the inverter’s output Y.

1. Ratioed logic, its two problems and IDDQ testing

The idea. Pseudo-NMOS makes wide NORs cheap, but its low output is never quite at ground and it burns power whenever its output is low.

Lecture11 @ 02:17Pseudo-NMOS and its two problems: ① logic low not full rail; ② static power whenever the output is low.

The lecture opens where Lecture 10 stopped (00:05). The commonest ratioed gate is pseudo-NMOS, inspired by the old NMOS logic with its depletion-mode load: in CMOS, the load becomes a PFET with its gate tied to ground (00:15). Its strength is the wide NOR: any number of parallel NFETs, with no stack of PFETs to carry along (00:44).

Two problems (00:57–01:39) board:

1. The logic low is not full rail. With the output low, the PFET load is still on, fighting the pull-down. added The output settles where the two currents balance, a little above ground. The NFET/PFET strength ratio must make it low enough that the next gate doesn’t misread it.
2. Static power. Whenever the output is low, current flows from $V_{DD}$ to ground through both devices, all the time.

It is still worth it for very wide ORs; programmable logic arrays (PLAs), a NOR followed by a NOR, use it (01:39).

IDDQ testing (02:11) board. When a chip comes back from fabrication, one test measures the quiescent supply current, $I_{DDQ}$ (the Q). A power-to-ground short anywhere on the chip shows up as a large quiescent current. Ratioed logic draws static current by design and would hide such a short, so its load’s gate is not tied to ground but to a control line: 0 in normal operation (load on), 1 in test mode (load off) (02:33–03:11). The board writes it as “ctl = 1, 0” on the PFET’s gate (10:53). Testing comes back later in the course.

Check yourself A pseudo-NMOS NOR has eight inputs. In normal operation, for which input combinations does it draw static current? Why would that spoil an I_DDQ test, and what does the control line do?

It draws current whenever its output is low, that is, whenever at least one input is 1 (255 of the 256 combinations): the PFET load and the conducting NFETs form a path from $V_{DD}$ to ground. An $I_{DDQ}$ test looks for unexpected quiescent current, so these legitimate currents would mask a short. Setting the control line to 1 in test mode turns the load PFET off, and the gate draws nothing.

2. Sizing pass transistors

The idea. A pass transistor is sized together with the gate that drives it. Because both devices of a complementary pass transistor help on both edges, its PFET needs to be only as wide as its NFET.

Lecture11 @ 10:53Sizing a pass transistor with its driver: the CCC (top), redrawn as two-high stacks (bottom), and the resistor model: R∥4R = 0.8R down, 2R∥2R = R up.

Size it with its driver

“Just as delay makes no sense if we don’t consider the driving gate, sizing of pass transistors makes no sense unless we consider the driving gate” (03:43). The simplest case: an inverter (input A) drives a complementary pass transistor (gates B and $\overline B$B), which drives a load $C_L$ board. Together they are one channel-connected component (CCC, or region, CCR): current flows from the supply through both.

Redraw it (04:14–04:51) board: from $V_{DD}$VDD​, the inverter’s PFET (A) in series with the pass PFET ($\overline B$B) reaches the output Y; from Y, the pass NFET (B) in series with the inverter’s NFET (A) reaches ground. It is a two-high PFET stack and a two-high NFET stack. (The board labels the bottom NFET “B”; it is the inverter’s NFET, driven by A.)

For the drive of a 2/1 inverter, Chapter 7’s stack rule gives the first attempt (05:00): NFETs 2 µm each, PFETs 4 µm each board.

Both devices help on both edges

The catch (05:18–06:45): when the output is pulled down, current flows through the pass NFET and through the pass PFET; when it is pulled up, through the pass PFET and the NFET. Only the PFET can pull all the way to $V_{DD}$VDD​, and only the NFET all the way to ground; the other one keeps losing overdrive as the output moves and finally cuts off (at $V_{DD} - V_T$ for the NFET, at $V_T$ for the PFET). That is why the complementary pass transistor was used in the first place. But during most of each transition, both help.

The resistor model

For equal widths $W$W, “without proving it” (07:13–08:42) board:

device and edge	resistance
NFET pulling down (its good direction)	$R$
PFET pulling up (its good direction)	$2R$
NFET pulling up (losing overdrive)	about $2R$
PFET pulling down (losing overdrive)	about $4R$

The weak direction is about twice the good one, because the device keeps losing overdrive while it works (08:42).

Pull-down and pull-up of the pass transistor (board, 08:42–09:26)

1. Pulling down, the NFET and the PFET are in parallel board: $R \parallel 4R = \dfrac{R \cdot 4R}{R + 4R} = 0.8R$0.8R. (The lecturer first says “like 0.9R”, then corrects himself.)
2. Pulling up board: $2R \parallel 2R = R$R.
3. These are roughly equal, and both are about the NFET’s own $R$ (09:26).
4. So the pass transistor at equal widths acts like its NFET alone, in both directions. Its PFET doesn’t need the usual factor of two: size the pass PFET equal to the pass NFET, 2 µm rather than 4 µm (09:37) board.

The rule of thumb (09:52): size the stack as you normally would, then make the pass PFET equal to the pass NFET, always with the driving gate in view. Compare the 09:27 frame in the gallery, where the pass PFET is still 4 µm, with 10:53, where it has become 2 µm.

Worked example. added The lecture’s circuit: inverter 4/2, pass transistor 2/2. Resistances in units of $R_{nfet}$ (kΩ·µm) divided by µm.

1. Target: each element of a two-high stack should be half the 2/1 inverter’s resistance, $R_{nfet}/2\,\mu\mathrm{m} = 0.5R_{nfet}$0.5Rnfet​.
2. Inverter NFET: $R_{nfet}/2 = 0.5R_{nfet}$0.5Rnfet​. Inverter PFET: $2R_{nfet}/4 = 0.5R_{nfet}$0.5Rnfet​. On target.
3. Pass transistor down: NFET $R_{nfet}/2 = 0.5$0.5, PFET $4R_{nfet}/2 = 2$2; in parallel $0.4R_{nfet}$0.4Rnfet​.
4. Pass transistor up: NFET $2R_{nfet}/2 = 1$1, PFET $2R_{nfet}/2 = 1$1; in parallel $0.5R_{nfet}$0.5Rnfet​. On target.
5. Whole path: down $0.5 + 0.4 = 0.9R_{nfet}$0.9Rnfet​, up $0.5 + 0.5 = 1.0R_{nfet}$1.0Rnfet​, against the 2/1 inverter’s $1.0R_{nfet}$ both ways.
6. With a 4 µm pass PFET instead: down $0.5 \parallel 1 = 0.33$0.33, up $1 \parallel 0.5 = 0.33$0.33, so $0.83R_{nfet}$ both ways: faster than needed, and 2 µm more gate on the $\overline B$ line.

Common mistakes.

• Copying the inverter’s 2:1 ratio into the pass transistor. The PFET’s job on the rising edge is shared with the NFET.
• Sizing the pass transistor alone. Its resistance is in series with the driver’s; the two are one stack.
• Forgetting that the weak device stops helping near the rail. The 0.8R and R are averages over a transition, a rough model the lecturer offers “without proving it”.

Check yourself With R_nfet = 2 kΩ·µm and R_pfet = 2R_nfet, the lecture's 4/2 inverter drives 30 fF through a 2/2 µm complementary pass transistor. Estimate the falling and the rising delay at the output.

Falling: the path is $0.9R_{nfet}/\mu\mathrm{m} = 1.8\,\mathrm{k\Omega}$1.8kΩ, so $1.8 \times 30 = 54\,\mathrm{ps}$54ps. Rising: $1.0R_{nfet} = 2.0\,\mathrm{k\Omega}$2.0kΩ, so $60\,\mathrm{ps}$60ps. A 2/1 inverter driving 30 fF directly would take $2.0 \times 30 = 60\,\mathrm{ps}$ both ways.

Check yourself An NFET-only pass transistor of width W is driven by an inverter. Using the lecture's table, how strong is it pulling up compared with pulling down? What does Chapter 10 add to that?

Pulling down it is $R/W$R/W; pulling up about $2R/W$2R/W, twice as slow, because it loses overdrive as the output rises. And it never finishes: it cuts off at $V_{DD} - V_T$ (Chapter 10), which is why the complementary pass transistor or a half latch is used.

3. Why dynamic logic

The idea. Static CMOS is robust but carries a PFET network; pseudo-NMOS drops the PFETs but fights its load all the time. Dynamic logic keeps the first advantage of each.

Lecture11 @ 14:24The two starting points: a complementary static NOR (its PFET stack circled) and pseudo-NMOS (its load circled).

Static CMOS: exactly one connection from the output to $V_{DD}$ or ground (10:36) board. Connected to both: ratioed logic. Connected to neither: a high-impedance node, and that is dynamic logic (11:03). The lecturer believes it was invented at Bell Labs, by people inspired by NMOS design (11:41), and follows their reasoning.

The complementary static NOR (12:15–13:40):

• it always gets the right answer, however it is sized (“very, very hard to break”); it draws no static power;
• but while it switches, both networks are briefly on: crowbar current that doesn’t charge the load, burning power and slowing the gate (Chapter 6);
• and it carries the PFET switches, extra capacitance for the preceding gate to drive. That is exactly what raises the logical effort of complex gates (Chapter 7).

Pseudo-NMOS (13:40–14:39) removes the PFET capacitance, but turns the brief crowbar current into a permanent fight with its load. “Is there a way to get the best of both worlds?” (14:39): no PFET network, and no fight.

4. Precharge and evaluate

The idea. Put the pull-up PFET’s gate on a clock. On one phase it charges the output high (precharge); on the other it is off, and the NFET network either discharges the output or leaves it floating at its precharged 1 (evaluate).

Lecture11 @ 17:08The dynamic gate: the PFET's gate on the clock; in evaluate with all inputs 0, Y floats: a dynamic node.

The two phases

Keep pseudo-NMOS’s NFET pull-down network (again, a wide NOR is natural here), and tie the PFET’s gate to a clock that toggles between 0 and 1 (15:07–15:49) board:

• clk = 0: precharge. The PFET is on and pulls the output Y all the way to $V_{DD}$ (15:59).
• clk = 1: evaluate. The PFET is off (16:12). If every input is 0, nothing connects Y to $V_{DD}$ or to ground: Y is floating, in a high-impedance state, a dynamic node board (16:35). It stays at 1 only because its capacitance was charged to $V_{DD}$VDD​: the logic value is stored as charge (16:53).
• If any input is 1 during evaluate, Y is pulled down to 0 (17:51). With inputs A, B, C, D the gate computes $\overline{A + B + C + D}$A+B+C+D​: a NOR (17:27).

The next precharge pulls Y back to 1, and the cycle repeats.

The collision and the footer

Lecture11 @ 20:18The clocked NFET at the foot of the network: the evaluate transistor, foot device or footer; the PFET is the precharge device.

What if an input is still 1 when the clock goes back to 0 (18:18)? The PFET precharges while the NFET pulls down: a collision, with short-circuit current through both. The usual fix is one more NFET at the foot of the network, also driven by the clock (18:43) board. It is called the evaluate transistor, the foot device or the footer; the clocked PFET is the precharge device (18:57–19:06).

During precharge the footer is off, so the pull-down can never conduct, whatever its inputs (19:12). The price is delay: the footer adds one device to the stack (19:40). It can be left out in circuits that guarantee every input is back at 0 before the next precharge begins (19:40–20:06); the lecture returns to that later (Chapter 12).

Clock:clk = 0 (precharge)clk = 1 (evaluate)

Inputs:A = 0B = 0C = 0D = 0

Footer in (clocked NFET at the foot)Start over

precharge PFET

on

footer

off

path to ground

no

dynamic node X

1

domino output Y = NOT X

0

NOR of the inputs now

1

X is precharged: driven to V_DD.

clk	ABCD	X	Y	X is
0	0000	1	0	precharged

Green boxes conduct; a circle marks a PFET. The table logs your last 8 steps. This is a switch-level picture: a node is 1, 0, or "?" in a collision, and the inverter is ideal. Leakage, charge sharing and noise, which make a floating 1 sag (Sections 8–12), are left out. Try: evaluate with all inputs 0 (X floats at 1); raise A (X discharges); lower A again (X stays 0); go back to precharge with A = 1, with and without the footer.

What to notice.

• In evaluate with all inputs 0, X is 1 with every device around it off: the “floating” rows of the log.
• Raise an input in evaluate and X falls; lower it again and X stays 0. A dynamic gate can only discharge during evaluate: an input that rises by mistake, even briefly, does damage that the next precharge alone repairs.
• Remove the footer and return to precharge with an input at 1: collision.

Reading the function of a dynamic gate

added In evaluate, the dynamic node is 0 exactly when the pull-down network conducts. So the node computes the complement of the network’s switching function $f$f, like a static gate: series NFETs are AND, parallel ones OR, and $X = \overline{f}$f​. An inverter after it gives $f$ itself (Section 6).

The evaluate delay

added Precharge happens for every gate at once and is not on the critical path (Section 7); what matters is the evaluate delay, the time to discharge the node through the network and the footer, in series. Chapter 7’s model applies directly.

A footed stack (added)

1. A dynamic gate’s pull-down is A and B in series with the footer, each NFET 4 µm; the load is 50 fF; $C_g = 2\,\mathrm{fF/\mu m}$2fF/μm.
2. Three 4 µm devices in series act as one NFET of $1/(3/4) = 4/3\,\mu\mathrm{m}$ (Chapter 7’s stack rule).
3. 50 fF is $25\,\mu\mathrm{m}$ of gate. Delay $= \dfrac{R_{nfet}}{4/3\,\mu\mathrm{m}} \times 25\,\mu\mathrm{m}\,C_g = 18.75\,R_{nfet}C_g$18.75Rnfet​Cg​.
4. With $\tau_{inv} = 3R_{nfet}C_g$3Rnfet​Cg​: $6.25\,\tau_{inv}$6.25τinv​. If the problem says the NFET and PFET have equal strength, $\tau_{inv} = 2R_{nfet}C_g$ and the delay is $9.375\,\tau_{inv}$9.375τinv​.
5. The 1 µm precharge PFET doesn’t appear: it is off during evaluate. Without the footer, the stack would be $2\,\mu\mathrm{m}$ wide and the delay $12.5\,R_{nfet}C_g$12.5Rnfet​Cg​: the footer costs 50% here.

Common mistakes.

• Leaving the footer out of the evaluate stack. It is in series with the network and must be counted.
• Counting the precharge device in the evaluate delay. It is off.
• Calling a footed gate’s output “static” because it is driven during precharge. During evaluate with the network off, nothing drives it.

Check yourself A dynamic gate's pull-down network is A in series with (B in parallel with C), above a footer. What does the dynamic node compute in evaluate? What does an inverter after it give?

The network conducts when $A(B + C)$ is true, so the node is $\overline{A(B + C)}$ and the inverter’s output is $A(B + C)$C). (Reading the function of a dynamic stage is MT24-5a’s first step; its stages are this kind of gate, one of them in Lecture 12’s p-type form.)

Check yourself In MT17-3c, a dynamic gate has a 1 µm clocked PFET and three 4 µm NFETs in series (A, B and the clocked footer), driving 50 fF with C_g = 2 fF/µm. The NFET and PFET have equal strength. Find the A-rising-to-Y-falling delay in evaluate, with B = 1, in units of τ_inv.

The stack acts as one $4/3\,\mu\mathrm{m}$ NFET; 50 fF is 25 µm of gate. With equal strengths the FO1 inverter is W/W, so $\tau_{inv} = 2R_{nfet}C_g$2Rnfet​Cg​. Delay $= (R_{nfet}/(4/3)) \times 25C_g = 18.75R_{nfet}C_g = 9.375\,\tau_{inv}$9.375τinv​. (This is MT17-3c; its key’s 9.375 τ_inv is right.)

Check yourself Why can't a footless dynamic gate accept an input that is still 1 when the clock falls?

With clk = 0 the precharge PFET is on; an input at 1 turns the pull-down on as well, and with no footer the two fight: a collision, with current from V_DD to ground and an output somewhere in between (18:18). A footless gate is safe only if its inputs are guaranteed to be 0 before precharge starts.

5. Cascading dynamic gates: the race

The idea. A dynamic gate’s output is 1 during precharge. Fed straight into the next dynamic gate, that 1 starts discharging the next gate before the first has decided; which of two delays wins then decides the answer.

Lecture11 @ 30:38Race condition (top right), and the cure: an inverter after each dynamic gate, which makes domino logic (yellow); the logic becomes non-inverting.

Cascading is unavoidable: one NOR must drive another (20:21) board. Take two dynamic NORs on the same clock, the first’s output Y driving one input of the second, every other input of the second at 0 (20:47–21:32):

1. Precharge. Both outputs go to 1 (21:32).
2. Evaluate. Input A of the first gate is 1, so the first output should fall to 0, and the second gate, whose inputs are then all 0, should stay at 1 (21:12).
3. But the first gate takes a finite time to discharge. Until it does, its output is still 1, and that 1 is turning on the second gate’s NFET, which starts discharging the second output (22:09–22:36).
4. If the first gate falls fast, the second output loses little and stays a 1. If the second output falls fast, it reaches 0 before the first gate has turned its NFET off, and stays 0, the wrong answer: once discharged, a dynamic node can’t recover (23:02).

The answer depends on which of two delays is faster: a race condition board (23:29). Race conditions are “very, very bad”: the delays can’t be controlled precisely, and they change with process, voltage and temperature (23:40). A few designs use a race on purpose, carefully controlled and margined across all corners; this one is uncontrolled (24:08–24:38).

Between the stages:a wire (dynamic into dynamic)an inverter (domino)

Stage 1 input A:A = 1 (stage 1 discharges)A = 0 (stage 1 holds)

stage 1 delay ÷ stage 2 delay (τ₁/τ₂)

0.50

stage 1's node crosses V_DD/2 at

0.35 τ2

stage 2's node should end at

1

it ends at

0.707 V_DD

read by its inverter as

1

Correct, but only because stage 1 won the race: stage 2 still lost 29% of its charge while stage 1's node was on its way down.

Toy model, added to make "which delay wins" visible: the lecture argues it in words (21:32–23:29). Each dynamic node discharges as an RC exponential with its own time constant (τ₁, τ₂), the NFET it drives is a switch that conducts above V_DD/2, and the inverter is ideal and instant. Without the inverter, stage 2's input is stage 1's node, so their two lines coincide. Then stage 2 keeps 2^−τ1/τ2 of its charge when A = 1, so it reads as 1 only if stage 1 is the faster of the two. Real waveforms differ; the race does not.

What to notice.

• With a wire between the stages and A = 1, slide τ₁/τ₂ past 1: stage 2 ends below V_DD/2 and is read as 0.
• Even when stage 1 wins (τ₁/τ₂ = 0.5), stage 2 has lost about 30% of its charge: it is left with less margin against the noise of Sections 8–12.
• With the inverter, every ratio gives the right answer.

Check yourself In the toy model of the widget, stage 2 keeps 2^−τ1/τ2 of its charge. With τ₁ = 0.5τ₂ and τ₁ = 2τ₂, what does it end at, and how does its inverter read it? Why is a design that works at τ₁ = 0.5τ₂ still a bad design?

$2^{-0.5} = 0.71\,V_{DD}$0.71VDD​, read as 1; $2^{-2} = 0.25\,V_{DD}$0.25VDD​, read as 0. The first case works only because of a delay ratio that varies with process, voltage and temperature (23:40); a slow corner for stage 1 or a fast one for stage 2 flips it. And even when it works, the node has lost charge that noise can finish off.

6. Domino logic

The idea. Put an inverter after every dynamic gate. During precharge every inverter output is 0, so no gate can start discharging the next one before it has evaluated.

The race exists because a precharged output is a 1 (24:38). If it were a 0 during precharge, the next gate would be off until the previous one had decided. So insert an inverter between the stages (25:06) board. The dynamic gate and its inverter together are domino logic (25:36) board.

Why “domino” (25:51). Precharge stands every domino up. Evaluate pushes the first one; each one either stays standing (a 1 on its dynamic node) or falls, and a falling one can knock over the next. At the end of the cycle, precharge stands them all up again.

Non-inverting (26:18) board. With the inverter, each stage computes the network’s function itself: the NOR becomes $A + B + C + D$ board, an OR. Non-inverting logic is not logically complete: no network of ANDs and ORs makes an inversion. The remedies (27:12–27:56): push the inversions back into the latches that feed the logic and carry both the true and the complement of each signal through the logic as needed, or push them forward to some static logic at the end. Both come up again with latches and clocking, after the midterm material.

Worked example. added With true and complement signals available, a domino gate can make an XOR: a pull-down of A in series with $\overline B$B, in parallel with $\overline A$ in series with B. The network conducts when $A\overline B + \overline A B$AB, so the dynamic node is $\overline{A \oplus B}$ and the domino output is $A \oplus B$B.

Check yourself Why can't a chain of domino gates fed only by true signals compute the NAND of two inputs?

Every domino stage computes the AND–OR function of its network on its inputs, which is non-inverting: if an input rises, the output can only rise or stay. NAND falls when its inputs rise. It needs $\overline A$ or $\overline B$ from somewhere else (a latch that supplies complements, 27:12): with them, $\overline A + \overline B$ is an OR.

Check yourself A domino gate's network is (A in series with B) in parallel with (Ā in series with B̄). What do the dynamic node and the output compute? MT23-3a asks the same of a gate built the other way up (Chapter 12's p-type form: PFETs evaluate and pull a node that rests at 0 up to 1). Its PFETs conduct when (A = 0 or B̄ = 0) and (Ā = 0 or B = 0). What is its output after the inverter?

Here the network conducts for $AB + \overline A\,\overline B$ (A and B equal), so the node is $\overline{AB + \overline A\,\overline B} = A \oplus B$ and the output is the XNOR. In the exam’s gate, the PFET network conducts when $(\overline A + B)(A + \overline B) = AB + \overline A\,\overline B$AB; there the node rises when the network conducts, so the node is the XNOR and the inverter gives $A \oplus B$B, an XOR. Always ask which way the node moves when the network conducts.

7. Why domino is fast: a skewed logic family

The idea. All the logic is done by NFETs on one edge, against nothing; the other edge, the precharge, happens everywhere at once. So each device can be sized for the edge that matters.

Why go to all this trouble (27:56)?

• Only NFETs evaluate. The logic no longer carries PFETs, the original motivation, as with pseudo-NMOS (28:13).
• Nothing to fight. When the pull-down discharges the dynamic node, no PFET is trying to hold it up: the node is high-impedance, and “all I have to do is discharge the capacitor” (28:39). The evaluation is very fast. The next lecture puts numbers on it with logical effort and gain-based tuning (29:06; Chapter 12).
• One edge. All the logically important transitions happen on one edge: the dynamic node falling, the inverter’s output rising (29:06). The other edge is the precharge, which “doesn’t have any logically important evaluations on it” and happens in parallel for every gate.

So domino is a skewed logic family (29:33): each network is sized for the edge that carries the logic, and the other side is made small. In particular, the inverter after the dynamic node is not sized 2:1. Its PFET, which drives the rising output, is made much stronger than its NFET, which only resets the output during precharge, and “I have plenty of time to do precharge” (29:47–30:12).

added The skew has a price (Chapter 6). An inverter with a strong PFET switches at a higher input voltage, so the dynamic node, which sits at $V_{DD}$VDD​, needs to sag less before the inverter flips: its high noise margin shrinks. That matters for everything in the rest of this chapter.

Check yourself Why is the domino inverter skewed toward a strong PFET and not a strong NFET? What does that do to its noise margins, and which margin matters for the dynamic node?

Its output carries the logic when it rises (the dynamic node falling, 29:06); its falling edge is the precharge reset, which has time to spare. So the PFET is made strong. That raises the inverter’s switching threshold: $NM_L$ grows and $NM_H$ shrinks. The dynamic node rests at 1 and noise pulls it down, so the shrinking $NM_H$ is the one that hurts. (MT23-3c asks the mirror question for a p-type gate, whose inverter has the strong NFET: there the small margin is $NM_L$NML​.)

8. Leakage noise and the half latch

The idea. A node held only by its charge loses that charge through every off transistor attached to it. A weak PFET, driven back from the inverter, replaces it.

Lecture11 @ 35:24Leakage noise: in evaluate with every input 0, the dynamic node droops through subthreshold leakage; the half latch (circled, ON) holds it up.

The dynamic node is fast precisely because nothing holds it, and for the same reason it is “very noise sensitive” (30:40). The lecture takes four noise sources in turn; dynamic gates are good for this, being “especially sensitive to all of them” (52:18).

Leakage noise

Take a very wide OR, natural in dynamic logic because width costs no PFET stack (31:58), in evaluate with all its inputs 0 (32:32) board. Each NFET is off, but each still conducts a little subthreshold leakage (32:43; Chapter 4). Together they slowly discharge the dynamic node: by the end of the evaluate phase it has drooped from $V_{DD}$ by some amount, and if that is too much, the inverter flips and the gate falsely evaluates (33:22) board. Noise on the inputs makes it worse: a coupled blip that turns some of the NFETs on a little drains the node faster (33:39).

added The droop grows with the number of parallel devices and with the length of the evaluate phase, so a wide gate on a slow clock is the worst case.

The half latch

The fix (34:08) is the half latch already met with pass transistors (Chapter 10): a PFET from $V_{DD}$ to the dynamic node, its gate driven by the domino inverter’s output board. While the node is 1, the inverter’s output is 0, the PFET is on, and it holds the node at 1 against leakage and noise (34:32–34:48). Strictly, the node is no longer dynamic (34:32).

It isn’t free (35:15): when the network should discharge the node, it must now fight the half latch until the inverter switches and turns it off. So the half latch’s size is a direct trade-off (35:15–36:00):

• weaker: faster evaluation, worse noise margins; none at all is the fastest and the noisiest;
• stronger: better noise margins, slower evaluation.

added The fight is also why a node with a half latch is not plain static CMOS either: correct operation now depends on the pull-down being stronger than the half latch, a ratio (the point of MT24-3a’s grading note about half latches in a pass-transistor circuit).

Common mistakes.

• Driving the half latch’s gate from the dynamic node. It is driven from the inverter’s output, so that it turns off once the node falls.
• Making it as strong as the pull-down. Then a real evaluation may never win the fight.

Check yourself MT23-3d asks how one transistor can improve the noise margin of a domino gate's dynamic node. What is it for the lecture's n-type gate, and how is it connected? What is the mirror device for a p-type gate whose dynamic node rests at 0?

A half latch: a weak PFET from V_DD to the dynamic node, its gate on the inverter’s output, so that it is on while the node is 1 (34:08). For a p-type gate whose node is pre-discharged to 0 and pulled up by noise, the mirror is a weak NFET from the node to ground, gated by the inverter’s output, on while the node is 0.

9. Sizing the half latch

The idea. Make the half latch about one tenth as strong as the pull-down network. When minimum width is still too strong, add a series device and lengthen that one, not the one the output drives.

Lecture11 @ 38:30The half latch at 1/10 the strength of the pull-down network; weaken it by W↓ and L↑, or with a series device, keeping the output-loading device at L_min, W_min.

The rule of thumb (36:37) board: size the half latch to one tenth the strength of the pull-down network. It must be a weak device. How do you make one (37:11)?

1. Reduce its width board. Until you reach the minimum width.
2. Increase its length board: a longer channel conducts less (Chapter 4: current goes as $W/L$W/L). But its gate area grows with $L$L, and that gate is driven by the inverter’s output: a direct extra load on the logic path, slowing the evaluation (37:11–37:42).
3. Use a series device (37:42–38:38) board. Keep the device whose gate is driven by the output at minimum length and minimum width, and put a second PFET in series with it. The series connection already halves the strength, and the second device’s length can be increased as much as needed, because its gate doesn’t load the output. Strength ratios of about a tenth become reachable.

Worked example. added (From the Fall 2026 recitation.) A pull-down network of three NFETs in series, each 3 µm.

1. The stack acts as one NFET of $1/(3 \times 1/3) = 1\,\mu\mathrm{m}$1μm.
2. One tenth of its strength: an NFET of $0.1\,\mu\mathrm{m}$0.1μm.
3. A PFET has half an NFET’s strength at the same width, so the half latch is a PFET of $0.2\,\mu\mathrm{m}$0.2μm.
4. That is narrower than any real minimum width: hence the series device, or a longer channel, of step 3 above.

Check yourself A domino gate's pull-down is one 2 µm NFET above a 2 µm footer. By the one-tenth rule, how wide should the half-latch PFET be (R_pfet = 2R_nfet)? If the minimum width is 0.5 µm, what does a second minimum-width PFET in series give?

The stack acts as a 1 µm NFET; one tenth is a 0.1 µm NFET, so a 0.2 µm PFET. A single 0.5 µm PFET would be 2.5 times too strong. Two 0.5 µm PFETs in series act as one 0.25 µm PFET, still 1.25 times too strong, so the series device is also lengthened (it doesn’t load the output). The one-tenth rule is a starting point, not a hard limit (36:37).

10. Charge-sharing noise and babysit devices

The idea. Internal nodes of the pull-down network that were left at 0 can steal charge from the dynamic node when a device above them turns on, even though no path to ground exists.

Lecture11 @ 47:02Charge sharing in a wide AND-OR gate: upper inputs switch to 1, lower ones stay 0; the fixes are babysit devices on the internal nodes (clocked PFETs, a clk̄ NFET, or always-on weak devices) and the half latch.

The mechanism

Take a wide AND-OR gate: several branches in parallel, each two NFETs in series (39:57–40:29) board. Suppose that in the previous cycle the lower NFETs were all on, so the internal nodes between the two devices of each branch were discharged to ground (40:59–41:23). Now, in evaluate, the upper inputs switch to 1 and the lower ones stay at 0 (40:41) board. No branch conducts to ground, so the dynamic node should stay at 1.

But each upper NFET now connects the dynamic node’s capacitance to an empty internal node. The charge on the dynamic node “gets shared across these capacitors” until they all reach the same potential (41:26), and the dynamic node’s voltage drops (42:00). If it drops far enough, the gate falsely evaluates. This is charge-sharing (or charge-redistribution) noise board.

How far it drops (added)

1. Before: the dynamic node, capacitance $C_X$CX​, holds $Q = C_XV_{DD}$CX​VDD​; the internal nodes, total capacitance $C_{int}$Cint​, hold nothing.
2. After: all are at one voltage $V$V, and no charge has left (there is no path to ground or to $V_{DD}$VDD​): $C_XV_{DD} = (C_X + C_{int})V$Cint​)V.
3. So $V = V_{DD}\,\dfrac{C_X}{C_X + C_{int}}$VDD​CX​+Cint​CX​​.
4. The internal nodes are charged through NFETs whose gates are at $V_{DD}$VDD​, which can raise them only to $V_{DD} - V_T$VT​. If step 3 gives more than that, the internal nodes stop at $V_{DD} - V_T$ and the dynamic node keeps the rest.

Worked example. added $V_{DD} = 1.2\,\mathrm{V}$1.2V, $C_X = 40\,\mathrm{fF}$40fF, three branches turning on with 8 fF internal nodes: $C_{int} = 24\,\mathrm{fF}$ and $V = 1.2 \times 40/64 = 0.75\,\mathrm{V}$0.75V. A skewed inverter switching at $0.6V_{DD} = 0.72\,\mathrm{V}$ still reads a 1, with 30 mV to spare. A fourth branch: $1.2 \times 40/72 = 0.67\,\mathrm{V}$0.67V, a false evaluation.

The fixes

• The half latch fights it too, with the same trade-off between delay and noise margin (42:26) board.
• Precharge the internal nodes (42:43–43:56) board. The problem is that they can start at 0; if they were at $V_{DD}$VDD​, there would be nothing to share. A small PFET with its gate on the clock, from $V_{DD}$ to each internal node, charges them all during precharge. Not free: more power in precharge, and a real evaluation must now discharge those capacitances too, so it is slower (43:56–44:22). “None of this is free.”
• Use NFETs for that (44:22–45:24) board. PFETs embedded in a sea of NFETs are a layout pain: each needs an N well. An NFET with its gate on $\overline{\text{clk}}$clk, from $V_{DD}$VDD​, is easy to lay out, and $\overline{\text{clk}}$ is “probably lying around”. It charges the internal nodes only to $V_{DD} - V_T$VT​. Keep these devices weak; there is no need for strong ones.
• Always-on weak devices (45:24–46:44) board. Clocked devices add load to the clock. Instead, a PFET with its gate grounded (but it is a PFET again) or an NFET with its gate at $V_{DD}$ can hold the internal nodes up all the time. These must be weak, because a real evaluation has to fight them.

All of these, clocked or static, are called babysit devices board: they babysit the internal nodes, keeping them in a known state (46:44).

Internal nodes left at 0Babysit NFETs: V_DD − V_TBabysit PFETs: V_DD

branches whose upper NFET turns on

3

dynamic node capacitance C_X

40 fF

capacitance of each internal node C_i

8.0 fF

V_DD

1.20 V

NFET threshold V_T

0.30 V

inverter switching threshold (÷ V_DD)

0.60

internal nodes start at

0.00 V

C_int = n·C_i

24.0 fF

dynamic node after sharing

0.750 V (37.5% drop)

internal nodes end at

0.750 V

inverter switches at

0.720 V

The inverter still reads a 1, with 0.030 V to spare.

Charge conservation, added: the lecture describes the sharing in words (41:26). Capacitances are fixed and the half latch is left out (it would supply charge and pull the node back up, at the cost of a fight on a real evaluation). In this ideal model both kinds of babysit device leave nothing to share, because a connecting NFET with its gate at V_DD cannot raise an internal node above V_DD − V_T anyway; the two babysat lines lie on top of each other at V_DD. The skewed domino inverter (strong PFET) switches above V_DD/2, which makes the drop more dangerous.

What to notice.

• Each extra branch that turns on lowers the node further; the dynamic node’s own capacitance is the defence.
• Raise the inverter’s switching threshold (a more skewed inverter): the same droop becomes a false evaluation.
• Both babysit choices give the full $V_{DD}$ here, including the NFET one that only reaches $V_{DD} - V_T$VT​: an internal node at $V_{DD} - V_T$ can’t take charge through an NFET whose gate is at $V_{DD}$VDD​. (In this ideal model; the lecture’s point is that the NFET is easier to lay out.)
• Lower $V_{DD}$ with a large $V_T$ and few branches: the internal nodes stop at $V_{DD} - V_T$ and the drop is smaller than the formula alone gives.

Common mistakes.

• Expecting the node to fall only if a path to ground exists. Charge sharing needs no path, only empty capacitance.
• Using $C_{int}/C_X$ as the fractional drop. It is $C_{int}/(C_X + C_{int})$Cint​).

Check yourself In FN12-5a, a footed dynamic gate has A above B above the footer; the dynamic node D is 50 fF, the node C between A and B is 10 fF, V_DD = 2.5 V. In evaluate, A and B are 0, C is at ground, D is precharged; then A rises. What is the final voltage on D? What could go wrong?

$V_D = 2.5 \times 50/(50 + 10) = 2.08\,\mathrm{V}$ (C rises to the same 2.08 V, below the NFET’s limit $V_{DD} - V_T$ for any $V_T$ under about 0.4 V). The 0.42 V drop is charge-sharing noise; the domino inverter is skewed toward its PFET, switches above $V_{DD}/2$VDD​/2, and may read the node as 0: a false evaluation. (FN12-5a’s key gives 2.08 V.)

Check yourself FN12-5b asks for two circuit changes that reduce the charge sharing above. Give three, with the cost of each.

A weak half latch on the dynamic node (slows every real evaluation, which must fight it). A clocked device precharging node C, a PFET on clk to V_DD or an NFET on clk̄ (more power and a slower evaluation; the NFET is easier to lay out among NFETs). A weak always-on device on C, such as an NFET with its gate at V_DD (a constant fight during evaluation, so it must be weak). These are babysit devices (46:44).

11. Coupling noise

The idea. A switching wire next to a quiet one pulls it through the capacitance between them. A driven wire recovers; a floating dynamic node does not.

Lecture11 @ 51:48Coupling noise: the switching aggressor and the quiet victim; a driven victim recovers, a floating dynamic node stays down.

Two wires that run next to each other, or one above the other, have a capacitance between them (47:57) board. When one of them switches (the aggressor), the other (the victim), which should stay quiet, sees a blip (48:43–49:09). If the victim is driven, its driver pushes it back. How big the blip is depends on the coupling capacitance relative to the victim’s other capacitance and on the strength of the victim’s driver; the course quantifies it later, with interconnect (49:09–49:37).

Two places where it hurts a dynamic gate:

1. On an input (49:48). A blip on one of the pull-down’s inputs can turn its NFET on briefly and discharge the dynamic node: a false evaluation that the input’s own recovery doesn’t undo (Section 4: a dynamic node can’t recover).
2. On the dynamic node itself (50:20). A truly floating node, pulled down by a switching aggressor, “will never recover” board. With a half latch it does recover, unless it dropped far enough to switch the inverter first, in which case the gate glitches, and the glitch may be caught by a latch (50:51–51:27).

The defences (51:27–51:57): size the half latch for it, and in layout protect the dynamic node: no significant aggressors next to it.

Check yourself A dynamic gate's input is driven by a strong inverter that holds it at 0. A neighbouring wire switches, and the input blips up to 0.4 V for 20 ps before its driver pulls it back. Why can the gate still give the wrong answer?

During the blip the input’s NFET is partly on and drains charge from the dynamic node. When the input returns to 0, nothing puts that charge back until the next precharge (49:48). If the node has lost enough to cross the inverter’s switching threshold, the output is wrong for the rest of the cycle.

12. Power-supply noise

The idea. If the supply is low when the node is precharged and high when it is read, the inverter sees the difference as noise.

Lecture11 @ 57:33Power-supply noise: precharged at V_DD′, read against V_DD; the difference V_DD − V_DD′ is noise on the node; the half latch lets it track V_DD.

The supply is not constant (52:43) board. Many circuits switching at once draw current through the impedance of the supply network, and the rails droop, or collapse toward each other and back, ringing together (53:06–53:48). Power-distribution networks, decoupling capacitance and grids to reduce resistance and inductance come later, with interconnect (53:48–54:19).

The effect on a domino gate (54:52–56:11) board:

1. Suppose the precharge happens when $V_{DD}$ is at its lowest, $V_{DD}'$VDD′​. The dynamic node is charged to $V_{DD}'$ and then floats.
2. In evaluate the supply has come back up to $V_{DD}$VDD​. The inverter now compares the stored $V_{DD}'$ against its own higher supply.
3. To the inverter the node looks low by $V_{DD} - V_{DD}'$ board: a DC noise on the dynamic node.

The fixes (56:11–56:41): first, reduce the supply noise itself. Second, the half latch: its source is tied to $V_{DD}$VDD​, so as the supply rises it pulls the node up with it, and the node tracks $V_{DD}$VDD​.

Next lecture (56:56). How to size dynamic logic with the same gain-based method as static CMOS, and the speed it gains from dropping the PFETs; two variants of domino, zipper logic and delayed-reset domino; then latches and clocking. The sizing and the two variants are in Chapter 12; latches are past the midterm.

Check yourself A domino gate is precharged while the supply has drooped to 1.1 V; in evaluate the supply is back at 1.2 V. Its inverter switches at 0.6 V_DD. On top of that, the charge sharing of Section 10 (C_X = 40 fF, C_int = 24 fF) occurs. Does it falsely evaluate? Would either problem alone?

Charge sharing from 1.1 V: $1.1 \times 40/64 = 0.69\,\mathrm{V}$0.69V, below the 0.72 V switching point: it falsely evaluates. Supply noise alone leaves 1.1 V (fine); charge sharing alone, from 1.2 V, leaves 0.75 V (just fine). Noise sources add, which is why each one must be kept well inside the margin. A half latch would help with both.

Formulas to remember

Formula	Meaning
pseudo-NMOS: low not at ground; static current when low	the two problems of ratioed logic; turn the load off for $I_{DDQ}$ tests
equal widths: NFET $R$ down, $2R$ up; PFET $2R$ up, $4R$ down	the lecture’s pass-transistor model
$R \parallel 4R = 0.8R$ down, $2R \parallel 2R = R$ up	so the pass PFET is sized equal to the pass NFET; size with the driver (one CCC)
exactly one / both / neither network connected	static / ratioed / dynamic
clk = 0 precharge (node to $V_{DD}$VDD​); clk = 1 evaluate	the dynamic gate; a floating 1 is held only by charge
footer: clocked NFET at the foot, in series	prevents collisions in precharge; counts in the evaluate stack
node $= \overline{f}$f​, domino output $= f$	$f$ is the pull-down’s switching function; domino is non-inverting
delay $= (R_{nfet}/W_{stack})\,C_{load}$(Rnfet​/Wstack​)Cload​, footer included	evaluate delay; the precharge device is off
dynamic into dynamic on one clock: a race	cured by the domino inverter (precharged outputs are 0)
strong-PFET inverter after the node	skewed; switches higher, smaller $NM_H$ for the node
half latch ≈ 1/10 of the pull-down’s strength	weaken by W↓, then a series device with long L; the output-driven device at $L_{min}$Lmin​, $W_{min}$
$V = V_{DD}\,C_X/(C_X + C_{int})$Cint​), internal nodes ≤ $V_{DD} - V_T$	charge sharing (added); fixed by babysit devices and the half latch
precharged at $V_{DD}'$VDD′​, read at $V_{DD}$VDD​: noise $V_{DD} - V_{DD}'$	supply noise; the half latch makes the node track $V_{DD}$

The lecture’s boards

Lecture11 @ 02:17 pseudo-NMOS: logic low not full rail; static power

Lecture11 @ 09:27 pass-transistor sizing, PFETs still 4 µm

Lecture11 @ 10:53 IDDQ; CCC; R, 2R, 2R, 4R; 0.8R and R; pass PFET 2 µm

Lecture11 @ 14:24 static NOR and pseudo-NMOS, the PFETs circled

Lecture11 @ 17:08 clocked PFET; floating dynamic node; precharge

Lecture11 @ 20:18 footer (evaluate, foot); precharge device

Lecture11 @ 30:38 race condition; domino logic; non-inverting

Lecture11 @ 35:24 leakage noise; the half latch

Lecture11 @ 38:30 1/10 strength; W↓, L↑; series device

Lecture11 @ 47:02 charge sharing; babysit devices

Lecture11 @ 51:48 coupling noise: aggressor and victim

Lecture11 @ 57:33 power-supply noise: V_DD − V_DD′