12. Domino sizing and delayed reset

Lecture 11 built domino logic and claimed it was fast. Lecture 12 puts a number on that claim with the tool of Chapter 8: a dynamic stage carries no PFETs on its inputs, so its logical effort is below one, two thirds with a footer and one third without. It then sizes a domino gate by gain, exactly as for static CMOS, and attacks the two costs that remain. The inverter after every stage can go if n-type and p-type stages alternate (NP, or zipper, domino). The footer can go if each stage’s clock resets a little later than the one before (delayed reset). At 23:15 the lecture turns to latches and flip-flops; that is where the midterm material ends, and where this chapter stops.

After this chapter you can:

1. find the logical effort of a dynamic stage, footed or footless, n-type or p-type, in either technology convention ($R_{pfet} = 2R_{nfet}$Rpfet​= or equal strengths);
2. size a domino gate backwards from its load for a chosen gain per stage, with a skewed inverter, as the lecture does (5.6 µm, 0.7 µm, 2.1 µm for 50 fF);
3. compute the logical effort of a skewed inverter or gate on the edge that carries the logic, and compare a domino gate’s delay with the static gate it replaces;
4. explain NP (zipper) domino: the p-type stage, its pre-discharge and evaluate devices, why alternating polarities removes the race, and what it costs;
5. read the function and estimate the delay of a p-type dynamic stage (MT23-3, MT24-5);
6. explain why a footless stage collides on an ordinary clock, how a delayed-reset clock prevents it, and why the delays eventually run out of precharge time.

Boxes and equations marked board were written in the lecture. Parts marked added are explanations or examples this guide adds.

Before you start

You need these ideas from earlier chapters. Each is restated here.

• The normalized inverter (Chapter 8). A gate’s gain is the capacitance it drives divided by the input capacitance of the inverter with the same drive. Its logical effort $g$ is its own input capacitance divided by that inverter’s input; $h = C_{out}/C_{in}$Cout​/Cin​; gain $= g \cdot h$h; a path’s delay is $\tau_{inv}\sum g_ih_i$τinv​∑gi​hi​. The balanced inverter is 2W/W (input $3W$3W), or W/W (input $2W$2W) when a problem says the NFET and PFET have equal strength.
• The stack rule (Chapter 7). $k$ equal devices in series act as one device $k$ times narrower. Loads are written as widths: a load $C$ is $C/C_g$ µm of gate.
• Equal gains (Chapter 8). With $F = \prod g_ih_i$ fixed, the delay $\sum g_ih_i$ is smallest when every stage has the gain $F^{1/N}$F1/N. Size backwards from the load.
• The domino stage (Chapter 11). A clocked precharge PFET charges the dynamic node X to $V_{DD}$ while clk = 0; while clk = 1 an NFET network discharges it or leaves it floating. The clocked NFET at the foot (the footer, evaluate or foot device) prevents a collision when precharge begins with the network still on. An inverter follows; its output Y is the function, and a weak half latch usually holds X.
• The race (Chapter 11). A dynamic node fed straight into the next dynamic stage is 1 after precharge, so it starts discharging the next stage before it has decided. The domino inverter makes every precharged output 0.
• The skewed inverter (Chapter 11). All logical transitions are on one edge (X falls, Y rises), so the inverter’s PFET is made strong and its NFET weak. A strong-PFET inverter switches at a higher input voltage, which shrinks the dynamic node’s high noise margin (Chapter 6).

Notation. X is the dynamic node of an n-type stage and Y its domino output, as in Chapter 11. Sizes such as “2/1” mean a PFET 2 µm and an NFET 1 µm wide. n-type: NFETs evaluate, the node is precharged to 1. p-type: PFETs evaluate, the node is pre-discharged to 0 (the board’s word). $\overline{\text{clk}}$ is the complement of the clock. “Strength” is drive: a PFET has half an NFET’s strength at the same width when $R_{pfet} = 2R_{nfet}$2Rnfet​.

1. The domino stage and the edge that matters

The idea. In a domino stage only one transition carries the logic: the dynamic node falling, then the inverter’s output rising. The precharge PFET is not on that path at all, so it can be small.

Lecture12 @ 02:07The domino stage (left, with its half latch), and the question of the lecture's first part: the logical effort of the dynamic stage alone (its precharge PFET circled).

The lecture opens with the domino stage of Lecture 11 (00:06) board: a precharge PFET on the clock, the logical inputs, a footer on the clock, an inverter, and “usually a half latch here for noise considerations” (00:33). It is non-inverting. The question for this lecture: what does dynamic logic bring to delay? Logical effort answers it (00:47).

A domino gate is really two stages, the dynamic stage and the inverter (01:19). Take the dynamic stage alone, for now with its evaluate device board.

The first thing to notice (01:47): the size of the precharge PFET is “completely independent of anything associated with the logic delay”. The logic delay is the pull-down of the dynamic node; only the NFETs matter. The PFET only has to be large enough to precharge its node during the precharge phase, and since all gates precharge together, in parallel, it has only its own gate to precharge in that time (02:14).

So, for delay, a dynamic stage is its evaluate network and nothing else. The inverter after it has the mirror property: its logical edge is the rising output, driven by its PFET; its NFET only resets the output during precharge.

2. Logical effort of a dynamic stage

The idea. Compare the dynamic stage with the inverter that pulls down as hard as it does. That inverter carries a PFET twice as wide as its NFET; the dynamic stage’s input carries only an NFET. So its logical effort is below one.

Lecture12 @ 04:07Footed: B and the footer 2 µm each act as a 1 µm NFET; the inverter with that drive is 2 µm/1 µm; g = 2 µm/3 µm = 2/3 < 1. Footless (right): B 1 µm, g = 1/3 (circled on the board by 07:39).

The footed stage

Logical effort of a footed dynamic stage (board, 02:14–03:42)

1. The evaluate path is the input B and the footer, in series, each 2 µm board.
2. Two 2 µm devices in series pull down like one 1 µm NFET (02:41).
3. The balanced inverter with that pull-down is 2 µm/1 µm: its input is $2 + 1 = 3\,\mu\mathrm{m}$ (02:47).
4. The dynamic stage’s input B is a single 2 µm NFET: 2 µm of gate.
5. $g = \dfrac{2\,\mu\mathrm{m}}{3\,\mu\mathrm{m}} = \dfrac23 < 1$ board: better than an inverter (03:14).

Why (03:14): the input doesn’t “carry along” a PFET. A static gate’s input drives an NFET and a PFET; a dynamic gate’s input drives only the NFET. It wins even though the footer makes it a stack.

The footless stage

“Now imagine I was able to get rid of that evaluate device completely” (03:42) board. The same pull-down now needs only a 1 µm NFET; its inverter is still 2 µm/1 µm, so

$$g = \frac{1\,\mu\mathrm{m}}{3\,\mu\mathrm{m}} = \frac13 .$$

That is the whole case for dynamic logic’s speed: no PFETs on the inputs, and, if the footer can go, no stack either. “This also shows you how important it is to get rid of the stack transistor” (04:09). Section 7 shows how.

The general rule

added The two board cases are one rule. Replace the evaluate path (footer included) by the single NFET of the same strength, $W_{eq}$Weq​; the reference inverter has input $(1 + R_{pfet}/R_{nfet})\,W_{eq}$Rpfet​/Rnfet​)Weq​; the input’s own gate width divided by that is $g$g.

Logical effort of an n-type dynamic stageadded

$$g = \frac{C_{in}}{(1 + R_{pfet}/R_{nfet})\,W_{eq}}$$$$g = \frac{k}{3}\quad (R_{pfet} = 2R_{nfet})$$$$g = \frac{k}{2}\quad\text{(equal strengths)}$$

Holds when: a k-high evaluate path of equal devices (footer counted); the input drives one device; drain capacitance ignored. The cases k = 2 (2/3) and k = 1 (1/3) are on the board

The precharge PFET does not appear anywhere: it is off during evaluate. If an input drives two devices (it appears twice in the network), its $C_{in}$ is their sum.

Worked example. added The evaluate delay of Chapter 11’s footed stack (Chapter 11 §4), redone with logical effort: A, B and the footer each 4 µm, 50 fF at $C_g = 2\,\mathrm{fF/\mu m}$ (25 µm).

1. Three 4 µm devices in series: $W_{eq} = 4/3\,\mu\mathrm{m}$4/3μm.
2. With $R_{pfet} = 2R_{nfet}$ the reference inverter’s input is $3 \times 4/3 = 4\,\mu\mathrm{m}$4μm; input A is 4 µm, so $g = 1$ (that is $k/3$ with $k = 3$3).
3. $h = 25/4 = 6.25$6.25; delay $= g \cdot h = 6.25\,\tau_{inv}$6.25τinv​, as Chapter 11 found from $(R/W)C$(R/W)C.
4. At equal strengths the reference is $2 \times 4/3 = 8/3\,\mu\mathrm{m}$8/3μm, $g = 4/(8/3) = 3/2$3/2, delay $= 1.5 \times 6.25 = 9.375\,\tau_{inv}$9.375τinv​.

Common mistakes.

• Counting the precharge PFET in $C_{in}$ or in the reference. The input drives only its NFET; the precharge PFET’s gate is on the clock.
• Leaving the footer out of the stack. It is in the evaluate path: $k$ counts it.
• Using the unbalanced reference. The reference is the balanced inverter (2W/W, or W/W at equal strengths) with the stage’s pull-down strength, exactly as for static gates.

Check yourself A footed dynamic NOR4 has four parallel 2 µm input NFETs over one 2 µm footer, R_pfet = 2R_nfet. What is the logical effort of one input? Of a footless version with 1 µm inputs? Compare with the static NOR4 of Chapter 7.

One input’s evaluate path is that input and the footer: two 2 µm devices, $W_{eq} = 1\,\mu\mathrm{m}$1μm, reference $3\,\mu\mathrm{m}$3μm, so $g = 2/3$ (the parallel inputs don’t change it). Footless with 1 µm inputs: $g = 1/3$1/3. The static NOR4 has NFETs $W$ and four series PFETs of $8W$8W: $g = (1 + 8)/3 = 3$3, four and a half times the footed dynamic NOR’s. A wide NOR is where dynamic logic gains most.

Check yourself In MT17-3c, a dynamic gate has a 1 µm clocked PFET and three 4 µm NFETs in series (A, B and the clocked footer) driving 50 fF, C_g = 2 fF/µm, and the NFET and PFET have equal strength. Use logical effort to find the delay from A rising, in τ_inv.

Equal strengths: the reference inverter is W/W. $W_{eq} = 4/3\,\mu\mathrm{m}$4/3μm, reference $8/3\,\mu\mathrm{m}$8/3μm, $g = 4/(8/3) = 3/2 = k/2$k/2. $h = 25\,\mu\mathrm{m}/4\,\mu\mathrm{m} = 6.25$6.25. Delay $= 1.5 \times 6.25 = 9.375\,\tau_{inv}$9.375τinv​, the same as Chapter 11’s $(R/W)C$ route; the 1 µm PFET plays no part. (This is MT17-3c; its key’s 9.375 τ_inv is right.)

3. Sizing a domino gate

The idea. Size it like any path: work back from the load with the target gain per stage, on the edges that carry the logic. The inverter’s PFET gets the gain; its NFET is made several times weaker; the dynamic stack is sized to drive the inverter’s input.

Lecture12 @ 08:54Sizing a domino AND for 50 fF (25 µm) with a gain of 3 per stage: inverter 5.6 µm over 0.7 µm, stack 2.1 µm each, precharge PFET 0.7 µm.

The lecture’s example

A domino AND gate: a clock device, inputs A and B, the footer, then the inverter, loaded with 50 fF (05:02–05:16) board. Take $C_g = 2\,\mathrm{fF/\mu m}$ (the lecturer notes that the class’s technology is closer to 1, 05:29), so the load is 25 µm of gate. Size each stage for a gain of 3, and only in the direction that carries the logic: the pull-down of the dynamic node, the pull-up of the inverter (05:58). The precharge directions don’t matter.

Sizing the domino AND (board, 05:58–08:51)

1. Inverter PFET. For a gain of 3 into 25 µm, the inverter’s normalized inverter has input $25/3\,\mu\mathrm{m}$ and NFET $25/(3 \cdot 3)$3); its PFET is twice that board: $\dfrac{25\,\mu\mathrm{m}\,(2)}{(3)(3)} = 5.6\,\mu\mathrm{m}$ (06:26–06:50).
2. Inverter NFET. Rule of thumb: the inverter’s PFET at least four times stronger than its NFET (06:58). A PFET has half the strength per micron, so the NFET is $4 \times 2 = 8$ times narrower: $5.6/8 = 0.7\,\mu\mathrm{m}$ board (07:21).
3. The dynamic stage’s load is the inverter’s input: $5.6 + 0.7\,\mu\mathrm{m}$ (07:50).
4. Its normalized NFET for a gain of 3: divide by 3, and by 3 again: $(5.6 + 0.7)/((3)(3)) = 0.7\,\mu\mathrm{m}$0.7μm.
5. The stack. A, B and the footer are three in series, so each is three times that board: $\dfrac{5.6 + 0.7}{(3)(3)} \times (3) = 2.1\,\mu\mathrm{m}$ (08:16).
6. The precharge PFET just has to precharge the node in time: “maybe I make this seven tenths micron or something like that” board (08:24). Then check that every stage precharges within the precharge phase.

“And that’s how you size a domino gate using the same kind of tricks that we used for … gain-based sizing for complementary static CMOS” (08:51).

added Unrounded: $W_p = 50/9 = 5.556\,\mu\mathrm{m}$5.556μm, $W_n = 0.694\,\mu\mathrm{m}$0.694μm, the inverter’s input $6.25\,\mu\mathrm{m}$6.25μm, and each stack device $25/12 = 2.083\,\mu\mathrm{m}$2.083μm. The board’s rounded values give 2.1 exactly.

Domino AND of1 input2 inputs3 inputs4 inputsfooter in

Technology:R_pfet = 2R_nfetequal strengthsC_g = 2 fF/µmC_g = 1 fF/µmthe lecture's example

load C_L

50 fF

gain per stage

3.0

inverter skew (PFET ÷ NFET strength)

4.0×

stage	g	h	gain g·h
dynamic (3-high)	1.000	3.00	3.00
skewed inverter (rising)	0.750	4.00	3.00

C_in of each input

4.17 fF

H = C_L/C_in

12.00

domino delay

6.00 τ_inv

F = G·H

9.00

inverter width ratio

8.0 : 1

inverter g, falling edge

3.00

static NAND2 + inverter

8.00 τ_inv

its F (g = 1.33)

16.00

The lecture's board: inverter 5.6 µm over 0.7 µm, stack 2.1 µm each (here unrounded). Each stage has gain 3, so the gate takes 6 τ_inv; a static AND from the same input to the same load needs 8.

Sizes come from the delay model of Chapter 7 (drain capacitance ignored), worked back from the load as the lecture does: the inverter's PFET is twice (or, at equal strengths, once) the NFET of the inverter whose gain is the target; its NFET is that divided by the skew; each stack device is k times the dynamic stage's normalized NFET. The precharge PFET does not appear in any delay: it only has to precharge the node within the precharge phase (the lecture picks 0.7 µm). Logical effort is on the edge that carries the logic: the node falling, the output rising.

What to notice.

• At the lecture’s settings each stage has gain 3, so the gate takes $6\,\tau_{inv}$6τinv​.
• Remove the footer: the stack drops to two devices, each narrower (1.39 µm), and the input capacitance the gate presents falls with it; the gains stay 3.
• Raise the skew: the inverter’s NFET shrinks, its rising-edge logical effort falls toward 2/3 (its input is nearly all PFET), and the stack can shrink too. The price is the inverter’s switching threshold and noise margin (Chapter 11 §7).
• Switch to equal strengths: the inverter’s PFET halves, and every effort is measured against a W/W inverter.

Common mistakes.

• Sizing the inverter’s NFET for its own gain. It only resets the output during precharge; it is set by the skew, not by the load.
• Forgetting that four times stronger means eight times wider when $R_{pfet} = 2R_{nfet}$2Rnfet​.
• Sizing the precharge PFET by gain. It has no logic delay; it only has to finish precharging in time.

Check yourself Size a footed two-input domino AND for a 60 fF load with C_g = 2 fF/µm, a gain of 3 per stage, R_pfet = 2R_nfet, and an inverter PFET four times stronger than its NFET. What is the delay in τ_inv? And the stack widths if the footer is removed (same gains)?

The load is 30 µm. Inverter: normalized NFET $30/9 = 3.33\,\mu\mathrm{m}$3.33μm, so the PFET is $6.67\,\mu\mathrm{m}$ and the NFET $6.67/8 = 0.83\,\mu\mathrm{m}$0.83μm; the inverter’s input is $7.5\,\mu\mathrm{m}$7.5μm. Dynamic stage: $7.5/9 = 0.83\,\mu\mathrm{m}$0.83μm, times 3 for the three-high stack: 2.5 µm each for A, B and the footer. Delay $3 + 3 = 6\,\tau_{inv}$6τinv​. Footless: a two-high stack, $0.83 \times 2 = 1.67\,\mu\mathrm{m}$ each; its $g$ is $2/3$ and $h = 7.5/1.67 = 4.5$4.5, still a gain of 3.

4. What the domino gate gains

The idea. Both stages of the sized gate have logical effort at or below one, so the domino gate needs less path effort than the static gate it replaces. But it is still two stages.

The logical efforts of the result

“This one will be similarly driven down below one because it’s a skewed inverter” (09:02). added The numbers, by the definition of Section 2 applied to each stage’s logical edge:

The efforts of the 50 fF domino AND (added)

1. Skewed inverter, rising edge. Its 5.556 µm PFET pulls up like the PFET of a 5.556/2.778 µm balanced inverter, input $8.33\,\mu\mathrm{m}$8.33μm. Its own input is $6.25\,\mu\mathrm{m}$6.25μm: $g = 6.25/8.33 = 3/4$3/4. Its $h = 25/6.25 = 4$4; gain 3.
2. Skewed inverter, falling edge (the precharge reset): its 0.694 µm NFET’s balanced inverter has input $2.08\,\mu\mathrm{m}$2.08μm, so $g = 3$3. That edge has time to spare; it is not on the logic path.
3. Dynamic stage. A three-high stack: $g = 3/3 = 1$1, the inverter’s value. $h = 6.25/2.083 = 3$3; gain 3.
4. The gate’s path effort is $F = G \cdot H = (1 \times 3/4) \times (25/2.083) = 0.75 \times 12 = 9$9, and $2 \times \sqrt{9} = 6\,\tau_{inv}$6τinv​.

The lecturer says of the dynamic AND stage that its effort is “greater than one here, but … better than it would for a complementary static CMOS of the same logic function” (09:22). By his own rule it is exactly one for a three-high stack; the comparison holds either way, since the static NAND2 has $4/3$4/3.

Worked example: against static CMOS. added The static AND is a NAND2 and an inverter. Give it the same input capacitance (2.083 µm per input) and the same 25 µm load, sized for equal gains:

1. $H = 25/2.083 = 12$ for both.
2. Static: $G = 4/3 \times 1$1, $F = 16$16, two stages of gain 4: $8\,\tau_{inv}$8τinv​.
3. Domino: $G = 1 \times 3/4$3/4, $F = 9$9, two stages of gain 3: $6\,\tau_{inv}$6τinv​. A quarter faster, before counting that the static gate also fights crowbar current.

Skewed gates in general

added The same definition gives any skewed gate’s effort: input capacitance over the balanced inverter that has the same strength on the edge that matters. A static gate after a domino stage, which only ever switches one way during evaluate, can be skewed toward that edge too. Exams that allow it give a limit on the strength ratio (for example “no more than 4 or less than 1/4”).

Check yourself A static NAND2 follows a dynamic stage and only its falling output matters. Its NFETs are W each; its PFETs are skewed to W/4 each (R_pfet = 2R_nfet). What is its logical effort on the falling edge, and on the rising edge? What is its PFET:NFET strength ratio?

Falling: the two NFETs act as $W/2$W/2; the balanced inverter with that pull-down has input $3 \times W/2 = 1.5W$1.5W; the NAND’s input is $W + W/4 = 1.25W$1.25W, so $g = 1.25/1.5 = 0.83$ (the unskewed NAND2’s $4/3$4/3). Rising: one PFET $W/4$ alone; its balanced inverter is $W/4$ over $W/8$W/8, input $0.375W$0.375W: $g = 1.25/0.375 = 3.3$3.3. Strength ratio: the PFET’s $W/8$ (NFET-equivalent) over the NFET stack’s $W/2$ is $1/4$1/4, the limit. (This is the step FN10-9b and FN19-8b need; their key uses 0.833.)

Check yourself A domino path: (I) a dynamic OR with 1 µm inputs over a 1 µm footer drives (II) an inverter with a 4 µm PFET and 1 µm NFET, which drives (III) a dynamic gate of three 1 µm NFETs in series (footer included), which drives (IV) another 4/1 µm inverter loaded by 500 fF. C_g = 2 fF/µm, R_nfet = 4 kΩ·µm, R_pfet = 8 kΩ·µm, so τ_inv = 24 ps. Estimate the evaluation delay through all four stages.

Logical edges: I and III fall, II and IV rise. (I) $g = 2/3$2/3, $h = 5/1$5/1: gain 3.33. (II) the 4 µm PFET matches a 4/2 balanced inverter (input 6 µm), $g = 5/6$5/6; it drives III’s 1 µm input, $h = 1/5$1/5: gain 0.17. (III) $g = 3/3 = 1$1, $h = 5/1$5/1: gain 5. (IV) $g = 5/6$5/6, $h = 250/5 = 50$50: gain 41.7. Sum 50.2 τ_inv = 1.20 ns. The gains are badly unbalanced: with stage I’s input fixed, $F = G \cdot H = 0.463 \times 250 = 115.7$ and four equal gains of $115.7^{1/4} = 3.28$ would take about $13.1\,\tau_{inv} = 315\,\mathrm{ps}$315ps. (This is FN12-8; its key writes the sum as 50.76 and the product as 128.94.)

Still two stages

The domino gate gains on logical effort, “but I still need two stages” (09:33). The inverter is there only because of the race: a dynamic node fed straight into the next dynamic stage starts it discharging before it has decided (10:00, Chapter 11 §5). Is there another way to avoid the race?

5. NP (zipper) domino

The idea. Alternate the polarity. After an n-type stage, whose node rests at 1, put a stage whose evaluating devices are PFETs: a 1 is “off” for a PFET. That p-type stage’s node rests at 0, which is “off” for the NFETs of the next n-type stage. No inverters, no race.

Lecture12 @ 16:07NP (zipper) domino: an n stage (precharge PFET, PDN, evaluate footer on clk) feeds a p stage (evaluate PFET on clk̄, PUN of PFETs, pre-discharge NFET), which feeds the next PDN.

The lecturer only teaches circuit styles that were used in real microprocessors (10:21). This one was: the Digital Equipment Corporation’s Alpha processors of the early 1990s used it widely, in a fully custom design he remembers its engineers presenting “like the tablets coming down from the mountain” (10:47–12:31).

The structure

Start with an ordinary n-type dynamic stage (12:51–13:08) board: the precharge PFET on clk, a pull-down network (PDN) of NFETs, the evaluate (foot) device on clk. Instead of an inverter, its node feeds a second stage built the other way up (13:08–13:58) board:

• a pull-up network (PUN) of PFETs, which does the logic;
• above it, a PFET on $\overline{\text{clk}}$clk: the evaluate device of this stage (on while clk = 1);
• below it, an NFET to ground: the pre-discharge device, on while clk = 0.

While clk = 0, the n stage’s node is precharged to 1 and the p stage’s node is pre-discharged to 0 (13:58). While clk = 1, both evaluate. The p stage’s node feeds another PDN, on clk again, and so on: N, P, N, P, hence “NP domino” (14:25).

(The pre-discharge NFET’s gate is $\overline{\text{clk}}$clk. The lecturer says “clock” for it at 13:37, and its board label is hard to read, but it must be on while clk = 0, “when clock bar is high” as he says at 13:58; on clk it would fight the PUN in every evaluate phase.)

The zipper, and no race

When the dominoes fall, the n node falls down to 0 and the p node falls up to 1: one going down, one going up, “like a zipper opening” (14:43). And there is no race (14:52):

• after precharge the n node is 1, which is off for the PFETs of the p stage it drives, so they can’t turn on falsely;
• the pre-discharged p node is 0, which is off for the NFETs of the next pull-down, so that stage can’t evaluate early either.

Each stage waits for its input to evaluate, as in domino, without the inverters (15:13).

Chain:NP (zipper) dominon-type into n-type, no invertersdomino (inverter after every stage)

Input A:A = 1A = 0Evaluate:prechargeone stepplay

After precharge the n nodes are 1 and the p nodes 0. A 1 on a p stage's PFET input and a 0 on an n stage's NFET input are both "off": no stage can start before its input has evaluated.

Switch level with unit delays, added to show the zipper: each node (and each inverter) responds one step after its input, and a node that has evaluated stays put until the next precharge. Each stage has a single input, so logically each node is the complement of its input; a real stage has more inputs in its network. Colours: 1, 0. In the NP chain the p stages' header and pre-discharge device take clk, so every stage evaluates while clk = 1.

What to notice.

• NP with A = 1: the nodes go 0, 1, 0, 1 in four steps, one stage per step.
• n into n without inverters: every stage after the first is already on after precharge, and the stages that should hold their 1 lose it: the race.
• Domino with inverters: correct, but eight steps for four stages. NP removes those four inverter stages.

The cost

“The negative, of course, here is that my pull-up network is now PFETs” (15:13), and PFETs are worse than NFETs in most technologies. The Alpha designers argued, “quite correctly” in the lecturer’s view, that getting rid of the inverters still brings a delay advantage (15:43). Section 6 puts a number on the cost.

Check yourself In FN12-10b an n-type dynamic stage (precharge PFET and footer on clk) produces Y; Y drives a PFET in a second stage whose top PFET and bottom NFET both take clk, made by an inverter from clk. During which phase of clk does Y evaluate? And Z, the second stage's node?

Both evaluate while clk is high. Y’s stage evaluates with clk = 1 (precharge PFET off, footer on). The second stage is p-type: its header PFET on $\overline{\text{clk}}$ conducts when $\overline{\text{clk}}$ = 0, i.e. clk = 1, and its pre-discharge NFET on $\overline{\text{clk}}$ holds Z at 0 while clk = 0. This is NP domino: Y rests at 1 (off for the PFET it drives) and Z rests at 0. (FN12-10b’s key: both evaluate for clk high.)

Check yourself Why can't a p-type dynamic stage drive another p-type stage directly, any more than an n-type stage can drive an n-type stage?

A pre-discharged p node is 0, and a 0 turns a PFET on. The second p stage would start charging its node before the first had decided: the same race, mirrored. NP domino works because each stage’s resting value is “off” for the devices of the next, which needs the polarity to alternate.

6. Working with p-type stages

The idea. A p-type stage is the mirror of the n-type one. Its node rises when its PFET network conducts, its logical effort uses the PFET-side reference, and the inverter after it (where one is used) is skewed toward its NFET.

Reading the function

added A PFET conducts on a 0: series PFETs conduct when all their gates are 0, parallel ones when any is. The p node rises when the network conducts, so the node equals the network’s conduction function $f$f, and an inverter after it gives $\overline{f}$f​. (For an n-type stage it is the other way round: node $\overline f$f​, domino output $f$f.)

Check yourself MT24-5a's first stage is p-type: a clocked header PFET above a network of PFETs (A ∥ B) in series with C, all in parallel with A in series with B, and a clocked pre-discharge NFET below; an inverter follows. What does the p node compute, and the inverter?

The network conducts when $(\overline A + \overline B)\,\overline C + \overline A\,\overline B$AB. That simplifies to $\overline{AB + AC + BC}$AB+AC+BC​: the complement of the majority (the full adder’s carry). The node rises when the network conducts, so the node is $\overline{\text{carry}}$ and the inverter gives Carry $= AB + AC + BC$BC. (This is MT24-5a’s first stage; the key agrees. The exam’s figure gates the pre-discharge NFET with $\overline{\text{clk}}$clk, as it must be; the lecturer says “clock” at 13:37.)

Logical effort of a p-type stage

added Mirror Section 2: replace the evaluate path (header included) by one PFET of the same strength, $W_{eq}$Weq​. The balanced inverter with that pull-up has a PFET $W_{eq}$ and an NFET $W_{eq}R_{nfet}/R_{pfet}$Weq​Rnfet​/Rpfet​.

Logical effort of a p-type dynamic stageadded

$$g = \frac{C_{in}}{(1 + R_{nfet}/R_{pfet})\,W_{eq}}$$$$g = \frac{2k}{3}\quad (R_{pfet} = 2R_{nfet})$$$$g = \frac{k}{2}\quad\text{(equal strengths)}$$

Holds when: a k-high PFET evaluate path of equal devices (header counted); the input drives one device; drain capacitance ignored

With $R_{pfet} = 2R_{nfet}$ a p-type stage has twice the logical effort of the n-type stage with the same stack: a two-high p stage has $4/3$ where the n stage has $2/3$2/3. That factor is the lecturer’s “PFETs are worse” (15:13) as a number. With equal strengths the two are the same.

Check yourself MT24-5 (equal strengths; every device 2 µm). Stage 1 is p-type: input A drives two PFETs, and A's worst evaluate path is three high (header, A, C). Stage 2 is n-type: its input from stage 1's node drives one NFET in a three-high path (that NFET, one of A, B, C, the footer). Find both logical efforts.

Stage 1: $W_{eq} = 2/3\,\mu\mathrm{m}$2/3μm; the W/W reference has input $4/3\,\mu\mathrm{m}$4/3μm; A drives $2 + 2 = 4\,\mu\mathrm{m}$4μm: $g_1 = 4/(4/3) = 3$3. Stage 2: same path strength, input 2 µm: $g_2 = 2/(4/3) = 3/2$3/2. (These are MT24-5b’s first two efforts; the key agrees. The midterm kit (M6) takes the delay from there.)

Delays and the inverter after a p node

added A p node rests at 0, rises in evaluate, and is threatened by noise that pulls it up. An inverter after it carries the logic on its falling edge, so it is skewed toward a strong NFET: that lowers its switching threshold and shrinks $NM_L$NML​, the margin that protects the resting 0 (the mirror of Chapter 11 §7). The mirror of the half latch is a weak NFET from the node to ground, driven by the inverter’s output.

Check yourself MT23-3: a p-type stage (clocked PFET M1 above PFETs A ∥ B̄ in series with Ā ∥ B, all 3 µm) drives an inverter with M4 = 10 µm NFET and M3 = 5 µm PFET, loaded by 50 fF. C_g = 1 fF/µm, R_nfet = 1 kΩ·µm, R_pfet = 2 kΩ·µm. With A = 0, find the delay from B falling to Y falling with logical effort.

τ_inv = 3 × 1 × 1 = 3 ps. Stage 1: B falling turns on the 3 µm PFET B; with A = 0 the charging path is M1, A, B: three 3 µm PFETs, $W_{eq} = 1\,\mu\mathrm{m}$1μm, reference $1 + 0.5 = 1.5\,\mu\mathrm{m}$1.5μm, $g = 3/1.5 = 2$2; the node drives M3 + M4 = 15 µm, $h = 15/3 = 5$5: gain 10. Stage 2: Y falls through M4 (10 µm), whose balanced inverter is 20/10 µm (30 µm): $g = 15/30 = 0.5$0.5, $h = 50/15$50/15: gain 1.67. Total $11.67\,\tau_{inv} = 35\,\mathrm{ps}$35ps, the same as $(R/W)C$(R/W)C: $2\,\mathrm{k\Omega} \times 15\,\mathrm{fF} + 0.1\,\mathrm{k\Omega} \times 50\,\mathrm{fF}$50fF. (MT23-3b; its key uses $0.69RC$0.69RC, labels ps as ns, and counts one PFET in stage 1 instead of three in series: about 24.2 ps with the 0.69. The inverter’s strong NFET is the skew MT23-3c asks about.)

7. Dropping the footer: delayed-reset clocks

The idea. A footless stage collides only if its precharge starts while its input is still 1. Give it a clock whose falling edge comes a little later, after the stage that drives it has finished its own precharge and its output has fallen to 0.

Lecture12 @ 20:29The footer dropped from the second stage (its clk device struck through) and its clock replaced by clk′, whose falling edge (reset) comes later than clk's: the duty cycle goes above 50%.

Why the footer is there, and what it costs

The evaluate device is there to prevent collisions (16:06): entering precharge, the pull-down may still be on, and without a footer current flows straight from $V_{DD}$ to ground. It also costs a device in every stack: Section 2’s $2/3$ against $1/3$1/3. “The other thing that would really be nice to do here is to get rid of this evaluate device” (16:06).

The collision on one clock

Start with a normal, footed domino stage, and drop the evaluate device from the stage it drives (16:59–17:40) board. Put both on the same clock and follow one precharge (18:10–18:41):

1. Suppose stage 1 evaluated: its output is 1, so stage 2’s input NFET is on.
2. clk falls. Stage 2’s precharge PFET turns on at once, while its input NFET is still on (nothing has reset stage 1’s output yet): a short-circuit current spike.
3. Eventually stage 1 precharges, its output falls, stage 2’s NFET turns off and the spike ends.

“One way to handle this is to say, well, just let it burn” (18:41): the answer is still right in the end. But every stage waits for the one before it to precharge, burning short-circuit power all the while (19:13).

The delayed-reset clock

The better way (19:13) board: drive stage 2 with a different clock, clk′, “whose reset is slightly delayed”. How long a delay? “Long enough to give this first gate time to precharge” (19:48): by the time stage 2 starts precharging, stage 1’s output is already 0, and no short-circuit current can flow.

clk′ rises with clk (evaluation starts together) but falls later, so it is high for more than half the period: its duty cycle, the fraction of the period the clock is high, is above 50% (20:22) board.

Lecture12 @ 22:29The pattern: footed (clk), footless (clk′), footless (clk″), then footed (clk) again; each footless clock's reset is delayed more, and its precharge phase gets shorter.

Running out of time, and starting again

A third stage, also footless, gets clk″, its reset delayed even more (20:49) board. And so on, but not for ever: each delay comes out of the precharge phase, and “eventually I’m not gonna have enough time to precharge here anymore” (21:04). Then put a footed stage back, on clk again, and repeat (21:20) board. A footed stage cannot collide whatever its inputs are doing: its footer is off whenever its precharge PFET is on. Typically there are about three footless stages between footed ones: footed, footless, footless, footless, footed (21:57–22:05).

Clocks like these are “almost standard fare”: one global clock is distributed over the chip, and local clock generators make the delayed versions (22:05–22:35); clock distribution comes later in the course. Together, they let the designer drop evaluate devices “without paying the penalty of short-circuit current” (22:47).

added A time budget makes “eventually” a number. If the precharge phase lasts $T_P$TP​, each stage needs $t_p$ to precharge (its node up and its inverter’s output down), and each footless clock falls $\Delta \ge t_p$ after the one before, the $k$-th footless stage starts precharging $k\Delta$ late and needs

$$k\,\Delta + t_p \le T_P .$$

Footless stages after the footed one:1234all on the same clock

reset delay per stage

100 ps

time a stage needs to precharge, t_p

100 ps

stage	clock	precharge starts (after clk falls)	window	collision	duty
footed	clk	0 ps	400 ps	none (footer)	50.0%
footless 1	clk′	100 ps	300 ps	none	62.5%
footless 2	clk″	200 ps	200 ps	none	75.0%

Works: no collisions, and every stage precharges in time. With this delay and t_p, at most 3 footless stages fit before a footed one is needed.

Clock waveforms as on the board (22:29), with an added time budget. All clocks rise together; each footless stage's clock falls one reset delay after the previous one, so it is high for more than half the period. The thick segment after each falling edge is the stage's precharge, green if it ends before the next evaluate, red if not; red bands are collisions. A collision needs the input stage to have evaluated (its output at 1); the footed stage cannot collide, because its footer is off whenever its precharge PFET is on.

What to notice.

• “All on the same clock”: every footless stage collides for $t_p$tp​, each cycle.
• A delay shorter than $t_p$ shrinks the collision to $t_p - \Delta$ but doesn’t remove it.
• With $\Delta = t_p = 100\,\mathrm{ps}$ and $T_P = 400\,\mathrm{ps}$400ps, three footless stages fit and a fourth has no time: the lecture’s “typically three”.
• The duty cycles climb: 50%, 62.5%, 75% with 100 ps steps in an 800 ps period.

Common mistakes.

• Delaying the rising edge too. Evaluation starts together; only the reset (falling) edge moves.
• Applying delayed reset to stages without the domino inverter. It works because stage 1’s output falls to 0 during precharge. A bare dynamic node rises to 1 during precharge, so delaying the next stage’s precharge until then guarantees the collision it was meant to avoid.

Check yourself A domino path has a 500 ps precharge phase. Each stage needs 120 ps to precharge (node up, inverter output down), and each footless stage's clock falls 120 ps after the previous one. How many footless stages can follow a footed one? What goes wrong if the delay is cut to 80 ps?

The $k$-th footless stage needs $120k + 120 \le 500$500, so $k \le 3.17$3.17: three (their windows are 380, 260 and 140 ps; a fourth would get 20 ps). With 80 ps each, every footless stage starts precharging 40 ps before its input has finished resetting: a 40 ps collision every cycle in which the stage before it evaluated.

Check yourself A footed dynamic NAND (no inverter after it) drives the NFET of a footless dynamic NOR whose precharge PFET is on its own clock φ′. A designer delays φ′'s falling edge until the NAND has finished precharging, as in delayed reset. Does that prevent collisions in the NOR?

No. The NAND’s precharged output is 1, not 0: once the NAND has precharged, the NOR’s input NFET is certainly on, so the NOR’s precharge PFET turns on into a conducting pull-down. Delayed reset relies on the domino inverter, which makes the upstream output fall to 0 during precharge (18:10). Without it, a footless stage driven by bare dynamic nodes collides whenever any of its inputs is 1 while it precharges. (FN17-2 has this circuit; its key’s answer to 2b applies the delayed-reset rule, and should be re-checked.)

End of the midterm material. “That’s all I wanted to say about dynamic logic” (22:56). The lecture returns to dynamic logic only after latches and clocking, and at 23:15 starts sequential design: latches and flip-flops are after the midterm and not in this guide’s midterm chapters.

Formulas to remember

Formula	Meaning
logical edge: node falls (n), domino output rises	size only for it; the precharge PFET is sized just to precharge in time
footed 2 µm + 2 µm: $g = 2/3$2/3; footless 1 µm: $g = 1/3$	the board’s dynamic logical efforts (reference: balanced 2/1 inverter)
n-type: $g = k/3$ ($R_p = 2R_n$Rp​=2Rn​), $k/2$ (equal strengths)	$k$-high evaluate path, footer counted; the precharge PFET never counts
p-type: $g = 2k/3$ ($R_p = 2R_n$Rp​=2Rn​), $k/2$ (equal strengths)	reference: the balanced inverter with the same PFET; twice the n-type’s
inverter PFET $= 2 \cdot C_L/(C_g \cdot f \cdot 3)$3); NFET = PFET/8 for 4:1 strength	domino sizing from the load: 5.6 µm and 0.7 µm for 50 fF, $f = 3$
stack device $= k \cdot (W_p + W_n)/(3f)$	2.1 µm each for the three-high AND
skewed inverter 8:1 in width: $g = 3/4$ rising, $3$ falling	logical effort on each edge
domino AND $6\,\tau_{inv}$ against static $8\,\tau_{inv}$ (same $C_{in}$Cin​, 25 µm)	$F = 9$ against $16$
NP domino: n stage (clk), p stage (header and pre-discharge on $\overline{\text{clk}}$clk), …	resting 1 is off for PFETs, resting 0 off for NFETs: no race, no inverters
p node $= f$ of its PFET network; n node $= \overline f$	which way the node moves when the network conducts
delayed reset: clk′ falls $\ge t_p$ after clk; $k\Delta + t_p \le T_P$	footless stages without collisions; about three, then a footed stage

The lecture’s boards

Lecture12 @ 02:07 domino stage; logical effort of the dynamic stage?

Lecture12 @ 04:07 2 µm/3 µm = 2/3 < 1; footless 1 µm

Lecture12 @ 07:39 domino AND, 50 fF (25 µm); 5.6 µm; 1/3 circled

Lecture12 @ 08:54 5.6 µm, 0.7 µm, 2.1 µm; precharge 0.7 µm

Lecture12 @ 14:07 NP domino: precharge, evaluate, PDN, PUN

Lecture12 @ 16:07 NP and zipper domino; pre-discharge device

Lecture12 @ 20:29 footless stage on clk′; duty cycle

Lecture12 @ 22:29 clk, clk′, clk″; footed again on clk