M3. Past midterms: inverters, energy and devices

This page works every past-midterm problem on inverters: the inverter-chain question that every midterm has asked (switching energy, leakage energy, delay and the energy × delay optimum), the noise-margin questions, the single-gate delays in units of $\tau_{inv}$τinv​, and the device short answers (a forward-biased well, subthreshold current against temperature, FO4 from the transit time). Together they carry 23% to 68% of each past midterm’s points: 23% of MT23, 40% of MT21, 45% of MT24 and 68% of MT17.

Every number below is re-solved here; none is copied from an answer key. Where a key disagrees, the folded note on the key at the end of the part explains why, and the table at the end lists them all.

After this page you can:

1. write a chain’s energy per cycle or per transition, its leakage energy, and its delay as functions of $N$ and $W$W, in the exams’ units;
2. find the width that minimizes energy × delay, and say why “minimize the delay” has no finite answer;
3. find the PFET/NFET ratio that minimizes a chain’s delay ($\sqrt{2}$2​, or 1 with equal strengths);
4. answer the noise-margin questions for noise on every node or on one node, and say how a stronger PFET or a lower gain moves the curve;
5. put an inverter’s or a NAND’s delay into units of $\tau_{inv}$ with equal-strength devices;
6. answer the device short answers: FO4 from $\tau_{tr}$ and $\eta$η, a well tied to the wrong rail, leakage at two temperatures.

Before you start

How to use this page. Each section restates one exam question with its source page (MT23-1b, p3 is Fall 2023, question 1b, physical PDF page 3) and its points, and shows the exam’s own figure. Each family opens with a short How to approach section: how to recognize the question, the moves in order, why the formulas apply, and the traps. Then every part is worked the same way: what it asks, the idea behind the method, the solution in steps (each step gives its reason first), a check on the result, the answer, and one thing to remember. Try each part on your own first; open the Hint if you are stuck, and step through the solution before you press “Show all”. The answer key’s verdict is folded at the end of each part. The chapters teach each method in full, and every solution links the section.

Family	Questions (most recent first)	Points	Chapters
Inverter chain: energy, leakage, delay, optimum	MT24-2, MT23-1, MT21-4, MT17-4	50, 34, 35, 38	4, 6, 7
Noise margins and the VTC	MT24-1, MT17-2, MT17-1a (Section 9)	40, 16, 8	6
Single-gate delays in τ_inv	MT17-3a, b, d	24	7, 8
Device short answers	MT21-2, MT17-1b–c (Section 9)	25, 16	4, 5

MT17-3c (a dynamic gate’s evaluate delay) is on page M6, with the other dynamic-logic problems.

Conventions the exams use

State these at the top of your answer; the keys mix them, and so do the questions.

• Delay model. A transistor of width $W$ driving $C$ takes $(R/W)\,C$(R/W)C, with $R$ in kΩ·µm and $C$ in fF; 1 kΩ × 1 fF = 1 ps (Chapter 7, Section 1). No 0.69 factor unless the question asks for one. MT24-2c’s key accepted answers with and without it.
• τ_inv. The FO1 delay of the balanced inverter. With $R_{pfet} = 2R_{nfet}$ the inverter is 2W/W and $\tau_{inv} = 3R_{nfet}C_g$3Rnfet​Cg​; with equal-strength devices it is W/W and $\tau_{inv} = 2R_{nfet}C_g$ (Chapter 7, Section 7).
• Energy. Each node that rises draws $CV_{DD}^2$ from the supply (Chapter 6, Section 6). “Per transition” (one input edge: only every other node rises) is half of “per cycle” (every node rises once). MT17-4c and MT21-4b ask per transition; MT23-1a and MT24-2a ask per cycle.
• Leakage. Only the device that is off leaks, with the full $V_{DD}$ across it: $E = V_{DD}\,I_{leak}\,T$VDD​Ileak​T. Currents are per µm of width (Chapter 4, Section 11).
• Units. fF × V² = fJ. nA × V × ps = $10^{-21}$ J = $10^{-6}$ fJ. Drain capacitance is ignored unless the question includes it.

How to approach an inverter-chain question

Every past midterm has asked this question, for 23–25% of its points. You get a chain of identical inverters, usually with a fixed capacitance on every output (a side load or a wire), driven by a square wave or a single edge. Then the parts build on each other: the switching energy, sometimes the leakage energy and its share of the total, the delay, and a best width (for energy × delay, for delay alone, or the best PFET width). Recognize it by the picture, a chain with a capacitor on every node, and by the phrase “as a function of N and W”.

The moves, in order.

1. Find the capacitance on one node first. Every part uses it. A node carries the next inverter’s input, which is both of its gates ($W_n + W_p$Wn​+ µm of gate), plus the side load. Ignore drain capacitance unless the question includes it.
2. Read the device strengths. With equal strengths ($R_{pfet} = R_{nfet}$Rpfet​=Rnfet​) the balanced inverter is W/W; with $R_{pfet} = 2R_{nfet}$ it is 2W/W. In a balanced chain the rising and falling delays are equal, so one stage delay serves both edges.
3. Switching energy. Count how many nodes rise in the interval the question names, and charge each one $C_{node}V_{DD}^2$Cnode​VDD2​. Per cycle, every node rises once; per transition, half of them do.
4. Leakage energy. In each inverter exactly one device is off, with the full $V_{DD}$ across it. Get its current from the subthreshold slope, then multiply by $V_{DD}$VDD​, its width and the time.
5. Delay. One stage is $(R/W)\,C_{node}$(R/W)Cnode​; the chain is $N$ stages.
6. Optimum. Write the quantity as a function of $W$ and find where the part that grows with $W$ balances the part that shrinks.

Why these formulas.

• Energy. Raising a node from 0 to $V_{DD}$ pulls the charge $CV_{DD}$ out of the supply at the voltage $V_{DD}$VDD​, so the supply delivers $CV_{DD}^2$CVDD2​. Half is stored on the node and half burns in the PFET. When the node falls, the NFET burns the stored half and the supply delivers nothing (Chapter 6, Section 6).
• Delay. The course models the conducting transistor as a resistor $R/W$R/W, with $R$ in kΩ·µm, that charges or discharges the node; 1 kΩ × 1 fF = 1 ps (Chapter 7, Section 1).
• Leakage. Below threshold the current falls by one decade for every $S$ millivolts that the gate is below $V_T$ (Chapter 4, Section 11).

Traps. Per cycle against per transition. $\tfrac12 CV_{DD}^2$ (stored) against $CV_{DD}^2$ (drawn). The off device’s width when the inverter isn’t W/W. nA, not pA. Leaving $T_{cycle}$ in the answer when the question says it equals the chain’s delay.

1. MT24-2: a W/W chain, energy, leakage and the best width

MT24-2, p4 (source figure; the “W:W” and “N inverters” labels are handwritten on the key).

MT24-2, p4 (Fall 2024, 50 points). A chain of $N$ W/W inverters (both FETs of width $W$W), each loaded by an additional 4 fF of side-branch loading. $C_g = 1\,\mathrm{fF/\mu m}$1fF/μm, $R_{nfet} = R_{pfet} = 1\,\mathrm{k\Omega\cdot\mu m}$1kΩ⋅μm. Ignore drain capacitances. The input is a 50% duty-cycle square wave of period $T_{cycle}$Tcycle​; $V_{DD} = 1.2\,\mathrm{V}$1.2V.

Before the parts: one node. Every part needs the capacitance on one node of the chain, so find it once. On the output of each inverter hang:

• the next inverter’s input. An input is wired to both gates, the NFET’s ($W$W) and the PFET’s ($W$W), so it presents $2W\,C_g$2WCg​;
• the 4 fF side load;
• the inverter’s own drains, which the question tells us to ignore.

$$C_{node} = (2W + 4)\,\mathrm{fF}\quad(W\text{ in }\mu\text{m}).$$

The strengths are equal, so a W/W inverter pulls up exactly as hard as it pulls down: every stage has the same delay on both edges. Its fan-out-of-one delay is $\tau_{inv} = (R/W)(2W\,C_g) = 2RC_g = 2\,\mathrm{ps}$2ps.

MT24-2a: supply energy per cycle

MT24-2a, p4 (10 points). What is the energy drawn from the supply for this chain of N inverters during $T_{cycle}$Tcycle​? Express it as a function of N and W. Ignore crowbar currents.

Hint

Which nodes take charge from the supply during one period of the input, and how much does each one take?

What it asks. The energy the supply delivers to the whole chain in one full period of the input: one rising edge and one falling edge. The words “during $T_{cycle}$Tcycle​” decide how many nodes you count. (Questions that say “per transition” mean one edge, and the answer is half as much.)

The idea. The supply delivers energy only when a node is charged up. Raising a node of capacitance $C$ from 0 to $V_{DD}$ pulls the charge $Q = CV_{DD}$ out of the supply at the voltage $V_{DD}$VDD​, so the supply delivers $QV_{DD} = CV_{DD}^2$CVDD2​. Half of it is stored on the node and half burns in the PFET. When the node falls again, the NFET burns the stored half, and the supply delivers nothing (Chapter 6, Section 6). So the energy per cycle is (the number of nodes that rise in one cycle) × $C_{node}V_{DD}^2$Cnode​VDD2​. The tempting slip is $\tfrac12 CV_{DD}^2$21​CVDD2​: that is the energy stored on a node, not the energy drawn from the supply.

Energy per cycle

1. Count the rising nodes. An inverter’s output rises when its input falls. On the input’s rising edge nodes 2, 4, 6, … rise; on its falling edge nodes 1, 3, 5, … rise. Over one period, every one of the $N$ nodes rises exactly once.
2. Price one rise. Each costs $C_{node}V_{DD}^2 = (2W + 4)\,\mathrm{fF} \times (1.2\,\mathrm{V})^2 = 1.44(2W + 4)\,\mathrm{fJ}$4)fJ, since fF × V² = fJ.
3. Add them up. $N$ rises: $E_{cycle} = 1.44N(2W + 4)\,\mathrm{fJ} = N(2.88W + 5.76)\,\mathrm{fJ}$5.76)fJ, with $W$ in µm.

Check. At $W = 1\,\mu\mathrm{m}$ each node is 6 fF and costs $6 \times 1.44 = 8.64$ fJ per cycle, and the formula gives $2.88 + 5.76 = 8.64$ fJ per inverter. ✓ The 5.76 fJ per inverter that doesn’t depend on $W$ is the side load’s share ($4\,\mathrm{fF} \times 1.44\,\mathrm{V^2}$4fF×1.44V2): no choice of $W$ removes it.

Answer: $E_{cycle} = N(2.88W + 5.76)\,\mathrm{fJ}$5.76)fJ.

Remember. Supply energy = (number of rising nodes) × $CV_{DD}^2$CVDD2​. Per cycle every node rises once; per transition, half of them do.

The answer key agrees

It gives the same expression. A very faint ½ in front of its first line is not carried into its later lines, nor should it be: the ½ is the energy stored, not the energy drawn.

MT24-2b: leakage energy per cycle

MT24-2b, p5 (10 points). What is the total subthreshold leakage energy consumed by these N inverters at 300 K during a cycle? The nFET (pFET) draws $10\,\mu\mathrm{A/\mu m}$ at its threshold voltage of 200 mV (−200 mV); the subthreshold slope is 90 mV/decade for both.

Hint

In each inverter one transistor is off. How far below its threshold is its gate, and what does the subthreshold slope say that costs in current?

What it asks. Part (a) was the energy spent switching. This part is the energy wasted while nothing switches: current through transistors that are meant to be off. Three things decide it: which transistor is off (and how wide it is), how much current it still passes, and for how long.

The idea. A MOSFET doesn’t shut off at its threshold. Below $V_T$ its current falls exponentially, by one decade (a factor of 10) for every $S$ millivolts that the gate is below threshold, where $S$ is the subthreshold slope (Chapter 4, Section 11):

$$I = I(V_T) \cdot 10^{-(V_T - V_{GS})/S}$$

(for the PFET, in magnitudes). An “off” transistor has $V_{GS} = 0$0, so its gate sits a full $V_T$ below threshold. That is the only device model this part needs; the rest is bookkeeping.

Leakage energy

1. Which device is off, and what is across it? In a settled inverter one device is on and the other off. Output high: the NFET is off, with the output ($V_{DD}$VDD​) on its drain and ground on its source. Output low: the PFET is off, with $V_{DD}$ on its source and the output (0 V) on its drain. Either way, each inverter always has exactly one leaking device, with the full $V_{DD}$ across it.
2. How far below threshold? $V_{GS} = 0$ and $V_T = 200$ mV (the PFET’s −200 mV in magnitude), so the gate is 200 mV below threshold. At 90 mV per decade that is $200/90 = 2.22$ decades (Chapter 4, Section 11).
3. How much current? $I_{off} = 10\,\mu\mathrm{A/\mu m}\,/\,10^{2.22} = 10/166.8 = 0.0599\,\mu\mathrm{A/\mu m} \approx 60\,\mathrm{nA/\mu m}$60nA/μm. (Two decades would divide by 100; a little more than two divides by 167.)
4. How wide is the leaking device? Both devices are $W$ wide here, so whichever one is off, each inverter leaks $60W$ nA all the time. (In MT23-1b’s 2W/W inverter the width depends on the output; that is the one new idea there.)
5. Energy is power × time. One inverter dissipates $V_{DD} \cdot I_{off} \cdot W$W, and all $N$ do so for the whole cycle: $E_{leak} = N \cdot W \cdot T_{cycle} \times 59.9\,\mathrm{nA/\mu m} \times 1.2\,\mathrm{V} = 71.9\,NWT_{cycle}$ nW.
6. Units. nW × s = nJ, so that is $71.9\,NWT_{cycle}$ nJ with $T_{cycle}$ in seconds. With $T_{cycle}$ in ps, nW × ps = $10^{-21}$ J = $10^{-6}$ fJ, so it is $7.19\times10^{-5}\,NWT_{cycle}$ fJ. Part (c) needs this form.

Check. One 1 µm inverter leaking through a 100 ps cycle: $71.9\,\mathrm{nW} \times 100\,\mathrm{ps} = 7.2\,\mathrm{aJ}$7.2aJ, that is $7.2\times10^{-3}$ fJ, against the 8.64 fJ it spends switching in (a): about a thousandth. Part (c) makes this comparison exact.

Answer: $E_{leak} \approx 72\,N\,W\,T_{cycle}$ nJ ($W$W in µm, $T_{cycle}$ in s).

Remember. Leakage is always three questions: which device is off and how wide, how many decades below threshold, and for how long. Temperature changes only the slope $S$ (MT17-1c, Section 9).

The answer key agrees

It rounds the current to 60 nA/µm.

MT24-2c: the leakage share when the cycle equals the chain delay

MT24-2c, p5 (10 points). Assuming $T_{cycle}$ equals the delay of the N-stage chain, what is the ratio of the leakage energy in (b) to the total energy consumed in a cycle, as a function of N and W?

Hint

Leakage grows with the length of the cycle; switching energy doesn’t. Replace $T_{cycle}$ by the chain’s delay, and both energies become functions of $N$ and $W$ alone.

What it asks. The fraction of all the energy used in one cycle that is leakage, when the clock runs as fast as the chain allows: $T_{cycle}$ equals the chain’s delay. “Total” means switching (a) plus leakage (b). Because $T_{cycle}$ is now tied to the circuit, it has to be replaced by the delay before you divide.

The idea. The chain’s delay comes from the course’s delay model: the conducting transistor acts as a resistor $R/W$ that charges or discharges the node, so one stage takes $(R/W)\,C_{node}$ (Chapter 7, Section 1), and $N$ stages in a row take $N$ times as long. Put that into (b), then divide by (a).

Leakage share

1. One stage. The driving device is $W$ wide with $R = 1\,\mathrm{k\Omega\cdot\mu m}$1kΩ⋅μm, and it drives $C_{node}$Cnode​: $\dfrac{1\,\mathrm{k\Omega\cdot\mu m}}{W}(2W + 4)\,\mathrm{fF} = \dfrac{2(W + 2)}{W}\,\mathrm{ps}$W2(W+2)​ps. With equal strengths this holds on both edges (Chapter 7, Section 7).
2. The whole chain. $T_{cycle} = N \cdot \dfrac{2(W + 2)}{W}\,\mathrm{ps}$W2(W+2)​ps.
3. Leakage over that cycle. From (b), with $T_{cycle}$ in ps: $E_{leak} = 7.19\times10^{-5}\,NW \cdot \dfrac{2N(W + 2)}{W} = 1.44\times10^{-4}\,N^2(W + 2)\,\mathrm{fJ}$2)fJ. The $W$ in front cancels the $1/W$ of the delay: wider devices leak more, but they shorten the cycle in the same proportion.
4. Switching energy, from (a), written the same way: $E_{cycle} = 1.44N(2W + 4) = 2.88N(W + 2)\,\mathrm{fJ}$2)fJ.
5. Divide. Leakage ÷ switching $= \dfrac{1.44\times10^{-4}N^2(W + 2)}{2.88N(W + 2)} = 5.0\times10^{-5}N$10−5N. The total is switching plus leakage, so leakage ÷ total $= \dfrac{5.0\times10^{-5}N}{1 + 5.0\times10^{-5}N}$1+5.0×10−5N5.0×10−5N​.
6. Read the result. It doesn’t depend on $W$W, and it grows with $N$N: a longer chain needs a longer cycle, so each inverter leaks for longer while it still switches only once per cycle.

Check. A second route gives the coefficient directly added. Leakage is $N W I_{off} V_{DD}$ for a time $N(R/W)C_{node}$N(R/W)Cnode​, and switching is $NC_{node}V_{DD}^2$NCnode​VDD2​, so their ratio is $I_{off}RN/V_{DD}$Ioff​RN/VDD​: the capacitance and $W$ cancel, and a current times a resistance over a voltage has no units, as a ratio must. $59.9\,\mathrm{nA} \times 1\,\mathrm{k\Omega} = 59.9\,\mu\mathrm{V}$59.9μV, and $59.9\,\mu\mathrm{V} \times N/1.2\,\mathrm{V} = 5.0\times10^{-5}N$10−5N. ✓ For scale: $N = 10$ gives a share of $5.0\times10^{-4}$10−4, $N = 100$ gives 0.50%, and leakage would equal the switching energy only near $N = 20\,000$20000.

Answer: $\dfrac{E_{leak}}{E_{leak} + E_{cycle}} = \dfrac{5.0\times10^{-5}N}{1 + 5.0\times10^{-5}N} = \dfrac{10^{-4}N}{2 + 10^{-4}N}$2+10−4N10−4N​.

Remember. When $T_{cycle}$ is tied to a delay, substitute the delay before you divide. The leakage share is then $I_{off}RN/V_{DD}$ in disguise: no $W$W, and proportional to $N$N.

The answer key agrees

It writes $\dfrac{10^{-4}N}{2 + 10^{-4}N}$2+10−4N10−4N​, the same expression. With the 0.69 factor in the delay, which the key also accepted, the coefficient becomes $3.4\times10^{-5}$10−5.

MT24-2d: the width that minimizes energy × delay

MT24-2d, p6 (10 points). If you can change the sizing of the inverters, what W minimizes the product of the energy in (a) and the delay of the N-stage chain?

Hint

Write energy × delay as a function of $W$W. The energy grows with $W$ and the delay shrinks; find where the two pulls balance.

What it asks. The width that makes (the energy per cycle of (a)) × (the chain’s delay) smallest. Why a product: energy alone is smallest for the smallest $W$W, and delay alone for the largest $W$ (part (e)). The product charges for both, so it has a best width in between.

The idea. Both factors contain $W + 2$2. The energy grows with $W$ (bigger gates to charge); the delay falls with $W$ (stronger devices, so the fixed 4 fF matters less). Their product is smallest where the two effects balance. Find that point by setting the derivative to zero added, or faster: write the product as a sum $aW + b/W$b/W, which is smallest where its two terms are equal.

Energy × delay

1. Multiply. $E \cdot D = 1.44N(2W + 4) \times \dfrac{2N(W + 2)}{W} = 5.76N^2\,\dfrac{(W + 2)^2}{W}\,\mathrm{fJ\cdot ps}$5.76N2W(W+2)2​fJ⋅ps.
2. Keep only what depends on W. $5.76N^2$ is a constant factor, so minimize $\dfrac{(W + 2)^2}{W} = W + 4 + \dfrac{4}{W}$W4​.
3. Balance the two terms added. The 4 is constant. As $W$ grows, the term $W$ grows and $4/W$ shrinks, and their sum is smallest where they are equal: $W = 4/W$4/W, so $W = 2\,\mu\mathrm{m}$2μm. (If $W$ were larger than $4/W$4/W, a smaller $W$ would lower the sum, and the other way round.) The derivative agrees: $\dfrac{(W + 2)(W - 2)}{W^2} = 0$0.
4. What it means. At $W = 2$ each inverter’s own input, $2W\,C_g = 4\,\mathrm{fF}$4fF, equals the side load. Narrower, and the side load dominates every node, so the delay climbs; wider, and most of the energy goes into driving the inverters’ own gates.
5. The numbers there. Each stage takes $2 \times 4/2 = 4\,\mathrm{ps} = 2\tau_{inv}$ and the chain $4N$ ps; the energy is $11.52N$ fJ and $E \cdot D = 46.1N^2\,\mathrm{fJ\cdot ps}$46.1N2fJ⋅ps.

Check. Try the neighbours: $(W + 2)^2/W$ is 9 at $W = 1$1, 8 at $W = 2$ and 9 at $W = 4$4. The minimum is at 2, and it is shallow: a width off by a factor of 2 costs only 12.5%.

Answer: $W = 2\,\mu\mathrm{m}$2μm, where the gates’ own load equals the 4 fF side load.

Remember. Energy × delay is least where the gates’ own load equals the fixed load. MT23-1d and MT17-4d ask the same thing with other numbers (Section 2, Section 4).

The answer key agrees

MT24-2e: the width that minimizes delay

MT24-2e, p6 (10 points). If the goal is simply to minimize the delay of this chain, what W is required? Think carefully about your answer.

Hint

Split one stage’s delay into a part that comes from driving the next inverter and a part that comes from the side load. What does each do as $W$ grows?

What it asks. The same chain, but now only the delay counts. “Think carefully” is the exam’s warning that the usual move, setting a derivative to zero, finds nothing here.

The idea. Split one stage’s delay into its two causes: $\dfrac{R}{W}(2W\,C_g + 4\,\mathrm{fF}) = 2RC_g + \dfrac{4\,\mathrm{fF} \cdot R}{W}$W4fF⋅R​. The first part is the stage driving the next inverter. A wider inverter is stronger by $W$W, but its load is larger by $W$ too, so this part is the fixed FO1 delay, $\tau_{inv} = 2$ ps. The second part is the side load, driven by an ever stronger device: it shrinks as $1/W$ and never turns around.

Delay alone

1. The chain delay. $N(2 + 4/W) = 2N(1 + 2/W)$ ps. It falls every time $W$ grows: there is no finite minimum.
2. The floor. As $W \to \infty$ the side-load part vanishes and each stage becomes a plain FO1: the chain approaches $N\tau_{inv} = 2N$ ps but never reaches it.
3. Diminishing returns. $W = 2$ gives $4N$ ps, $W = 20$ gives $2.2N$ ps and $W = 200$ gives $2.02N$ ps, while the energy per cycle grows in proportion to $2W + 4$4.
4. So the answer is “as wide as possible”, and the careful part is to say why: the side load is fixed, so wider inverters only shrink its share, and the chain can never beat $N\tau_{inv}$Nτinv​.

Check. The other end: as $W \to 0$ the delay grows without bound, because ever weaker devices drive a fixed 4 fF. From there the delay only falls toward its floor, so there is nothing in between to minimize.

Answer: $W \to \infty$ (much larger than 2 µm); the delay approaches $N\tau_{inv} = 2N$ ps but never reaches it. added Outside this question’s model the first inverter’s input, $2W\,C_g$2WCg​, also grows, so whatever drives the chain slows down; the question leaves that driver out.

Remember. With a fixed side load and nothing else fixed, minimizing delay has no finite answer. A best width needs a cost on width: the energy, as in (d), or a fixed input capacitance, as in the path-sizing questions (M4).

The answer key agrees

2. MT23-1: the same chain with 2W/W inverters

MT23-1, p2 (source figure).

MT23-1, p2 (Fall 2023, 34 points). A chain of $N$ 2W/W inverters, each loaded by an additional 4 fF of side-branch loading. $C_g = 1\,\mathrm{fF/\mu m}$1fF/μm, $R_{nfet} = 1\,\mathrm{k\Omega\cdot\mu m}$1kΩ⋅μm, $R_{pfet} = 2\,\mathrm{k\Omega\cdot\mu m}$2kΩ⋅μm. Ignore drain capacitances. A 50% duty-cycle square wave of period $T_{cycle}$Tcycle​; $V_{DD} = 1.2\,\mathrm{V}$1.2V.

Before the parts: what changes from MT24-2. This is the chain of Section 1 a year earlier, and every move is the same. Only the device strengths differ, and three things follow from them.

• The inverter is 2W/W. Here $R_{pfet} = 2R_{nfet}$2Rnfet​: a PFET passes half the current of an NFET of the same width. To pull up as hard as the NFET pulls down, the PFET is made twice as wide, $2W$2W. Its resistance is then $R_{pfet}/2W = R_{nfet}/W$Rnfet​/W, the same as the NFET’s, so a stage still has one delay for both edges.
• The node is larger. An inverter’s input is wired to both gates, the NFET’s ($W$W) and the PFET’s ($2W$2W), so it presents $3W\,C_g$3WCg​. With the 4 fF side load, and drains ignored as the question says,

$$C_{node} = (3W + 4)\,\mathrm{fF}.$$

• The unit of delay is larger. The fan-out-of-one delay is $\tau_{inv} = (R_{nfet}/W)(3W\,C_g) = 3R_{nfet}C_g = 3\,\mathrm{ps}$ (Chapter 7, Section 7).

The one new idea is in (b): the two devices now have different widths, so the width of the device that leaks depends on whether the output is high or low.

MT23-1a: supply energy per cycle

MT23-1a, p2 (10 points). What is the energy drawn from the supply for this chain during $T_{cycle}$Tcycle​, as a function of N and W? Ignore crowbar currents.

Hint

How many nodes rise during one period, and how much capacitance does each one carry now that the PFET is $2W$2W?

What it asks. The energy the supply delivers to the whole chain in one full period of the input. “During $T_{cycle}$Tcycle​” means one rising and one falling input edge, so every node rises once, exactly as in MT24-2a. Only the node’s capacitance has changed.

The idea. Same principle as MT24-2a: the supply delivers energy only when a node is charged. Raising a node of capacitance $C$ to $V_{DD}$ draws the charge $CV_{DD}$ from the supply at the voltage $V_{DD}$VDD​, so it costs $CV_{DD}^2$CVDD2​; a falling node draws nothing (Chapter 6, Section 6). The new part is $C_{node} = 3W + 4$ fF, because the next inverter’s input now has $3W$ of gate.

Energy per cycle

1. Count the rising nodes. An output rises when its input falls, so the odd nodes rise on one input edge and the even nodes on the other. Over one period each of the $N$ nodes rises once.
2. Price one rise. $C_{node}V_{DD}^2 = (3W + 4)\,\mathrm{fF} \times (1.2\,\mathrm{V})^2 = 1.44(3W + 4)\,\mathrm{fJ}$4)fJ, since fF × V² = fJ.
3. Add them up. $E_{cycle} = N(3W + 4)\,\mathrm{fF} \times 1.44\,\mathrm{V^2} = N(4.32W + 5.76)\,\mathrm{fJ}$5.76)fJ, with $W$ in µm.

Check. Against MT24-2a’s $N(2.88W + 5.76)$5.76): the side load’s 5.76 fJ per inverter is the same, and only the $W$ term grew, by $4.32/2.88 = 1.5$1.5. That is $3W/2W$3W/2W, the extra gate of the twice-as-wide PFET. ✓

Answer: $E_{cycle} = N(4.32W + 5.76)\,\mathrm{fJ}$5.76)fJ.

Remember. The energy per cycle is always $N\,C_{node}V_{DD}^2$NCnode​VDD2​. The inverter’s sizing enters only through $C_{node}$Cnode​, so count both gates of the next input: $2W$ for W/W, $3W$ for 2W/W.

The answer key agrees

MT23-1b: leakage energy per cycle

MT23-1b, p3 (8 points). What is the total subthreshold leakage energy of these N inverters at 300 K during a cycle? $10\,\mu\mathrm{A/\mu m}$ at $|V_T| = 200\,\mathrm{mV}$ for both devices; 90 mV/decade.

Hint

When the output is high, which device is off, and how wide is it? And when the output is low?

What it asks. The energy wasted in one cycle by current through the transistors that are off, with the same device numbers as MT24-2b. The difference is that this inverter’s two devices have different widths, so how wide the leaking device is depends on the output’s state.

The idea. Leakage energy is $V_{DD} \times$ (the off current per µm) $\times$ (the leaking width) $\times$ (the time). The current per µm comes from the subthreshold slope, as in MT24-2b: below threshold the current falls one decade for every $S$ millivolts that the gate is below $V_T$VT​, $I = I(V_T)\cdot10^{-(V_T - V_{GS})/S}$10−(VT​−VGS​)/S, and an off device has $V_{GS} = 0$ (Chapter 4, Section 11). What is new is the width. With the output high, the NFET ($W$W) is off; with the output low, the PFET ($2W$2W) is. The input is a 50% duty-cycle square wave, so every node spends half of each cycle high and half low, and the leaking width averages $1.5W$1.5W.

Leakage energy

1. The current per µm. Both devices have $|V_T| = 200$ mV and 90 mV/decade, so an off gate is $200/90 = 2.22$ decades below threshold, as in MT24-2b: $I_{off} = 10\,\mu\mathrm{A/\mu m}/10^{200/90} = 59.9\,\mathrm{nA/\mu m}$59.9nA/μm.
2. Which device leaks, and when. Because the off device has a different width in each half of the cycle, take the two halves separately. Output high (half the time): the NFET, width $W$W, is off, with $V_{DD}$ across it. Output low (the other half): the PFET, width $2W$2W, is off, with $V_{DD}$ across it.
3. Average the width over the cycle. Each state lasts half the cycle, so the average off width is $(W + 2W)/2 = 1.5W$1.5W.
4. Energy is power × time. All $N$ inverters leak for the whole cycle: $E_{leak} = N \cdot 1.5W \cdot I_{off} \cdot V_{DD} \cdot T_{cycle} = N W T_{cycle} \times 1.5 \times 59.9 \times 1.2\,\mathrm{nW} = 108\,NWT_{cycle}$ nW.
5. Units. nW × s = nJ, so that is $108\,NWT_{cycle}$ nJ with $T_{cycle}$ in seconds, or $1.08\times10^{-4}\,NWT_{cycle}$ fJ with $T_{cycle}$ in ps (nW × ps = $10^{-6}$ fJ). Part (c) needs the second form.

Check. The current per µm is the same as in MT24-2b, because the devices are the same; only the width changed. So the result should be MT24-2b’s $71.9\,NWT_{cycle}$ times $1.5W/W$1.5W/W: $71.9 \times 1.5 = 108$108. ✓

Answer: $E_{leak} \approx 108\,N\,W\,T_{cycle}$ nJ ($W$W in µm, $T_{cycle}$ in s).

Remember. When the inverter isn’t W/W, ask which device is off in each output state, and average their widths over the time the output spends in each state.

The answer key differs

It gives 60 pA/µm and so $108\,WTN$ pJ: a factor 1000 too small. $10\,\mu\mathrm{A}/166.8$ is 60 nA, and the MT24 key, on the same problem, has nA. Its 1.5W counting is right.

MT23-1c: the leakage share

MT23-1c, p3 (8 points). Assuming $T_{cycle}$ equals the delay of the N-stage chain, what is the ratio of the leakage energy in (b) to the total energy consumed in a cycle, as a function of N and W?

Hint

Replace $T_{cycle}$ by the chain’s delay before you divide. With a $2W$ PFET and $R_{pfet} = 2R_{nfet}$2Rnfet​, is a rising stage slower than a falling one?

What it asks. The fraction of the energy used in one cycle that is leakage, when the cycle is as short as the chain allows. “Total” is switching (a) plus leakage (b). “In a cycle” decides which switching energy to use: (a)‘s, with every node rising once.

The idea. The method is MT24-2c’s: one stage takes $(R/W)\,C_{node}$ in the course’s delay model, where the conducting transistor acts as a resistor $R/W$ (Chapter 7, Section 1); the chain takes $N$ stages; put that delay in for $T_{cycle}$ in (b), then divide by (a). Two things differ. The stage delay uses $C_{node} = 3W + 4$4. And the leakage share comes out 1.5 times MT24’s, because the leaking width averages $1.5W$ while the driving width is still $W$W.

Leakage share

1. One stage. Falling, the $W$ NFET drives the node: $\dfrac{1\,\mathrm{k\Omega\cdot\mu m}}{W}(3W + 4)\,\mathrm{fF} = 3 + \dfrac{4}{W}$ ps. Rising, the $2W$ PFET has $2/2W = 1/W$ kΩ, the same resistance, so the same delay: the 2W/W inverter is balanced.
2. The whole chain. $T_{cycle} = N(3 + 4/W)$ ps $= N(3W + 4)/W$ ps.
3. Leakage over that cycle. From (b), with $T_{cycle}$ in ps: $E_{leak} = 1.08\times10^{-4}\,NW \cdot \dfrac{N(3W + 4)}{W} = 1.08\times10^{-4}\,N^2(3W + 4)\,\mathrm{fJ}$4)fJ. The $W$ cancels: wider devices leak more, but they shorten the cycle in the same proportion.
4. Switching energy, from (a), written the same way: $E_{cycle} = 1.44N(3W + 4)\,\mathrm{fJ}$4)fJ.
5. Divide. Leakage ÷ switching $= \dfrac{1.08\times10^{-4}N^2(3W + 4)}{1.44N(3W + 4)} = 7.5\times10^{-5}N$10−5N. The total is switching plus leakage, so leakage ÷ total $= \dfrac{7.5\times10^{-5}N}{1 + 7.5\times10^{-5}N}$1+7.5×10−5N7.5×10−5N​.
6. Read the result. Again no $W$W, and it grows with $N$N. For $N = 10$10: $7.5\times10^{-4}$10−4.

Check. The second route of MT24-2c’s check added gives the coefficient directly. Leakage ÷ switching is (the leaking width ÷ the driving width) × $I_{off}R_{nfet}N/V_{DD}$Ioff​Rnfet​N/VDD​, and MT24-2c found $I_{off}R_{nfet}/V_{DD} = 5.0\times10^{-5}$10−5. Here the width ratio is $1.5W/W = 1.5$1.5, so $1.5 \times 5.0\times10^{-5} = 7.5\times10^{-5}$10−5. ✓

Answer: $\dfrac{7.5\times10^{-5}N}{1 + 7.5\times10^{-5}N}$1+7.5×10−5N7.5×10−5N​, independent of $W$W.

Remember. Substitute the delay for $T_{cycle}$ before you divide. The share is then (leaking width ÷ driving width) × $I_{off}RN/V_{DD}$Ioff​RN/VDD​: no $W$W, and proportional to $N$N.

The answer key differs

It differs in three ways: it carries the pA slip from (b); it leaves $T$ in the answer instead of substituting the chain delay; and it takes the switching energy as $\tfrac{N}{2}(4.32W + 5.76)$ fJ, reasoning that in one chain delay “all inverters have switched state once”. That is the energy of one input transition. The question asks for the energy in a cycle, which part (a) found to be twice as much, and the MT24 key uses the full cycle. If your exam asks this, use your part (a) and say so.

MT23-1d: the width that minimizes energy × delay

MT23-1d, p4 (8 points). If you can change the sizing, what W minimizes the product of the energy in (a) and the delay of the chain?

Hint

Write energy × delay as a function of $W$W. Which of its terms grows as $W$ grows, and which shrinks?

What it asks. The width that makes (the energy per cycle of (a)) × (the chain’s delay) smallest: MT24-2d with the 2W/W numbers.

The idea. Same balance as MT24-2d. Both factors contain $3W + 4$4: the energy grows with $W$ (more gate to charge), and the delay $(3W + 4)/W$ falls with $W$ (stronger devices, so the fixed 4 fF matters less). The product is smallest where the two pulls balance, and that happens where the inverters’ own gate load equals the side load. The only change is that the gate load is now $3W\,C_g$3WCg​, so the best $W$ is smaller than MT24’s 2 µm.

Energy × delay

1. Multiply (a) by the chain delay of (c): $E \cdot D = 1.44N(3W + 4) \times N\dfrac{3W + 4}{W} = 1.44N^2\,\dfrac{(3W + 4)^2}{W}\,\mathrm{fJ\cdot ps}$1.44N2W(3W+4)2​fJ⋅ps.
2. Keep only what depends on W. $1.44N^2$ is a constant factor, so minimize $\dfrac{(3W + 4)^2}{W} = 9W + 24 + \dfrac{16}{W}$W16​.
3. Balance the two terms added. The 24 is constant; $9W$ grows and $16/W$ shrinks, and their sum is smallest where they are equal: $9W = 16/W$16/W, so $W = 4/3 = 1.33\,\mu\mathrm{m}$1.33μm. The derivative agrees: $\dfrac{6(3W + 4)W - (3W + 4)^2}{W^2} = \dfrac{(3W + 4)(3W - 4)}{W^2} = 0$0.
4. What it means. At $W = 4/3$ the gate load $3W\,C_g = 4\,\mathrm{fF}$ equals the side load, as in MT24-2d.
5. The numbers there. Each stage is $3 + 3 = 6\,\mathrm{ps} = 2\tau_{inv}$ and the energy is $1.44 \times 8 = 11.52N$ fJ.

Check. Try the neighbours: $(3W + 4)^2/W$ is 49 at $W = 1$1, 48 at $W = 4/3$ and 50 at $W = 2$2, so the minimum is at 4/3, and shallow. The energy at the optimum, $11.52N$ fJ, is the same as MT24-2d’s, and so is the stage delay in units of $\tau_{inv}$τinv​: in both exams each node is then twice the side load, 8 fF.

Answer: $W = 4/3\,\mu\mathrm{m} \approx 1.33\,\mu\mathrm{m}$1.33μm.

Remember. Energy × delay is least where the gates’ own load equals the fixed load, whatever the inverter’s ratio. Only the gate load per µm changes: $2W\,C_g$ for W/W, $3W\,C_g$ for 2W/W.

The answer key agrees

Try it

Switch between the two exams’ technologies, move $W$W, the side load and $N$N, and watch the three curves. The minimum of energy × delay always sits where the inverters’ own gate load equals the side load, and the leakage share never depends on $W$W.

W/W, equal strengths (MT24-2)2W/W, R_p = 2R_n (MT23-1)

NFET width W

1.0 µm

side load on every node

4.0 fF

inverters N

10

node capacitance

6.00 fF

stage delay (R/W)·C

6.00 ps = 3.00 τ_inv

chain delay = T_cycle

60.0 ps

switching energy per cycle

86.40 fJ

leakage per cycle (59.9 nA/µm)

4.32×10⁻² fJ

leakage share of the total

4.99×10⁻⁴

W for least energy × delay

2.00 µm

Each curve is divided by its value at W*, where the inverters' own gate load equals the side load. Delay falls toward N·τ_inv as W grows, energy grows in a straight line, and their product has its minimum at W*. The leakage share uses T_cycle equal to the chain delay and a 50% duty cycle; W cancels from it, and it grows with N. Delay is (R/W)·C with no 0.69 factor; drain capacitance is ignored.

What to notice.

• The delay curve flattens toward 1/2 of its value at $W^*$W∗: the $N\tau_{inv}$ floor of MT24-2e.
• Set the side load to 0: the delay no longer depends on $W$ (MT17-4a), and energy × delay is smallest at the smallest $W$W.
• Raise $N$N: the leakage share grows in proportion; it is the only knob that moves it.

3. MT21-4: four inverters and the best PFET width

MT21-4, p6 (source figure).

MT21-4, p6 (Fall 2021, 35 points). A chain of four identical inverters sized $W_p/W_n = n\,\mu\mathrm{m}/1\,\mu\mathrm{m}$nμm/1μm. They would give equal rise and fall delays if sized 2 µm/1 µm. $k_{gate} = 2\,\mathrm{fF/\mu m}$2fF/μm; $\tau_{inv} = 25\,\mathrm{ps}$25ps; $V_{DD} = 2.5\,\mathrm{V}$2.5V. The output B drives $2(n + 1)$ fF.

Before the parts: one node. This chain has no side load; what is new is that the PFET’s width $n$ is the unknown. Two facts set up every part.

• The strengths. “Equal rise and fall delays if sized 2 µm/1 µm” says that a 2 µm PFET drives as hard as a 1 µm NFET, so $R_{pfet} = 2R_{nfet}$2Rnfet​. The balanced inverter is the 2/1, and $\tau_{inv} = 25$ ps is its fan-out-of-one delay.
• Every node is the same. An inner node carries the next inverter’s input, which is wired to both its gates: $(n + 1)$ µm of gate, or $2(n + 1)$ fF at 2 fF/µm. The last node, B, has no fifth inverter, but the question loads it with exactly $2(n + 1)$ fF, what a fifth inverter would present. So all four inverters drive the same load, a copy of themselves, whatever $n$ is. Drains are not counted.

MT21-4a: the delay for n = 2

MT21-4a, p6 (10 points). For $n = 2$2, what is the delay from A rising to B rising?

Hint

With $n = 2$2, what does each inverter drive, compared with itself?

What it asks. The time for a rising edge at A to come out as a rising edge at B, through four inverters, at $n = 2$2. Four inversions take a rise back to a rise; on the way two stages fall and two rise.

The idea. $\tau_{inv}$ is the fan-out-of-one delay: the balanced inverter driving one copy of itself. In the course’s delay model a stage takes $(R/W)\,C_{node}$(R/W)Cnode​, and for an FO1 the widths cancel: $(R_{nfet}/W)(3W\,k_{gate}) = 3R_{nfet}k_{gate} = \tau_{inv}$τinv​. A wider inverter is stronger by $W$W, but its copy is larger by $W$ too (Chapter 7, Section 7). At $n = 2$ each inverter is the balanced 2/1 and drives its own copy, so every stage is exactly one FO1, on either edge.

1. Each stage is an FO1. With $n = 2$ each inverter is the balanced 2/1 and drives one copy of itself (the intro’s equal nodes). Because it is balanced, the falling stages (through the NFET) and the rising ones (through the PFET) each take $\tau_{inv}$τinv​.
2. Count the stages. Four of them: $4\tau_{inv} = 4 \times 25 = 100\,\mathrm{ps}$100ps.

Check. Price the two kinds of stage separately. A falling stage is the 1 µm NFET driving 3 µm of gate: $(R_{nfet}/1)(3k_{gate}) = 3R_{nfet}k_{gate} = \tau_{inv}$τinv​. A rising stage is the 2 µm PFET, $R_{pfet}/2 = R_{nfet}/1$Rnfet​/1, driving the same 3 µm: also $\tau_{inv}$τinv​. So two falling and two rising stages give $2\tau_{inv} + 2\tau_{inv} = 4\tau_{inv} = 100$ ps. ✓ $R_{nfet}$ itself never appears, which is why part (c) can use this result to stand in for it.

Answer: 100 ps.

Remember. A balanced inverter driving its own copy takes $\tau_{inv}$ whatever its size; a chain of them takes $N\tau_{inv}$Nτinv​.

The answer key agrees

MT21-4b: energy of one transition

MT21-4b, p7 (10 points). For $n = 2$2, what is the energy dissipated by a single transition through this chain? Ignore leakage, crowbar currents and the energy from the source at A; consider only dynamic charging energy.

Hint

When A rises once, which of the four nodes rise, and what does each one draw from the supply?

What it asks. The energy of one input edge, at $n = 2$2. “A single transition” decides the count: A changes once, so only half of the nodes rise (compare MT24-2a, where “during $T_{cycle}$Tcycle​” made every node rise once). “Dissipated” asks for the heat, not the energy drawn; the two come to the same total here.

The idea. A rising node draws $CV_{DD}^2$ from the supply: half is stored on the node and half burns in the PFET. A falling node draws nothing, and burns its stored $\tfrac12CV_{DD}^2$ in the NFET (Chapter 6, Section 6). In one transition two nodes rise and two fall, so you can count either way.

Energy per transition

1. One node. Each carries $(2 + 1)\,\mu\mathrm{m} \times 2\,\mathrm{fF/\mu m} = 6\,\mathrm{fF}$6fF, and $V_{DD}^2 = 6.25\,\mathrm{V^2}$6.25V2.
2. Which nodes rise. A rises, so node 1 falls, node 2 rises, node 3 falls and node 4 (B) rises: two of the four.
3. Count the energy drawn. The two rising nodes each draw $CV_{DD}^2 = 37.5\,\mathrm{fJ}$ from the supply: 75 fJ in all.
4. Count what is dissipated instead (Chapter 6, Section 6), since that is the question’s word. Each rising node burns half of its 37.5 fJ in its PFET (2 × 18.75 fJ), and each falling node burns its stored 18.75 fJ in its NFET (2 × 18.75 fJ). Total 75 fJ, the same, because as many nodes fall as rise.

Check. The other edge: A falling makes nodes 1 and 3 rise, again two nodes, again 75 fJ. And the key’s form: half of all the capacitance, $\tfrac12 \times 24\,\mathrm{fF} \times 6.25\,\mathrm{V^2} = 75$ fJ. ✓

Answer: 75 fJ (for either edge).

Remember. Per transition, half the nodes rise: the energy is $\tfrac12 C_{total}V_{DD}^2$21​Ctotal​VDD2​, whether you count what is drawn or what is dissipated.

The answer key agrees

It writes it as $\tfrac12 C_{total}V_{DD}^2$ with $C_{total} = 24$ fF.

MT21-4c: the PFET width that minimizes the delay

MT21-4c, p7 (15 points). Find the $n$ that minimizes the delay from A rising to B rising. Why is it less than two? What $n$ would minimize the delay if the nFETs and pFETs had equal strength?

Hint

The PFET’s width loads every node, but it speeds up only the rising stages. Write the four stage delays with $n$ unknown and add them.

What it asks. The PFET width $n$ (in µm, with the NFET at 1 µm) that makes the A-rising-to-B-rising delay smallest; why that $n$ is below 2; and the best $n$ if the two devices had equal strength. “From A rising to B rising” fixes which stages fall (1 and 3) and which rise (2 and 4).

The idea. The tempting answer is $n = 2$2, the balanced inverter, because it makes the rising and falling delays equal. But equal delays are not the smallest sum. Each stage takes $(R/W)\,C_{node}$ (Chapter 7, Section 1), and $n$ appears in both factors: in $C_{node} = (n + 1)k_{gate}$ on every stage, and in the PFET’s resistance $R_{pfet}/n$ on the rising stages only. Write the total as a function of $n$n, and find where the part that grows with $n$ balances the part that shrinks. $R_{nfet}$ isn’t given, so (a)‘s 100 ps has to stand in for it.

Best n

1. The falling stages. Every node carries $(n + 1)$ µm of gate. Stages 1 and 3 fall through the 1 µm NFET: $R_{nfet}(n + 1)k_{gate}$ each.
2. The rising stages. Stages 2 and 4 rise through the $n$ µm PFET, whose resistance is $R_{pfet}/n = 2R_{nfet}/n$2Rnfet​/n: $\dfrac{2R_{nfet}}{n}(n + 1)k_{gate}$ each (Chapter 7, the check on n µm/1 µm).
3. Add the four. $2(n + 1)k_{gate}R_{nfet}\left(1 + \dfrac{2}{n}\right) = 2k_{gate}R_{nfet}\left(n + 3 + \dfrac{2}{n}\right)$2kgate​Rnfet​(n+3+n2​).
4. Calibrate with n = 2. The question gives $\tau_{inv}$ but not $R_{nfet}$Rnfet​, and part (a) says the chain takes $4\tau_{inv}$ at $n = 2$2. Setting $n = 2$ in step 3: $2k_{gate}R_{nfet} \times 6 = 4\tau_{inv}$4τinv​, so $k_{gate}R_{nfet} = \tau_{inv}/3$ (the 2/1 inverter’s $\tau_{inv} = 3R_{nfet}k_{gate}$3Rnfet​kgate​). The delay is $\tfrac23\left(n + 3 + \tfrac{2}{n}\right)\tau_{inv}$32​(n+3+n2​)τinv​.
5. Balance the two terms added, the move first explained in MT24-2d. The 3 is constant; $n$ (the PFET’s load on every node) grows and $2/n$ (its resistance on the rising stages) shrinks. Their sum is smallest where they are equal: $n = 2/n$2/n, so $n = \sqrt{2} = 1.41$1.41. The derivative agrees: $1 - \dfrac{2}{n^2} = 0$0.
6. The delay there. $\tfrac23(3 + 2\sqrt{2})\,\tau_{inv} = 3.89\tau_{inv} = 97.1\,\mathrm{ps}$97.1ps, about 3% faster than at $n = 2$2.
7. Equal strengths. Now the PFET’s resistance is $R_{nfet}/n$Rnfet​/n, so the rising term becomes $\dfrac{R_{nfet}}{n}(n + 1)k_{gate}$1)kgate​, the total $2k_{gate}R_{nfet}\left(n + 2 + \dfrac{1}{n}\right)$2kgate​Rnfet​(n+2+n1​), and $n = 1/n$ (or $1 - 1/n^2 = 0$0) gives $n = 1$1.

Check. The sum $n + 2/n$ takes the same value at $n$ and at $2/n$2/n, so $n = 1$ gives the same 100 ps as $n = 2$2, and the minimum must sit between them at $\sqrt{1 \times 2} = \sqrt{2}$2​. ✓ The curve is flat there: the best $n$ saves only 3%.

Why less than two. The PFET’s width is load on every node, so it slows the falling stages too, but it speeds up only the rising ones. At $n = 2$ the two edges are equal; shrinking the PFET a little saves more on the falling stages (lighter load) than it costs on the rising ones. The optimum trades a little rising speed for less load. added In general the best ratio is $n = \sqrt{R_{pfet}/R_{nfet}}$Rpfet​/Rnfet​​: $\sqrt{2}$ here, 1 with equal strengths.

Answer: $n = \sqrt{2} \approx 1.41$ (97.1 ps instead of 100 ps); $n = 1$ with equal strengths.

Remember. Equal rise and fall is not the fastest chain. When the PFET’s width loads the same nodes it drives, the best ratio is $\sqrt{R_{pfet}/R_{nfet}}$Rpfet​/Rnfet​​. Recognize the question by “find the $n$ (or the PFET width) that minimizes the delay”.

The answer key agrees

It drops a factor $2R_n$ in its last derivative, which does not change the root.

4. MT17-4: a chain with wiring capacitance

MT17-4, p8 (source figure).

MT17-4, p8 (Fall 2017, 38 points). A chain of four identical inverters sized $2W/W$ with an additional wiring capacitance $C_x$ between inverters. They give equal rise and fall delays at $W_p/W_n = 2$2. $k_{gate} = 2\,\mathrm{fF/\mu m}$2fF/μm; $\tau_{inv} = 25\,\mathrm{ps}$25ps; $V_{DD} = 1.0\,\mathrm{V}$1.0V. The last output carries $C_x$ and $3Wk_{gate}$3Wkgate​.

Before the parts: one node. The same chain again, with two changes: the fixed load is a wire, $C_x$Cx​, given as a symbol instead of a number, and the energy in (c) is per transition. Every part uses the node, so find it once.

• The strengths. Equal rise and fall at $W_p/W_n = 2$ means $R_{pfet} = 2R_{nfet}$2Rnfet​, so the 2W/W inverter is balanced and $\tau_{inv} = 3R_{nfet}k_{gate} = 25$ ps is its fan-out-of-one delay (Chapter 7, Section 7).
• The node. Each output carries the next inverter’s input, both its gates, $W + 2W = 3W$ µm, so $3Wk_{gate}$3Wkgate​; plus the wire $C_x$Cx​. The last output has no fifth inverter, but the question loads it with $3Wk_{gate}$3Wkgate​, its stand-in. So every node carries $3Wk_{gate} + C_x$Cx​.

MT17-4a: no wire

MT17-4a, p8 (8 points). For $C_x = 0$0, what is the delay from A rising to B rising (or falling to falling)? Does it depend on W? Why?

Hint

With no wire, what does each inverter drive, compared with itself? What happens to its strength and to its load as $W$ grows?

What it asks. The delay through the four inverters with no wire, and whether the size $W$ matters. “Why?” is where the points are: the answer has to name what cancels.

The idea. With $C_x = 0$0, each inverter drives exactly one copy of itself, so each stage is a fan-out-of-one delay, $\tau_{inv}$τinv​. In the course’s delay model that is $(R_{nfet}/W)(3W\,k_{gate})$(Rnfet​/W)(3Wkgate​): the width appears once in the strength (underneath) and once in the load (on top), and cancels (Chapter 7, Section 7).

1. One stage. With no wire the node is $3Wk_{gate}$3Wkgate​, the next inverter’s input. Falling, the $W$ NFET drives it: $(R_{nfet}/W)(3Wk_{gate}) = 3R_{nfet}k_{gate} = \tau_{inv}$τinv​. Rising, the $2W$ PFET has $R_{pfet}/2W = R_{nfet}/W$Rnfet​/W, the same.
2. Four stages: $4\tau_{inv} = 100\,\mathrm{ps}$100ps.
3. Why W drops out. A wider inverter is stronger by $W$W, but its load, the next inverter, is larger by $W$ too, and the two cancel. Only a load that doesn’t grow with $W$W, such as the wire of (b), makes the size matter.

Check. This is MT21-4a again: four balanced inverters with $\tau_{inv} = 25$ ps, each driving its own copy, 100 ps. Neither question gives $R_{nfet}$Rnfet​, and neither needs it.

Answer: 100 ps, for any $W$W.

Remember. A chain that drives only copies of itself takes $N\tau_{inv}$Nτinv​, whatever its size. Size helps only against a fixed capacitance.

The answer key agrees

MT17-4b: with the wire

MT17-4b, p8 (10 points). For $C_x > 0$0, what is the delay as a function of W and $C_x$Cx​? What W minimizes it?

Hint

Split one stage’s delay into the part from driving the next inverter and the part from driving the wire. Which part depends on $W$W?

What it asks. The chain’s delay with the wire, as a formula in $W$ and $C_x$Cx​, and the $W$ that makes it smallest. It is MT24-2e with a wire in place of the side load, so expect the same “no finite answer”.

The idea. Split one stage: $\dfrac{R_{nfet}}{W}(3Wk_{gate} + C_x) = 3R_{nfet}k_{gate} + \dfrac{R_{nfet}C_x}{W}$WRnfet​Cx​​. The first part is (a)‘s $\tau_{inv}$τinv​, fixed. The second is a fixed wire driven by an ever stronger device: it shrinks as $1/W$ and never turns around. $R_{nfet}$ isn’t given, so write it through $\tau_{inv} = 3R_{nfet}k_{gate}$3Rnfet​kgate​.

1. One stage, with $R_{nfet} = \tau_{inv}/(3k_{gate})$τinv​/(3kgate​): $\dfrac{R_{nfet}}{W}(3Wk_{gate} + C_x) = \tau_{inv}\,\dfrac{3Wk_{gate} + C_x}{3Wk_{gate}}$τinv​3Wkgate​3Wkgate​+Cx​​, since $\tau_{inv} = 3R_{nfet}k_{gate}$3Rnfet​kgate​.
2. Four stages: $D = 4\tau_{inv}\left(1 + \dfrac{C_x}{3Wk_{gate}}\right) = 100\,\mathrm{ps}\left(1 + \dfrac{C_x}{6W}\right)$ with $C_x$ in fF and $W$ in µm.
3. Which W. Because only the wire term depends on $W$W, and it falls every time $W$ grows, the delay falls monotonically: it is smallest for $W \to \infty$∞, where it approaches 100 ps. For example $C_x = 6$ fF and $W = 1\,\mu\mathrm{m}$ give 200 ps: the wire equals the gates’ load and doubles the delay.

Check. $C_x = 0$ gives back (a)‘s 100 ps for every $W$W. ✓ And as $W \to 0$ the delay grows without bound, because ever weaker devices drive a fixed wire.

Answer: $D = 4\tau_{inv}(3Wk_{gate} + C_x)/(3Wk_{gate})$Cx​)/(3Wkgate​); minimized by $W \to \infty$∞.

Remember. With a fixed load and nothing else fixed, delay alone wants infinitely wide inverters, and the floor is $N\tau_{inv}$Nτinv​. A finite best width needs a cost on width, such as the energy in (d).

The answer key agrees

MT17-4c: energy of one transition

MT17-4c, p9 (10 points). What energy is dissipated by a single transition through this chain, as a function of W and $C_x$Cx​? Ignore leakage, crowbar current and the source at A; consider only dynamic charging energy.

Hint

One input edge: how many of the four nodes rise, and what does each one carry?

What it asks. The energy of one input edge, as a formula in $W$ and $C_x$Cx​, counting only the charging of the nodes. “A single transition” decides the count, as in MT21-4b: half of the nodes rise.

The idea. A rising node draws $CV_{DD}^2$ from the supply, half stored and half burnt in the PFET; a falling node draws nothing and burns its stored half in the NFET (Chapter 6, Section 6). So count the rising nodes and charge each one $C_{node}V_{DD}^2$Cnode​VDD2​, with this question’s node, $3Wk_{gate} + C_x$Cx​.

1. One node. $C = C_x + 3Wk_{gate}$3Wkgate​, from the intro: the next inverter’s input plus the wire.
2. Which nodes rise. One input edge makes two nodes rise and two fall: nodes 2 and 4 when A rises, 1 and 3 when it falls.
3. Price them. The rising pair draws $2CV_{DD}^2$ from the supply; counting dissipation instead gives the same $4 \times \tfrac12 CV_{DD}^2$21​CVDD2​, because as many nodes fall as rise.
4. Put in the numbers. With $V_{DD} = 1\,\mathrm{V}$ and $k_{gate} = 2\,\mathrm{fF/\mu m}$2fF/μm: $E = 2(C_x + 3Wk_{gate}) \times 1\,\mathrm{V^2} = 2(C_x + 6W)$ fJ.

Check. Units: fF × V² = fJ. ✓ And the trap: per cycle every node would rise once, $4(C_x + 6W)$ fJ, twice as much. The question says “a single transition”.

Answer: $E = 2(C_x + 3Wk_{gate})V_{DD}^2 = 2(C_x + 6W)$ fJ, with $C_x$ in fF and $W$ in µm.

Remember. “Per transition” is one input edge: half of the nodes rise, $\tfrac12 C_{total}V_{DD}^2$21​Ctotal​VDD2​.

The answer key agrees

It writes J, with the capacitances in farads.

MT17-4d: the width that minimizes energy × delay

MT17-4d, p9 (10 points). Find the W that minimizes the product of the energy in (c) and the delay in (b).

Hint

Multiply (c) by (b) and call the gates’ own load $x$x. As $x$ grows, which part of the product grows and which shrinks?

What it asks. The width that makes (c)‘s energy × (b)‘s delay smallest. The answer is a formula in $C_x$Cx​, because the wire is a symbol.

The idea. The same optimum as MT24-2d. The energy grows with the gate load $3Wk_{gate}$3Wkgate​; the delay falls with $W$ because the fixed wire matters less. Their product is smallest where the gates’ own load equals the fixed load. Two differences change nothing: the fixed load is a wire, and the energy is per transition. Per transition is half of per cycle, a constant factor: it scales the product but doesn’t move its minimum.

1. Multiply (c) by (b): $E \cdot D = 2(3Wk_{gate} + C_x)V_{DD}^2 \times 4\tau_{inv}\dfrac{3Wk_{gate} + C_x}{3Wk_{gate}} = 8\tau_{inv}V_{DD}^2\,\dfrac{(3Wk_{gate} + C_x)^2}{3Wk_{gate}}$8τinv​VDD2​3Wkgate​(3Wkgate​+Cx​)2​.
2. Name the gates’ load. Write $x = 3Wk_{gate}$3Wkgate​, the gates’ own load, and drop the constant $8\tau_{inv}V_{DD}^2$8τinv​VDD2​: minimize $\dfrac{(x + C_x)^2}{x} = x + 2C_x + \dfrac{C_x^2}{x}$xCx2​​.
3. Balance the two terms added. $x$ grows and $C_x^2/x$ shrinks; their sum is smallest where they are equal, $x = C_x^2/x$Cx2​/x, so $x = C_x$Cx​. The derivative agrees: $\dfrac{2(x + C_x)x - (x + C_x)^2}{x^2} = \dfrac{(x + C_x)(x - C_x)}{x^2} = 0$0.
4. Back to W. $x = C_x$Cx​: $3Wk_{gate} = C_x$Cx​, so $W = C_x/(3k_{gate}) = C_x/(6\,\mathrm{fF/\mu m})$Cx​/(6fF/μm).
5. The numbers there. Each node is $2C_x$2Cx​, so each stage takes $2\tau_{inv}$2τinv​, as in MT24-2d: the delay is $8\tau_{inv} = 200\,\mathrm{ps}$ and the energy $4C_xV_{DD}^2$4Cx​VDD2​.

Check. Put $x = C_x$ into (b): $D = 4\tau_{inv}(1 + C_x/C_x) = 8\tau_{inv}$8τinv​. ✓ And into (c): $2(C_x + C_x)V_{DD}^2 = 4C_xV_{DD}^2$4Cx​VDD2​. ✓

Answer: $C_x = 3Wk_{gate}$3Wkgate​, that is $W = C_x/(6\,\mathrm{fF/\mu m})$Cx​/(6fF/μm).

Remember. The third time the same result: make the gate load equal to the fixed load (MT24-2d, MT23-1d, MT17-4d). At that width every stage takes $2\tau_{inv}$2τinv​.

The answer key agrees

How to approach a noise-margin question

Noise-margin questions are explanation questions. They show an inverter’s voltage transfer curve (VTC: the output voltage against the input voltage) and ask how much DC noise a node can take, or which way the curve and the margins move when the inverter changes. They carry real points (MT24-1 was 40 of 200) but almost no arithmetic: the points are for the reasoning.

The one idea behind every part. A gate amplifies noise only where its VTC is steep. Mark the two points where the slope is −1 (Chapter 6, Section 4):

• between them the gain is larger than 1 in size: a disturbance at the input comes out larger at the output, and down a chain it grows until a logic value flips;
• outside them the gain is smaller than 1: a disturbance comes out smaller, and the chain cleans it up.

The upper point is $(V_{IL}, V_{OH})$ and the lower one $(V_{IH}, V_{OL})$(VIH​,VOL​). So an input is safely low up to $V_{IL}$ and safely high down to $V_{IH}$VIH​.

The moves.

1. Where does the node sit before its noise? That depends on whether the node before it is noisy too: at $V_{OL}$ or $V_{OH}$ if every node is noisy, at the rail if only this one is (MT24-1a and b).
2. Where does the next gate start to amplify? At $V_{IL}$ for a low node, at $V_{IH}$ for a high node.
3. The margin is the distance between the two. With noise everywhere, $NM_L = V_{IL} - V_{OL}$ and $NM_H = V_{OH} - V_{IH}$VIH​.
4. “How does the curve change?” Decide first whether the change moves the curve sideways (the PFET’s strength against the NFET’s) or changes its steepness (the gain). Then say which of the four points move and which way; the margins follow from step 3.

Traps. Pairing $V_{IL}$ with $V_{OH}$ in a margin: they are the same point, but a margin compares one gate’s output with the next gate’s input, so $NM_L$ pairs $V_{IL}$ with $V_{OL}$VOL​. Using the switching point (where $V_{out} = V_{in}$Vin​) as the limit instead of the −1 points. Giving firm directions for $V_{OH}$ and $V_{OL}$VOL​, which sit on the flat ends and barely move. Thinking that fanout changes a DC margin (MT17-1a).

5. MT24-1: noise on every node or on one node

MT24-1, p2: the question’s VTC (the faint mirrored curve and construction lines are handwritten on the key).

MT24-1a, p2: the inverter chain (source figure).

MT24-1, p2 (Fall 2024, 40 points). The VTC of a CMOS inverter, with $V_{OH}$VOH​, $V_{IL}$VIL​, $V_{OL}$ and $V_{IH}$ defined by the points where the slope is −1.

The tools are all in Chapter 6, Sections 4–5. The numbers below come from Chapter 6’s illustrative inverter (5 V, $V_T = \pm1\,\mathrm{V}$±1V, square law, equal strengths); the exam wants the reasoning, not numbers.

MT24-1a: noise on every node

MT24-1a, p2 (10 points). If DC noise is present on every logic node in the chain, what is the maximum DC noise a low node can tolerate (raising it), and a high node (lowering it)?

Hint

If every node is noisy, the node before this one is noisy too. Where does that leave this node before its own noise is added?

What it asks. A chain of inverters with DC noise on every node, each as large as it can be without breaking the chain. How far can the noise raise a low node, and lower a high node? The words “every logic node” decide the answer: the input of each inverter is itself degraded.

The idea. Picture the lecture’s chain, with a DC noise source between every pair of inverters (Chapter 6, Section 4). With the largest noise everywhere, every inverter is pushed exactly to the edge of amplifying: its input sits at one of the −1 points, and so does its output. The noise on a node may then move it from where its driver leaves it to where the next inverter starts to amplify, and no further.

Noise on every node

1. Where a low node starts. Its driver has a high input. With the largest noise, that input has been pulled down from $V_{OH}$ to $V_{IH}$VIH​, the lowest input still read as high, and at $V_{IH}$ the VTC gives the output $V_{OL}$VOL​. So the low node already sits at $V_{OL}$VOL​, not at 0 V.
2. Where it must stop. The next inverter starts to amplify when its input rises to $V_{IL}$VIL​. So the noise can add at most $V_{IL} - V_{OL} = NM_L$NML​.
3. A high node, the same way. Its driver’s input has been pushed up to $V_{IL}$VIL​, so it starts at $V_{OH}$VOH​, below $V_{DD}$VDD​. The next inverter amplifies once its input falls to $V_{IH}$VIH​. The noise can take away at most $V_{OH} - V_{IH} = NM_H$NMH​.
4. In Chapter 6’s inverter. $NM_L = 2.046 - 0.374 = 1.672\,\mathrm{V}$ and $NM_H = 4.626 - 2.954 = 1.672\,\mathrm{V}$1.672V: equal, because that inverter is symmetric.

Check. The answer has to hold all along the chain, and it does. A low node pushed up to $V_{IL}$ drives the next inverter to $V_{OH}$ (the upper −1 point), which is exactly where step 3 starts the next, high node; that one, pushed down to $V_{IH}$VIH​, drives the one after it to $V_{OL}$VOL​, where step 1 starts. Every inverter sits at a −1 point, alternating, as the lecture draws it.

Answer: a low node can take $NM_L = V_{IL} - V_{OL}$ (raising it); a high node $NM_H = V_{OH} - V_{IH}$ (lowering it).

Remember. A noise margin is the distance from where the node sits to where the next gate starts to amplify. With noise everywhere, the node starts at $V_{OL}$ or $V_{OH}$VOH​, not at the rail.

The answer key agrees

MT24-1b: noise on one node

MT24-1b, p3 (10 points). If DC noise is present only at a single node, what is the maximum DC noise it can tolerate when low, and when high?

Hint

Only this node is noisy, so the inverter driving it has a clean input. Where is that inverter’s output?

What it asks. The same two numbers, but now only one node in the chain is noisy.

The idea. The rule of (a) still holds: the margin runs from where the node sits to where the next gate starts to amplify. Only the starting point changes. The driving inverter now has a clean input, at 0 V or $V_{DD}$VDD​, so its output is at the opposite rail: a static CMOS output reaches the rail when its input is clean (Chapter 6, Section 5).

Noise on one node

1. A low node starts at 0 V, and the next inverter amplifies at $V_{IL}$VIL​: the noise can raise it by up to $V_{IL}$VIL​.
2. A high node starts at $V_{DD}$VDD​, and the next inverter amplifies at $V_{IH}$VIH​: the noise can lower it by up to $V_{DD} - V_{IH}$VIH​.
3. In Chapter 6’s inverter. 2.046 V for a low node, and $5 - 2.954 = 2.046\,\mathrm{V}$ for a high one.

Check. Each is larger than in (a) by exactly the head start that the clean driver gives: $V_{OL} = 0.374$ V on the low side ($2.046 - 1.672$2.046−1.672) and $V_{DD} - V_{OH} = 0.374$ V on the high side. That is why the lecture calls the every-node margins “extremely conservative”.

Answer: a low node can take $V_{IL}$VIL​; a high node $V_{DD} - V_{IH}$VIH​.

Remember. Same rule, different starting point: a clean driver leaves the node at the rail, so a single noisy node can take more than the textbook margin.

The answer key agrees

MT24-1c: a stronger PFET

MT24-1c, p3 (10 points). If the pFET is made stronger relative to the nFET, how does the VTC change? What happens to $V_{OH}$VOH​, $V_{IL}$VIL​, $V_{OL}$VOL​, $V_{IH}$ and the values in (a)?

Hint

The output switches where the NFET’s current matches the PFET’s. How high must the input go for that, once the PFET is stronger?

What it asks. Make the PFET stronger relative to the NFET (wider, for example). How does the VTC change, which way do the four voltages move, and what happens to the two margins of (a)?

The idea. This change moves the curve sideways; it doesn’t change how steep it is. The output switches where the NFET’s pull-down current matches the PFET’s pull-up current. Make the PFET stronger, and the NFET needs a higher input before it can match it: the switching point, and the whole steep part with it, moves right (Chapter 6, Section 4). Read the four points off the moved curve, then apply the margin formulas.

A stronger PFET

1. The steep part moves right, and both −1 points move with it: $V_{IL}$ and $V_{IH}$ increase.
2. The flat ends barely move. $V_{OH}$ and $V_{OL}$ sit on the nearly flat parts close to the rails, so they change little.
3. The margins follow. $NM_L = V_{IL} - V_{OL}$ increases, because its first term rose. $NM_H = V_{OH} - V_{IH}$ decreases, because the term it subtracts rose.
4. In Chapter 6’s inverter, with the PFET twice as strong. $V_{IL}$ 2.046 → 2.389 V and $V_{IH}$ 2.954 → 3.282 V, while $V_{OH}$ 4.626 → 4.587 V and $V_{OL}$ 0.374 → 0.294 V. So $NM_L$ 1.672 → 2.094 V and $NM_H$ 1.672 → 1.305 V.

Check. In words: a strong PFET holds the output high against a rising input for longer, so a low input can take more noise ($NM_L$NML​ up). The same strength makes a high input harder to act on: it has to rise further before the NFET wins ($NM_H$NMH​ down). And “barely move” is fair: $V_{IL}$ and $V_{IH}$ move by more than 0.3 V, $V_{OH}$ and $V_{OL}$ by less than 0.1 V.

Answer: the curve shifts right; $V_{IL}$ and $V_{IH}$ rise, $V_{OH}$ and $V_{OL}$ stay about the same; $NM_L$ grows and $NM_H$ shrinks.

Remember. Changing the strength ratio slides the curve, and trades one margin for the other. MT17-2 asks the same thing with three drawn curves (Section 6).

The answer key agrees

It says that $V_{OH}$ and $V_{OL}$ “stay the same”. That is an approximation: in Chapter 6’s model $V_{OL}$ falls by 0.08 V, small next to the 0.3 V moves of $V_{IL}$ and $V_{IH}$VIH​.

MT24-1d: a lower gain

MT24-1d, p3 (10 points). If the maximum small-signal gain of the inverter decreases with technology scaling, what effect does that have on $V_{OH}$VOH​, $V_{IL}$VIL​, $V_{OL}$VOL​, $V_{IH}$ and the values in (a)?

Hint

The output still has to fall from near $V_{DD}$ to near 0. If the middle of the curve is less steep, over how wide a range of inputs does that fall happen?

What it asks. As technology scales, an inverter’s largest small-signal gain (the steepest slope of its VTC) falls. What happens to the four voltages and to the margins of (a)?

The idea. This change makes the curve less steep instead of moving it sideways. The output still has to fall from near $V_{DD}$ to near 0. With a gentler middle, that fall is spread over a wider range of inputs, so the band where the slope is steeper than −1, between the two −1 points, gets wider on both sides.

A lower gain

1. The −1 points spread apart. $V_{IL}$ decreases and $V_{IH}$ increases.
2. Both margins shrink. $NM_L = V_{IL} - V_{OL}$ loses through its first term and $NM_H = V_{OH} - V_{IH}$ through its second, as long as $V_{OL}$ and $V_{OH}$ stay put. The band where noise is amplified has grown on both sides.
3. In Chapter 6’s inverter. Raising the output slope λ from 0.05 to 0.2 V⁻¹ lowers the peak gain from 30 to 10: $V_{IL}$ 2.046 → 1.885 V, $V_{IH}$ 2.954 → 3.115 V, and both margins 1.672 → 1.521 V.
4. $V_{OH}$ and $V_{OL}$ move little, and which way depends on the model. The key’s sketch draws a curve that is shallower everywhere, rounding off sooner at both ends; on that curve $V_{OH}$ falls and $V_{OL}$ rises. In Chapter 6’s square-law model they move by about 0.01 V the other way (4.626 → 4.636 V, 0.374 → 0.364 V).

Check. With the numbers of step 3, the band between the −1 points widens from 0.908 V to 1.230 V, and each margin loses about 0.15 V. The margins’ directions don’t depend on which curve you draw; only those of $V_{OH}$ and $V_{OL}$ do.

Answer: $V_{IL}$ down, $V_{IH}$ up, $NM_L$ and $NM_H$ both down. For $V_{OH}$ and $V_{OL}$VOL​, give the key’s picture (a curve that sags at both ends: $V_{OH}$ down, $V_{OL}$ up, each worth 2 points in its rubric), and say that it is your sketch’s assumption and that the change is small.

Remember. A sideways move (the strength ratio) trades one margin for the other; a flatter curve (a lower gain) costs both.

The answer key differs

It gives $V_{OH}$ decreasing and $V_{OL}$ increasing as firm directions, worth 2 points each. They depend on how the lower-gain curve is drawn (step 4); the margins’ directions are firm either way.

6. MT17-2: three transfer curves

MT17-2, p4. The source figure; the three handwritten labels are the key’s answer.

MT17-2, p4 (Fall 2017, 16 points). Three VTCs correspond to $W_p/W_n$ = 4 µm/1 µm, 2 µm/1 µm and 1 µm/1 µm. Label the curves and explain. Which gives the largest $NM_H$NMH​? Explain.

Hint

As the input rises, the NFET has to out-pull the PFET before the output can fall. For which inverter must the input rise furthest?

What it asks. Three VTCs, drawn with the same shape but switching at three different inputs, belong to three inverters that differ only in the PFET’s width. Match each curve to its sizing and say why; then say which inverter has the largest $NM_H$NMH​, and why. It is MT24-1c with three drawn curves; the moves are in How to approach a noise-margin question.

The idea. Changing $W_p/W_n$ changes the strength ratio, and that moves the curve sideways without changing its steepness. The output switches where the NFET’s pull-down current matches the PFET’s pull-up current. A wider PFET pulls up harder, so the NFET needs a higher input before it can match it: the switching point and the whole steep part move right (Chapter 6, Section 4). The margin then follows from where the −1 points sit: $NM_H = V_{OH} - V_{IH}$VIH​, the distance from the high output to the lowest input still read as high.

1. Order by strength. The wider the PFET, the stronger its pull-up, and the higher the input must go before the NFET can pull the output down. So the switching point moves right as $W_p$ grows.
2. Label the curves. From left to right: 1/1, 2/1, 4/1.
3. Read NM_H off each curve. $NM_H = V_{OH} - V_{IH}$VIH​. $V_{OH}$ sits on the flat top, close to 2.5 V on all three curves. $V_{IH}$VIH​, the lower −1 point, moves with the steep part, so it is smallest on the left-most curve.
4. Pick the largest. So the 1 µm/1 µm inverter has the largest $NM_H$NMH​. It pays with the smallest $NM_L$NML​: a weak PFET lets a low input that is pushed up start pulling the output down sooner (the trade-off of MT24-1c, in reverse).
5. Illustration in Chapter 6’s model (5 V; PFET half as strong per µm, so the three are 0.5×, 1× and 2× the NFET’s strength): $NM_H$ = 2.094, 1.672 and 1.305 V.

Check. Against MT24-1c: there, doubling the PFET’s strength took $NM_H$ from 1.672 to 1.305 V. Here 4/1 is twice as strong as 2/1, and the illustration gives the same two numbers, in the same direction. ✓

Answer: left 1/1, middle 2/1, right 4/1; the largest $NM_H$ is the 1/1 inverter’s, because it has the lowest $V_{IH}$VIH​.

Remember. Label VTCs by their switching point: the stronger the PFET, the further right. A weak PFET favours $NM_H$NMH​, a strong one $NM_L$NML​.

The answer key agrees

How to approach a gate-delay question

Recognize it by the picture: one gate, an inverter or a NAND, with every transistor labelled with its width, driving a fixed capacitor, and the words “estimate the delays as multiples of the fanout-of-one delay $\tau_{inv}$τinv​”. It asks for both edges (input rising to output falling, and the reverse), and, for a stacked gate, how another input’s delay compares. It has appeared once, MT17-3a, b and d, for 24 points. The same conversion is the first move of every path-sizing question (M4’s approach).

The moves, in order.

1. Read the strength convention. It sets the unit. Equal strengths: the balanced inverter is W/W and $\tau_{inv} = 2RC_g$2RCg​. $R_{pfet} = 2R_{nfet}$2Rnfet​: it is 2W/W and $\tau_{inv} = 3R_{nfet}C_g$3Rnfet​Cg​.
2. Convert the load to µm of gate: $C_L/C_g$CL​/Cg​.
3. For each edge, find the conducting path. Output falling: the pull-down NFETs that are on. Output rising: the pull-up PFETs that are on. Then find the path’s effective width $W_{eff}$Weff​.
4. Divide. The delay is $(R/W_{eff})\,C_L$(R/Weff​)CL​; divide it by $\tau_{inv}$τinv​. With equal strengths that is $\dfrac{C_L/C_g}{2W_{eff}}\,\tau_{inv}$2Weff​CL​/Cg​​τinv​.
5. “How does another input compare?” Argue it from the stack’s internal nodes. The model can’t compute it.

Why these formulas.

• The delay model. The conducting transistor acts as a resistor $R/W$ that charges or discharges the load, so a stage takes $(R/W)\,C_L$ (Chapter 7, Section 1).
• The unit. $\tau_{inv}$ is the balanced inverter driving its own copy. With equal strengths that is $(R/W)(2W\,C_g) = 2RC_g$2RCg​: the width cancels (Chapter 7, Section 7). So a delay in units of $\tau_{inv}$ is the load in µm of gate divided by $2W_{eff}$2Weff​, the input of a W/W inverter as strong as the path: how many such inverters the load is worth.
• The stack rule. Transistors in series add their resistances, so $n$ devices of width $W$ in series act as one of width $W/n$W/n, and in general $W_{eff} = 1/\sum(1/W_i)$1/∑(1/Wi​). Of devices in parallel, only those that are on count; when a single input switches, that is one (Chapter 7, Section 8).
• The bottom of a stack. A device low in a stack must first discharge the internal nodes above it, so it is slower than the model says; the lecture puts the penalty at roughly the square of the stack height (Chapter 8, Section 10).

Decisions to make on the way. Which convention the question states (MT17-3 puts “same strength” in bold italics). Which network carries each edge. Which devices are on for the stated inputs.

Traps. Using $3R_{nfet}C_g$ when the question says equal strengths. Counting all the parallel PFETs when only one input switches. Forgetting that a stack of $n$ acts as $1/n$ of the width. Trying to compute the bottom-input penalty instead of explaining it.

7. MT17-3: gate delays in units of the FO1 delay

MT17-3, p5 (Fall 2017). Estimate the delays as multiples of the fanout-of-one delay $\tau_{inv}$τinv​. Assume that the nFET and pFET have the same strength. Handwritten on the exam: assume 2 fF/µm of gate capacitance.

Set up once. Every part divides a delay by $\tau_{inv}$τinv​, so put both in the same terms first.

• The unit. The question says the two devices have the same strength: an NFET and a PFET of the same width drive the same current. So the balanced inverter is W/W, and its fan-out-of-one delay is $\tau_{inv} = \dfrac{R}{W}(2W\,C_g) = 2RC_g$ (Chapter 7, Section 7).
• The load. 50 fF at 2 fF/µm is 25 µm of gate.
• The ratio. A device (or stack) of effective width $W_{eff}$ driving the load takes $(R/W_{eff})(25\,\mu\mathrm{m})\,C_g$(R/Weff​)(25μm)Cg​. Dividing by $\tau_{inv} = 2RC_g$2RCg​, the unknown $R$ and $C_g$ cancel:

$$\frac{R}{W_{eff}}\,(25\,\mu\mathrm{m})\,C_g = \frac{25}{2W_{eff}}\,\tau_{inv}$$

with $W_{eff}$ in µm. In words: the load in µm of gate over $2W_{eff}$2Weff​, the input of a W/W inverter as strong as the path.

MT17-3a and b: two inverters

MT17-3a, p5.

MT17-3b, p5.

MT17-3a, p5 (8 points). Calculate the A-rising-to-Y-falling and A-falling-to-Y-rising delays of the inverter with a 2 µm PFET and a 1 µm NFET driving 50 fF.

MT17-3b, p5 (8 points). The same with an 8 µm PFET.

Hint

For each edge, which one transistor carries the current, and how wide is it?

What it asks. For each inverter, two delays in units of $\tau_{inv}$τinv​: A rising to Y falling, where the NFET discharges the 50 fF, and A falling to Y rising, where the PFET charges it. The two circuits differ only in the PFET’s width, 2 µm in (a) and 8 µm in (b). The bold italics of the question, “the same strength”, decide the unit.

The idea. Each edge has its own conducting path, here a single transistor: the one that is on while the other is off. Its delay is the set-up’s $\dfrac{25}{2W_{eff}}\,\tau_{inv}$ with $W_{eff}$ its width. With equal strengths a PFET counts like an NFET of the same width, so no factor of 2 enters. The tempting slip is the lectures’ default convention, $R_{pfet} = 2R_{nfet}$ with $\tau_{inv} = 3R_{nfet}C_g$3Rnfet​Cg​, as in Chapter 7’s check: the answers would differ. Read which convention the question states.

1. Y falling, both circuits. A rises, so the NFET turns on and the PFET off; the 1 µm NFET discharges the load: $\dfrac{25}{2 \times 1}\tau_{inv} = 12.5\tau_{inv}$12.5τinv​, in both circuits.
2. (a) Y rising. A falls, so the PFET turns on; with equal strengths the 2 µm PFET drives like a 2 µm NFET: $\dfrac{25}{2 \times 2}\tau_{inv} = 6.25\tau_{inv}$6.25τinv​.
3. (b) Y rising. The same, through the 8 µm PFET: $\dfrac{25}{2 \times 8}\tau_{inv} = 1.5625 \approx 1.56\tau_{inv}$1.56τinv​.
4. Why (b)‘s falling delay doesn’t change. The PFET is off while Y falls, so its width doesn’t help, and with a fixed 50 fF load it adds nothing to Y. (Its larger gate loads A, which is the previous stage’s concern.)

Check. The rising delay goes as $1/W_p$1/Wp​: the 8 µm PFET is 4 times the 2 µm one, and $6.25/4 = 1.5625$1.5625. ✓ Note also that under equal strengths (a)‘s 2/1 inverter is not balanced: it rises twice as fast as it falls.

Answers: (a) 12.5 $\tau_{inv}$ falling, 6.25 $\tau_{inv}$ rising; (b) 12.5 $\tau_{inv}$ falling, 1.56 $\tau_{inv}$ rising.

Remember. One edge, one conducting path. With equal strengths the delay in $\tau_{inv}$ is the load in µm of gate divided by twice the path’s width. Read the strength convention before you write $\tau_{inv}$τinv​.

The answer key differs

It gives 6.75 $\tau_{inv}$ for (a)‘s rising delay, although its own fraction is $25/4 = 6.25$6.25: a slip. Its other numbers agree.

MT17-3d: a four-input NAND

MT17-3d, p7 (source figure).

MT17-3d, p7 (8 points). Calculate the delays from A rising to Y falling and A falling to Y rising, with B = C = D = 1. How will the delay from D rising to Y falling (with A = B = C = 1) compare with the A-rising delay? Explain.

Hint

For Y to fall, which NFETs must conduct, and how does a stack of four in series compare with one transistor?

What it asks. The NAND4’s two delays when A switches with B = C = D = 1, in units of $\tau_{inv}$τinv​, and then a comparison: is D rising (with A = B = C = 1) faster or slower than A rising? “Explain” means the comparison is argued, not computed.

The idea. Two rules from the chapters set the widths. In series, resistances add, so four 4 µm NFETs act like one of $4/4 = 1$ µm (Chapter 7, Section 8). In parallel, only the devices that are on count: with B, C and D high, their PFETs are off, and only A’s pulls up. The comparison needs a third idea, the internal nodes between the stacked NFETs (Chapter 8, Section 10). The delay model ignores their capacitance, so it gives every input the same 12.5 $\tau_{inv}$τinv​; the difference has to be argued from what those nodes hold before the input switches.

1. Y falling: the whole stack. A rises with B, C and D already on, so all four 4 µm NFETs conduct in series. Their resistances add, $4 \times R/4 = R$R, so they act like one device a quarter as wide: $W_{eff} = 4/4 = 1\,\mu\mathrm{m}$1μm, and $\dfrac{25}{2 \times 1}\tau_{inv} = 12.5\tau_{inv}$12.5τinv​.
2. Y rising: one PFET. A falls; B, C and D are high, so their PFETs are off and only A’s 4 µm PFET turns on: $\dfrac{25}{2 \times 4}\tau_{inv} = 3.125\tau_{inv}$3.125τinv​.
3. What D finds when it rises. Before the edge A, B and C are on and D is off. So the three internal nodes above D are connected through A, B and C to Y, which is high, and they charge to about $V_{DD} - V_T$VT​: an NFET stops passing charge once its gate is only $V_T$ above its source.
4. Why that is slower. When D turns on it must discharge those three nodes, as well as Y, through the same stack before Y can fall. More charge through the same current takes longer: D rising is slower.
5. Why A is the fast case. When A switches last, B, C and D have been on, so the nodes below A are already at ground and only Y moves. That is the case the model describes, and the lecture says the penalty for a lower input grows about as the square of the stack height.

Check. The stack’s pull-down equals (a)‘s 1 µm NFET, and so does its falling delay, 12.5 $\tau_{inv}$τinv​: four series devices are sized four times as wide to keep one device’s strength. ✓

Answers: 12.5 $\tau_{inv}$ falling and 3.125 $\tau_{inv}$ rising; the D input is slower, because it must first discharge the internal nodes of the stack.

Remember. Series widths combine as $1/\sum(1/W_i)$1/∑(1/Wi​); of parallel devices, only the one that switches counts. The input at the bottom of a stack is the slowest, so a late-arriving signal goes to the input nearest the output.

The answer key agrees

How to approach a device short-answer question

Recognize it by its size: one device or one inverter, few numbers or none, and a request to calculate or explain one thing. The exams’ phrases: “calculate the fanout-of-four delay as a function of the transit time and $\eta$η”, “is there static DC current? Think carefully about the complete structure of the devices”, “what is $I_D$ at $V_{GS} = 0$ at 300 K? At 400 K?”. MT21-2 carried 25 points and MT17-1b–c 16. (MT17-1a, fanout and the noise margin, belongs to the noise-margin family.)

The moves, in order.

1. Name the physics the question tests: a delay (charge over current), a junction (which way it is biased), or subthreshold leakage (decades below threshold).
2. Draw what matters. For a delay, the node and every capacitance on it. For a junction, the device’s cross-section: which p and n regions touch, and at what voltages. For leakage, how far the gate is below threshold.
3. Write the one relation, with its conditions.
4. Put in the numbers or the symbols, keep the units, and say in one sentence what the result means.

Why these formulas.

• Charge over current. A node of capacitance $C$ at $V_{DD}$ holds the charge $V_{DD}C$VDD​C, and a saturated transistor removes it at the current $I_{DSAT}$IDSAT​, so the delay is $t \approx V_{DD}C/I_{DSAT}$VDD​C/IDSAT​. With a velocity-saturated current and $V_{DD} \gg V_T$VT​, one device’s $V_{DD}C_g/I_{DSAT}$ is $L/v_{sat}$L/vsat​, the transit time $\tau_{tr}$ (Chapter 5, Section 11).
• Junctions. A MOSFET’s source and drain form p–n junctions with its body. Tying the n well to $V_{DD}$ and the p substrate to ground keeps every one of them reverse-biased; a body tied anywhere else can forward-bias one, and a forward-biased junction conducts heavily (Chapter 5, Section 8).
• Subthreshold current. Below threshold the current falls one decade for every $S$ millivolts below $V_T$VT​, and $S = m\,(kT/q)\ln 10$ is proportional to the absolute temperature added (Chapter 4, Section 11).

Decisions to make on the way. The strength convention (a W/W inverter gives a factor 2, a 2W/W one a factor 3). Which rail each body is tied to. What the question holds fixed when the temperature changes (MT17-1c keeps $V_T$ and the current at threshold).

Traps. Taking FO4 as four times FO1: only the gate load grows with the fanout, not the driver’s drains. Reading the transistor symbol instead of the structure. Keeping 60 mV/decade at 400 K.

8. MT21-2: FO4 from the transit time

MT21-2, p4: the key’s sketch (the question has no figure).

MT21-2, p4 (Fall 2021, 25 points). Calculate the fanout-of-four delay as a function of the transit time $\tau_{tr}$ and $\eta = C_g/C_d$Cg​/Cd​. Assume the pFET has exactly the same drive current as an nFET of the same size.

Hint

The delay is the charge on the output node divided by the current that removes it. Which capacitances sit on that node when the inverter drives four copies of itself?

What it asks. The fan-out-of-four delay, an inverter driving four copies of itself, as a formula in the transit time $\tau_{tr}$ and $\eta = C_g/C_d$Cg​/Cd​, the ratio of a device’s gate capacitance to its drain capacitance. “Exactly the same drive current as an nFET of the same size” decides the sizing: the inverter is W/W, not the lecture’s 2W/W.

The idea. Delay is charge over current. The output node at $V_{DD}$ holds the charge $V_{DD}C_{node}$VDD​Cnode​, and the one transistor that switches removes it at its saturated current $I_{DSAT}$IDSAT​, so $t \approx V_{DD}C_{node}/I_{DSAT}$ (Chapter 5, Section 11). For one device with a velocity-saturated current, $I_{DSAT} = WC_{ox}v_{sat}(V_{DD} - V_T)$VT​), and with $V_{DD} \gg V_T$ the ratio $V_{DD}C_g/I_{DSAT}$ becomes $L/v_{sat} = \tau_{tr}$τtr​: $W$ and $C_{ox}$ cancel. So the whole question is to count the capacitance on the node in units of $C_g$Cg​. Count what hangs on the driver’s output node: the input gates of the four loads, and the driver’s own drains, since both of its transistors connect their drains to that node. Each load’s drains sit on the next node, which this delay doesn’t charge, so they are not counted. The tempting slip is FO4 = 4 × FO1, which counts four drivers’ drains.

FO4 of a W/W inverter

1. The sizes. Equal currents mean the PFET needs no extra width, so the inverter is W/W: its input is $C_g + C_g = 2C_g$ and its own drains are $C_d + C_d = 2C_d$ (Chapter 5, Section 12, with a $W$ PFET instead of $2W$2W).
2. Charge over current. $t = V_{DD}\,C_{node}/I_{DSAT}$VDD​Cnode​/IDSAT​, and $V_{DD}C_g/I_{DSAT} = \tau_{tr}$ for one device. On either edge one device of width $W$ does the work (the NFET falling, the PFET rising, with the same current), so this $I_{DSAT}$ is the right one.
3. FO1 first, as a reference. One load: $\dfrac{V_{DD}(2C_g + 2C_d)}{I_{DSAT}} = 2\tau_{tr}\left(1 + \dfrac{1}{\eta}\right)$2τtr​(1+η1​), using $C_d = C_g/\eta$Cg​/η.
4. FO4. Four loads’ gates but one driver’s drains: $\dfrac{V_{DD}(8C_g + 2C_d)}{I_{DSAT}} = 2\tau_{tr}\left(4 + \dfrac{1}{\eta}\right)$2τtr​(4+η1​).

Check. Against Chapter 5, Section 13: $\mathrm{FO4}/\mathrm{FO1} = (4\eta + 1)/(\eta + 1)$1), the same ratio as for the 2W/W inverter; only the factor 3 becomes 2. For scale: $\tau_{tr} = 2.5\,\mathrm{ps}$ and $\eta = 2$ give FO1 = 7.5 ps and FO4 = 22.5 ps, three times FO1, not four.

Answer: $\mathrm{FO4} = 2\tau_{tr}\left(4 + \dfrac{1}{\eta}\right)$2τtr​(4+η1​).

Remember. Count the loads’ gates times the fanout, and the driver’s drains once. The strength convention sets the factor: 2 for W/W, 3 for 2W/W.

The answer key agrees

9. MT17-1: short answers (fanout, a grounded well, leakage and temperature)

MT17-1a: fanout and the static noise margin

MT17-1a, p2 (8 points). What effect does fanout have on the static DC noise margin of a CMOS gate? Explain.

Hint

The margins are read off the DC transfer curve. Does a capacitor on the output change where the output settles?

What it asks. Whether driving more gates (a larger fanout) changes a gate’s static DC noise margins, and why. The words “static DC” decide it: the margins belong to the settled, DC behaviour. This is a noise-margin question; its moves are in How to approach a noise-margin question.

The idea. The margins come from the two −1 points of the VTC (Chapter 6, Section 4), and the VTC is the settled output for each input: the output voltage at which the PFET’s current equals the NFET’s. Anything that doesn’t change that balance doesn’t change the margins. A CMOS input is a gate on an oxide, a capacitor, and at DC a capacitor carries no current.

1. What sets the margins. The static DC margins come from the DC transfer curve: where the settled output lies for each input (Chapter 6, Section 5).
2. What fanout adds. More gates on the output. Each is a capacitor: a CMOS gate input draws no DC current, and a capacitor carries none once it has charged.
3. So the balance is unchanged. With no DC current into the loads, the output still settles where the pull-up current equals the pull-down current, for any input. The VTC, $V_{IL}$VIL​, $V_{IH}$VIH​, $V_{OH}$VOH​, $V_{OL}$ and both margins are unchanged.
4. What fanout does change. The capacitance to charge, so it only slows the switching.

Check. The limiting case: with a huge fanout the output takes a very long time to settle, but it settles at the same voltage. Speed and level are separate.

Answer: none; the margins are a DC property, and capacitive loading carries no DC current.

Remember. A DC margin comes from the DC curve. A capacitive load changes the timing, never the curve.

The answer key agrees

MT17-1b: a well tied to ground

MT17-1b, p2 (source figure): the PFET’s body (its n well) goes to ground.

MT17-1b, p2 (8 points). The n well of the pFET is tied to ground. $V_{DD} = 2.5\,\mathrm{V}$ and $V_{in} = 0$0. Is there static DC current? Explain. Hint: think carefully about the complete structure of the devices.

Hint

The PFET’s source is a $p^+$ region inside its n well. With the source at $V_{DD}$ and the well at ground, which way is that junction biased?

What it asks. An inverter whose PFET has its n well (its body) tied to ground instead of $V_{DD}$VDD​, with $V_{in} = 0$0: does a DC current flow, and why? The exam’s hint, “the complete structure of the devices”, says to look past the transistor symbol to the junctions inside it.

The idea. A MOSFET is also a set of p–n junctions: its source and its drain each form one with the body. The usual ties, the n well to $V_{DD}$ and the p substrate to ground, are chosen so that every one of those junctions stays reverse-biased, whatever the circuit does (Chapter 5, Section 8). Tie a body anywhere else and you have to check each junction. A junction whose p side is well above its n side is forward-biased, and a forward-biased junction conducts heavily. That is the whole argument: the transistor’s on or off state doesn’t enter.

1. Look at the structure, not the symbol. The PFET’s source and drain are $p^+$ regions inside the n well, and the well reaches ground through its $n^+$ well contact.
2. Bias the source junction. The source is at $V_{DD} = 2.5\,\mathrm{V}$ and the well at 0 V: the p side is 2.5 V above the n side, so that $p^+$/n junction is forward-biased by 2.5 V.
3. Follow the current. A forward-biased junction conducts heavily, so current flows from $V_{DD}$ through the source junction into the well and out of the well contact to ground. It never passes through the channel, so it flows whatever the transistors do.
4. The drain as well. With $V_{in} = 0$ the PFET is on and pulls the output up toward $V_{DD}$VDD​, so the drain junction, in the same grounded well, is forward-biased too.

Check. Put the well back at $V_{DD}$VDD​: the source junction then has 0 V across it and the drain junction is reverse-biased (the output can’t rise above $V_{DD}$VDD​), so no current flows. Only the tie changed, so the tie causes the current.

Answer: yes, a large static current through the forward-biased source junction (and the drain’s).

Remember. The n well goes to the highest voltage and the p substrate to the lowest. When a question ties a body anywhere else, check every source and drain junction for forward bias. The Fall 2026 instructor calls this kind of circuit “a classic exam problem that I often give” (Fall 2026 Lecture 4, 30:09).

The answer key agrees

It names only the source junction; the drain junction, in the same well, is forward-biased too.

MT17-1c: subthreshold current at two temperatures

MT17-1c, p3 (8 points). If $I_D = 10\,\mu\mathrm{A}$ at $V_{GS} = V_T = 1\,\mathrm{V}$ for an nFET, what is $I_D$ at $V_{GS} = 0$ at 300 K, with a 60 mV/decade subthreshold slope? What is it at 400 K?

Hint

How many decades below threshold is $V_{GS} = 0$ at each temperature, given that the subthreshold slope is proportional to $T$T?

What it asks. The current of an off NFET ($V_{GS} = 0$VGS​=0, a full volt below its threshold) at 300 K, with a 60 mV/decade slope, and again at 400 K. The words “at 400 K” carry the points: the slope changes with temperature. The problem keeps $V_T$ and the 10 µA at threshold fixed.

The idea. Below threshold the current falls by one decade for every $S$ millivolts that the gate is below $V_T$VT​, $I_D = I(V_T)\cdot10^{-(V_T - V_{GS})/S}$10−(VT​−VGS​)/S, as in MT24-2b (Chapter 4, Section 11). The slope is $S = m\,(kT/q)\ln 10$m(kT/q)ln10: carriers cross the barrier by thermal energy, so it is proportional to the absolute temperature added. A hotter device needs more millivolts per decade, so the same 1 V below threshold buys fewer decades of turn-off. Scaling the slope with $T$ is the step the exam tests.

1. Decades at 300 K. 1000 mV below threshold at 60 mV per decade is $1000/60 = 16.7$ decades.
2. The current at 300 K. $I_D = 10\,\mu\mathrm{A} \times 10^{-16.67} = 10^{-5} \times 2.15\times10^{-17} = 2.15\times10^{-22}\,\mathrm{A}$10−22A.
3. The slope at 400 K. Because $S$ is proportional to the absolute temperature added, at 400 K it is $60 \times 400/300 = 80\,\mathrm{mV/decade}$80mV/decade.
4. Decades and current at 400 K. Now $1000/80 = 12.5$ decades: $I_D = 10^{-5} \times 10^{-12.5} = 3.16\times10^{-18}\,\mathrm{A}$10−18A.
5. Compare. The leakage grows by $10^{16.67 - 12.5} = 1.47\times10^4$104: four decades from a third more temperature.

Check. The 300 K slope is the ideal one ($m = 1$m=1, about 60 mV/decade), as it should be at room temperature. And the size of the effect: the number of decades falls by only a quarter ($12.5/16.7 = 0.75$12.5/16.7=0.75), but the current is an exponential of that number, so a quarter of 16.7 decades is four decades of current.

Answer: $2.15\times10^{-22}$ A at 300 K and $3.16\times10^{-18}$ A at 400 K.

Remember. Leakage is counted in decades below threshold, and the slope grows in proportion to the absolute temperature. A modest temperature rise costs orders of magnitude of leakage.

The answer key agrees

Patterns

Inverter chain (every midterm, 23–25% of the points; the approach).

• Moves: the node capacitance first (both gates of the next input plus the fixed load); the strengths; energy = rising nodes × $C_{node}V_{DD}^2$Cnode​VDD2​; leakage = $V_{DD}I_{off}\times$ off width × time; delay $N(R/W)C_{node}$N(R/W)Cnode​; the optimum where the growing and shrinking parts balance.
• Results that come back: energy × delay is least where the gates’ load equals the fixed load; delay alone has no finite optimum; the best PFET ratio is $\sqrt{R_{pfet}/R_{nfet}}$Rpfet​/Rnfet​​; $W$ cancels from the leakage share.
• Traps: per cycle against per transition; the off width in a 2W/W inverter (1.5W on average); nA, not pA; $T_{cycle}$ left in.
• Time: about 15–20 minutes for the full 34–50 points.

Noise margins (MT24-1, MT17-2, MT17-1a; the approach).

• Moves: where the node sits before its noise ($V_{OL}$VOL​/$V_{OH}$ if every node is noisy, the rail if one is); where the next gate starts to amplify ($V_{IL}$VIL​, $V_{IH}$VIH​); the margin is the distance; for a change, sideways (strength) or flatter (gain).
• Traps: pairing $V_{IL}$ with $V_{OH}$ in a margin; firm directions for $V_{OH}$ and $V_{OL}$VOL​; thinking fanout changes a DC margin.
• Time: explanation questions. Two or three sentences and a sketch per part, about 3 minutes each.

Gate delays in τ_inv (MT17-3; the approach).

• Moves: the strength convention ($\tau_{inv} = 2RC_g$τinv​= or $3R_{nfet}C_g$3Rnfet​Cg​); the load in µm of gate; the conducting path and its effective width for each edge; divide.
• Traps: $3R_{nfet}C_g$ under equal strengths; all the parallel PFETs counted; a stack of $n$ not taken as $1/n$ of the width; computing the bottom-input penalty instead of explaining it.
• Time: one division per delay, a few minutes per part; spend the rest on the stack explanation.

Device short answers (MT21-2, MT17-1b–c; the approach).

• Moves: name the physics; draw the node, the cross-section or the decades; one relation with its conditions.
• Delay is charge over current: loads’ gates times the fanout, the driver’s drains once; factor 2 for W/W, 3 for 2W/W.
• A body tied to the wrong rail forward-biases a junction: large static current. The subthreshold slope scales with the absolute temperature added; count decades.
• Traps: FO4 = 4 × FO1; reading the symbol instead of the structure; 60 mV/decade at 400 K. Time: a few minutes each, most of it on the explanation.

What the keys get wrong

Re-solving every part found these disagreements; all are recorded in this page’s review/decisions.md.

Part	The key	Here
MT17-3a	6.75 $\tau_{inv}$ rising	$25/4 = 6.25\,\tau_{inv}$
MT23-1b	60 pA/µm, $108\,WTN$ pJ	60 nA/µm, $108\,NWT$ nJ ($T$T in s)
MT23-1c	dynamic energy $\tfrac N2(4.32W + 5.76)$ fJ (one transition), $T$ left in, pA carried over	per-cycle energy from (a), $T$ = chain delay: $7.5\times10^{-5}N/(1 + 7.5\times10^{-5}N)$
MT24-1c	$V_{OH}$VOH​, $V_{OL}$ “stay the same”	about the same (they move by under 0.1 V in Chapter 6’s model)
MT24-1d	$V_{OH}$ decreases, $V_{OL}$ increases	depends on how the lower-gain curve is drawn; the margins’ directions are firm

Every other part (MT17-1a–c, MT17-2, MT17-3b, d, MT17-4a–d, MT21-2, MT21-4a–c, MT23-1a, d, MT24-1a–b, MT24-2a–e) agrees with its key after re-solving.