H1. Homework 1: MOSFET I–V, junction capacitance and scaling

Homework 1 is the course’s own practice for the device chapters: the two I–V models, the pn junction as a capacitor, where a transistor stops conducting, subthreshold leakage, and scaling. This page re-solves every part that the midterm material covers, in the homework’s order, one section per problem.

Every number below is re-solved here and checked in this page’s review/examples.check.ts; none is copied from the key. Where the key disagrees, the folded note on the key at the end of the part explains why, and the table at the end lists them all.

After this page you can:

1. read a family of I–V curves and tell square law from velocity saturation by the spacing of the tops, and say how far a device is from the linear limit;
2. find the range of a junction capacitance from the range of voltages its node can reach;
3. find where a capacitor stops discharging through one or two transistors, and the region of each device on the way;
4. count decades of subthreshold current;
5. extract $v_{sat}$ and a width from evenly spaced I–V tops, and say why the extracted $v_{sat}$ comes out low;
6. scale any quantity when lengths and voltages shrink by different factors.

Before you start

What the source is. The file is the solution key only: the homework’s question text and two of its figures (problems 1b and 4) are not in it. Each part below is restated from what the key shows, its circuits, its given values and its working, and labelled “(from the key)”. Pages are physical PDF pages of the key (HW1-2c, p3). The key gives 20 points to problem 1, 30 to problem 2, 10 to problem 3, 20 to problem 4 and 20 to problem 5.

How to use this page. Every part is worked the same way: what it asks, the idea behind the method, the solution in steps (each step gives its reason first), a check on the result, the answer, and one thing to remember. Try each part on your own first; open the Hint if you are stuck, and step through the solution before you press “Show all”. The answer key’s verdict is folded at the end of each part. The homework’s methods are taught as families on other pages, and each problem links its family’s section: reading an I–V family on page H2, where a transistor stops on page M5, and subthreshold decades on page M3.

Problem	Parts	Points	Method	Chapters
1	a: I–V with and without velocity saturation (simulation); b: junction-capacitance range	20	the two I–V models; $C_j = \kappa_s\varepsilon_0/W$	3, 4, 5
2	a–c: final voltage and regions; d: with a BJT (out)	30	regions; a device stops at its own threshold	4, 10
3	subthreshold current at $V_{GS} = 0$	10	count decades	4
4	a: $v_{sat}$ for electrons and holes; b: a width	20	$I_{DSAT} = C_{ox}Wv_{sat}(V_{GS} - V_T)$	4
5	how ten quantities scale, long-channel and saturated	20	constant-field scaling, generalized	1, 4

Conventions.

• PMOS: every NMOS formula holds with $V_{SG}$ for $V_{GS}$VGS​, $V_{SD}$ for $V_{DS}$ and $|V_T|$ for $V_T$VT​; the current flows out of the drain (Chapter 4, Section 9). The key’s plots label the axes $V_{DS}$ and $I_{DS}$IDS​; for its PMOS they mean $V_{SD}$ and the current out of the drain.
• Problem 2 uses $|V_T| = 1\,\mathrm{V}$ for both device types and a capacitor charged to 5 V (the key’s values). The threshold model: a device conducts while $V_{GS} > V_T$ and is off below; subthreshold leakage is ignored there.
• Problem 1b uses the key’s constants: $kT/q = 0.026\,\mathrm{V}$0.026V, $n_i = 1.1\times10^{10}\,\mathrm{cm^{-3}}$1010cm−3, $\kappa_s = 11.7$11.7.
• Readings from the key’s plot. There is no simulator here. Where a number comes off one of the key’s plots, it says so; the page redoes the arithmetic, it does not reproduce the simulation.

1. HW1-1: PMOS curves and a junction’s capacitance range

HW1-1a: with and without velocity saturation

HW1-1a, p1: without velocity saturation (the key’s plot; current axis in A).

HW1-1a, p1: with velocity saturation (the key’s plot; current axis ×10⁻³ A).

HW1-1a, pp1–2 (10 points; from the key). Plot the PMOS I–V curves for $V_{SG} = 0$ to 5 V in 0.5 V steps, without and with velocity saturation, and explain the difference.

The lecture sets this up: Chapter 4’s velocity-saturated derivation follows Taur and Ning, “and the problem set has you plot the results” (Chapter 4, Section 6, 23:16–23:35). The two plots are the key’s. What follows is how to read them, and a check that they are Chapter 4’s two models.

Hint

Two features of a family tell the models apart: how the tops are spaced, and where each curve flattens. What does each model predict for both?

What it asks. The key has done the plotting: the same PMOS, first with the long-channel model and then with velocity saturation, for $V_{SG}$ from 0 to 5 V. What is left is “explain the difference”: say what the second family does differently, point to it on the curves, and say why. No device parameters are given, so the explanation has to come from the shapes.

The idea. This is the reading of an I–V family that page H2, Section 2 teaches: look at the spacing of the tops and at where the curves flatten. (H2’s third sign, how the current scales with $L$L, needs two channel lengths; here there is one.) What is new is that both families come from one device, so you can measure how far the second one is from each of Chapter 4’s two models.

• Square law (Chapter 4, Section 4): $I_{DSAT} = \tfrac{\beta}{2}U^2$2β​U2, where $U = V_{SG} - |V_T|$ is the overdrive and $\beta = \mu C_{ox}W/L$μCox​W/L. The curve flattens where the channel pinches off at the drain, at $V_{SD} = U$U. It holds while the field along the channel stays well below the critical field $\mathcal{E}_{crit}$Ecrit​, so that the carriers drift at $\mu\mathcal{E}$μE.
• Velocity-saturated (Chapter 4, Section 7): the drift velocity levels off near $v_{sat} = \mu\mathcal{E}_{crit}$μEcrit​, so more overdrive adds charge to the channel but no more speed. Then $I_{DSAT} = C_{ox}Wv_{sat}U\,\dfrac{s - 1}{s + 1}$ with $s = \sqrt{1 + 2U/(\mathcal{E}_{crit}L)}$1+2U/(Ecrit​L)​, and the curve flattens earlier, at $V_{DSAT} = 2U/(1 + s)$s). Only when $2U$ is much larger than $\mathcal{E}_{crit}L$ does $(s - 1)/(s + 1)$ approach 1, and the current approach the linear limit $C_{ox}Wv_{sat}U$Cox​Wvsat​U.

The quick test between them is to double the overdrive. The square law multiplies the top by 4, the linear limit by 2, and a factor in between means the device is partly saturated. The tempting answer is “with velocity saturation the current is linear”, because the top curves look evenly spaced; the doubling test says how far from linear they really are.

Reading the two families

1. Find the threshold first, because both models are written in the overdrive. The $V_{SG} = 0$0, 0.5 and 1 V curves lie on the axis, and 1.5 V is the first that conducts: $|V_T| = 1\,\mathrm{V}$1V. Write the overdrive $U = V_{SG} - |V_T|$∣VT​∣, from 0.5 to 4 V.
2. Look where each curve flattens, because the two models put the knee in different places. Without velocity saturation the knee is at $V_{SD} = U$U: 4 V for the top curve, the long-channel $V_{DSAT}$ (Chapter 4, Section 4). With it, the top curve flattens near 2.6 V: earlier, as the lecture says (Chapter 4, Section 7).
3. Read the tops without velocity saturation, to confirm that the first family is the square law. Readings from the key’s plot (table below): 0.18, 0.70, 1.57, 2.79, … 11.15 mA. Each is $(\beta/2)U^2$ with $\beta/2 = 11.15/16 = 0.697\,\mathrm{mA/V^2}$0.697mA/V2, to within 0.02 mA.
4. Read the tops with velocity saturation, the family the question is about. 0.14, 0.50, 1.00, 1.60, … 4.68 mA: lower, and nearly evenly spaced at high overdrive.
5. Apply the doubling test, because even spacing alone can’t tell “linear” from “nearly linear”. From $U = 2$ to 4 V the long-channel top grows $11.15/2.79 = 4.0$ times (square); the velocity-saturated one $4.68/1.60 = 2.9$ times. Linear would be 2. So this device is partly velocity-saturated, not fully.
6. Fit Chapter 4’s model, to put a number on “partly” added. At the same overdrive, the velocity-saturated current divided by the square law’s is $4/(s + 1)^2$1)2, since $\mu/v_{sat} = 1/\mathcal{E}_{crit}$1/Ecrit​. The top curves’ $4.68/11.15$ gives $s = 2.09$ and $\mathcal{E}_{crit}L = 2.38\,\mathrm{V}$2.38V.
7. Measure the distance from the linear limit, because “linear” is the claim to test. At $U = 4\,\mathrm{V}$4V, $(s - 1)/(s + 1) = 35\%$35%: the current is 35% of $C_{ox}Wv_{sat}U = \beta\,\mathcal{E}_{crit}L\,U = 13.3\,\mathrm{mA}$13.3mA, and 42% of the square law’s 11.15 mA.

$V_{SG}$ (V)	$U$ (V)	without: reading (mA)	$0.697U^2$	with: reading (mA)	Chapter 4 model
1.5	0.5	0.18	0.17	0.14	0.15
2	1	0.70	0.70	0.50	0.50
2.5	1.5	1.57	1.57	1.00	1.00
3	2	2.79	2.79	1.60	1.60
3.5	2.5	4.35	4.36	2.29	2.29
4	3	6.28	6.27	3.04	3.03
4.5	3.5	8.54	8.54	3.84	3.83
5	4	11.15	11.15	4.68	4.68

The readings are the flat level of each curve, read from the key’s plot images with their axis ticks for scale (about ±0.02 mA). Only the combinations $\beta = \mu C_{ox}W/L$ and $\mathcal{E}_{crit}L = v_{sat}L/\mu$ can be fitted from curves; the device’s own $\mu$μ, $W$W, $L$ and $t_{ox}$ are not in the key.

Check. The fit used only the top curve, so it has to reproduce the others. With $\beta = 1.39\,\mathrm{mA/V^2}$ and $\mathcal{E}_{crit}L = 2.38\,\mathrm{V}$ the model gives 0.15, 0.50, 1.60 and 4.68 mA at $U = 0.5$0.5, 1, 2 and 4 V, within 0.01 mA of every reading (the table’s last column), and $V_{DSAT} = 2U/(1 + s) = 2.59\,\mathrm{V}$ at the top: the knee in the plot.

ℰ_crit·L = v_satL/μ

2.38 V

at U = 4 V: 2U/(ℰ_critL)

3.36

(s − 1)/(s + 1), share of the linear limit

35%

I_DSAT(U)/I_DSAT(U/2): 4 square, 2 linear

2.92

velocity-saturated ÷ square law at U

42%

Lines: Chapter 4's models with β = μC_oxW/L = 1.39 mA/V² and the slider's ℰ_critL. Dots: readings from the key's two plots. The linear limit is C_oxWv_satU = β·ℰ_critL·U. Slide ℰ_critL down (a shorter channel) and the curve straightens toward the limit; slide it up and it rejoins the square law.

What to notice.

• The dots sit on the lines: the key’s curves are Chapter 4’s models.
• Slide $\mathcal{E}_{crit}L$ down to about 0.5 V (a channel five times shorter): the doubling ratio falls toward 2 and the curve hugs the linear limit. Slide it up past 20 V: the curve rejoins the square law.
• Even at the plotted $\mathcal{E}_{crit}L$ the tops look evenly spaced above $U = 2\,\mathrm{V}$ (steps of 0.69, 0.75, 0.80, 0.84 mA). They still grow; that is the partly saturated regime.

Answer: Velocity saturation lowers the saturated current (to 42% at the top curve) and makes the curves flatten at a smaller $V_{SD}$ (2.6 V instead of 4 V); the tops grow more slowly than the square of the overdrive, tending toward a straight line.

Remember. Double the overdrive and compare the tops: 4 times is the square law, 2 times the linear limit, anything between is partly saturated. Evenly spaced tops at the top of a family don’t yet make it linear.

The answer key differs

Its explanation makes two points. (1), that velocity saturation’s effect grows with the overdrive and lowers the current for a given overdrive, is right. (2) says the saturated current “only goes up linearly with $V_{GS} - |V_T|$∣VT​∣” with velocity saturation. That is the full-saturation limit of Chapter 4, Section 7, not what its own plot shows: doubling the overdrive from 2 to 4 V gives 2.9 times the current, and the top curve reaches only 35% of the linear limit. Chapter 4 lists this as a common mistake: $(s - 1)/(s + 1)$ approaches 1 slowly.

HW1-1b: the junction capacitance of an internal node

HW1-1b, p2 (10 points; from the key). The node C between two series PFETs is a $p^+$ diffusion ($N_A = 10^{18}\,\mathrm{cm^{-3}}$NA​=1018cm−3) of area $30\,\mu\mathrm{m}^2$ in an n well ($N_D = 8\times10^{16}\,\mathrm{cm^{-3}}$ND​=1016cm−3) at 5 V, with $|V_{Tp}| = 1\,\mathrm{V}$1V. Find the range of its junction capacitance.

The homework’s figure for this part is not in the key; the key’s working gives the doping, the area and the node’s range.

Hint

The junction’s capacitance depends on the voltage across it. Over what range can node C move, and what voltage is on the other side of the junction?

What it asks. Node C is a $p^+$ diffusion inside an n well, so it forms a pn junction with the well, and that junction is a capacitor on the node. Its value is not one number: it depends on the voltage across the junction. “The range” asks for its smallest and largest values over all the voltages the node can reach.

The idea. A reverse-biased junction is a parallel-plate capacitor: its plates are the two edges of the depletion region, with silicon between them, so $C_j = \kappa_s\varepsilon_0/W$ per area (Chapter 3, Section 5). The depletion width grows with the reverse bias $V_R$ (Chapter 3, Section 3):

$$W = \sqrt{\frac{2\kappa_s\varepsilon_0(V_{bi} + V_R)}{qN}}$$

Here $V_{bi} = (kT/q)\ln(N_AN_D/n_i^2)$ is the junction’s built-in voltage and $N = N_AN_D/(N_A + N_D)$ its reduced doping (Chapter 3, Section 2). These hold at zero or reverse bias. $N$ is always below the lighter doping, and close to it when the other side is much heavier, so the lightly doped side, here the well, sets the width, and most of the depletion region lies in it. A larger reverse bias widens the plates’ spacing and lowers the capacitance. So the question comes down to the node’s voltage range: its two ends give the two ends of the capacitance range.

Capacitance range

1. The node’s range, because it sets the reverse bias. C can be charged all the way to 5 V, because a PFET passes a high fully: its source is then the 5 V side, and its $V_{SG}$ doesn’t shrink as C rises. Discharged through the lower PFET, C stops where that PFET turns itself off, one threshold above its gate: with the gate at 0 V (the key’s range implies it; the figure is missing), at $V_G + |V_{Tp}| = 0 + 1 = 1\,\mathrm{V}$ (Chapter 10, Section 5; problem 2 works this out). So C lies between 1 V and 5 V.
2. The reverse bias, because the voltage across the junction, not the node’s own voltage, sets the width. The $p^+$ node sits in an n well at 5 V, so $V_R = 5 - V_C$VC​: from 0 V (node at 5 V) to 4 V (node at 1 V). The node never rises above the well, so the junction is never forward-biased and the formulas hold over the whole range (Chapter 5, Section 8).
3. Reduced doping and built-in voltage, the two junction numbers the width needs (Chapter 3, Sections 2–3): $N = \dfrac{N_AN_D}{N_A + N_D} = 7.41\times10^{16}\,\mathrm{cm^{-3}}$1016cm−3, and $V_{bi} = 0.026\ln\dfrac{10^{18} \times 8\times10^{16}}{(1.1\times10^{10})^2} = 0.887\,\mathrm{V}$0.887V.
4. Zero bias first, because the narrowest depletion region gives the largest capacitance (Chapter 3, Section 3): $W = \sqrt{\dfrac{2\kappa_s\varepsilon_0 V_{bi}}{qN}} = 124\,\mathrm{nm}$124nm, 93% of it in the lighter well.
5. The largest capacitance, because a parallel-plate capacitor per area is the permittivity divided by the plate spacing, and the spacing here is the depletion width: $C_j = \kappa_s\varepsilon_0/W = 0.832\,\mathrm{fF/\mu m^2}$ (Chapter 3, Section 5). Times $30\,\mu\mathrm{m}^2$30μm2: $C_{max} = 25.0\,\mathrm{fF}$25.0fF.
6. Full reverse bias, $V_R = 4\,\mathrm{V}$4V, because the widest region gives the smallest capacitance. The width grows as $\sqrt{V_{bi} + V_R}$Vbi​+VR​​: $W = 124\,\mathrm{nm} \times \sqrt{4.887/0.887} = 292\,\mathrm{nm}$292nm, $C_j = 0.355\,\mathrm{fF/\mu m^2}$0.355fF/μm2, $C_{min} = 10.6\,\mathrm{fF}$10.6fF.

Check. The ratio of the two ends needs none of the constants. $C_j$ goes as $1/W$1/W, and $W$ as $\sqrt{V_{bi} + V_R}$Vbi​+VR​​, so $C_{min}/C_{max} = \sqrt{0.887/4.887} = 0.426$0.426. The two values give $10.6/25.0 = 0.424$0.424, the same to rounding. ✓

Answer: from 10.6 fF (node at 1 V) to 25.0 fF (node at 5 V). The capacitance falls as the node falls, because the reverse bias grows (Chapter 5, Section 5: the nonlinear capacitance the lecture warns about).

Remember. A junction capacitance is a range, not a value. Turn the node’s voltage range into a reverse-bias range against its well or substrate, and evaluate $C_j = \kappa_s\varepsilon_0/W$ at both ends: largest at the smallest reverse bias.

The answer key differs

It gives $C_{max} = 25.89\,\mathrm{fF}$ and $C_{min} = 10.7\,\mathrm{fF}$10.7fF. It rounds the widths to two digits before dividing (120 nm for 124 nm, 290 nm for 292 nm), which puts $C_{max}$ 3.7% high. Its method and its range of bias are right.

2. HW1-2: a capacitor discharged through transistors

HW1-2, pp3–4 (30 points; from the key). A capacitor charged to 5 V discharges through the circuits below ($|V_T| = 1\,\mathrm{V}$∣VT​∣=1V). For each, find the capacitor’s final voltage and the region each transistor passes through. For (c), the capacitance of node $V_X$ is much smaller than the load capacitor.

The rule for all three. This is the threshold rule of page M5’s pass-transistor section, applied to a capacitor instead of a logic node. What this problem adds is the region of each device along the way. Three moves, each for a reason:

1. Find each transistor’s source, the terminal nearer its own rail: the lower one for an NFET, the higher one for a PFET. A MOSFET is symmetric, so the voltages, not the drawing, decide which terminal is the source, and $V_{GS}$ (or $V_{SG}$VSG​) is measured from it.
2. Ask when $V_{GS}$ (or $V_{SG}$VSG​) falls to the threshold, because in the threshold model a device conducts only while $V_{GS} > V_T$VT​. When the source is the node that moves, the moving node changes $V_{GS}$ itself: the device turns itself off at its threshold, and the node stops there (Chapter 10, Section 5). A source on a rail never moves, so then $V_{GS}$ never changes.
3. Name the region from $V_{DS}$VDS​, because the question asks for it. A conducting device is saturated while $V_{DS} \ge V_{GS} - V_T$VT​, because the channel is then pinched off at its drain end, and in triode below that (Chapter 4, Section 4). For a PFET read $V_{SD}$VSD​, $V_{SG}$ and $|V_T|$∣VT​∣.

HW1-2a: an NFET with its gate grounded

HW1-2a, p3 (the key’s sketch).

Hint

Which of the NFET’s terminals is its source, and can the capacitor change that terminal’s voltage?

What it asks. An NFET with its gate and source grounded and its drain on the capacitor’s charged top. Does the capacitor discharge through it, and how far?

The idea. Whether an NFET conducts depends on $V_{GS}$ alone, not on its drain. Its source is its lower terminal, here the grounded one, and its gate is grounded too, so $V_{GS} = 0$0. The capacitor sits on the drain, so nothing it does can move $V_{GS}$VGS​: the rule’s second move answers the question at once.

1. Find the source, because $V_{GS}$ is measured from it. The NFET’s terminals are at 0 V and 5 V; the lower one, ground, is the source. Its gate is at 0 V: $V_{GS} = 0 < V_T = 1\,\mathrm{V}$1V.
2. Ask whether $V_{GS}$ can change, because a discharging node would move a source that sat on it. The source is on the ground rail and the capacitor is on the drain, so nothing the capacitor does changes $V_{GS}$VGS​. The device never turns on, and with no current the capacitor keeps its charge.

Check. The opposite case shows the gate is what holds the charge. With the gate at 5 V, $V_{GS}$ would be 5 V, the source would still be at ground, and the NFET would stay on until the capacitor reached 0 V: an NFET passes a 0 fully. With its gate at 0 V it passes nothing.

Answer: $V_C(\infty) = 5\,\mathrm{V}$5V; the NFET is in cut-off throughout. In the threshold model the capacitor holds; really, subthreshold leakage (Chapter 4, Section 11) would bleed it slowly added.

Remember. Ask first whether the moving node is the source. If the source sits on a rail, $V_{GS}$ is fixed, and the device is on or off for good.

The answer key agrees

HW1-2b: a PFET with its gate at 3 V

HW1-2b, p3 (the key’s sketch).

Hint

Which terminal is the PFET’s source, and what happens to $V_{SG}$ as the capacitor discharges?

What it asks. A PFET with its gate held at 3 V, between the charged capacitor and ground. How far does the capacitor discharge, and in which regions is the PFET on the way?

The idea. Now the moving node is the source. A PFET’s source is its higher terminal, the capacitor, so $V_{SG} = V_C - 3$ falls as the capacitor discharges. The PFET turns itself off when $V_{SG}$ reaches $|V_{Tp}|$∣VTp​∣, at $V_C = V_G + |V_{Tp}|$∣VTp​∣: M5’s rule that a PFET passes a low only down to one threshold above its gate. For the region, compare $V_{SD} = V_C$ with the overdrive $V_{SG} - |V_{Tp}| = V_C - 4$4.

1. Find the source and the drain, because both voltages are measured from the source. The higher terminal, the capacitor, is the source: $V_{SG} = V_C - 3$3. Its drain is at ground, so $V_{SD} = V_C$VC​.
2. The start, because the region is decided at each moment, beginning with the first. $V_{SG} = 2\,\mathrm{V} > 1\,\mathrm{V}$1V: on, with 1 V of overdrive. $V_{SD} = 5\,\mathrm{V} \ge 1\,\mathrm{V}$1V: saturation.
3. On the way down, because $V_{SD}$ and the overdrive both fall as the capacitor discharges. $V_{SD} = V_C$ stays above the overdrive $V_C - 4$4, so the device stays saturated all the way.
4. Where it stops, because the falling source is turning the device off. It stops when $V_{SG} = |V_T|$∣VT​∣: $V_C - 3 = 1$1, so $V_C = 4\,\mathrm{V}$4V. There it is in cut-off.

Check. At every moment $V_{SD}$ exceeds the overdrive by $V_C - (V_C - 4) = 4\,\mathrm{V}$4V, so step 3 holds with room to spare: with its drain at ground and its gate above ground, this PFET is saturated whenever it conducts. And the end point is one threshold above the gate, $3 + 1 = 4\,\mathrm{V}$4V, as the rule says.

Answer: $V_C(\infty) = 4\,\mathrm{V}$ (gate voltage plus $|V_{Tp}|$∣VTp​∣); saturation, then cut-off.

Remember. A PFET that discharges a node stops it at $V_G + |V_{Tp}|$∣VTp​∣, one threshold above its gate, never at ground. Chapter 10 has a check on the same structure with other numbers (Section 5).

The answer key agrees

HW1-2c: two PFETs in series

HW1-2c, p3 (the key’s sketch and waveforms).

Hint

Each PFET has its own source and its own gate. Taken alone, where does each one stop?

What it asks. Two PFETs in series between the capacitor and ground: M1’s gate at 2 V, M2’s at 0 V, and a small node $V_X$ between them. Where do the capacitor and $V_X$ end, and through which regions does each device pass? “Much smaller than the load capacitor” decides how $V_X$ behaves: it settles almost at once, while the capacitor discharges slowly.

The idea. The rule gives the end points; Kirchhoff’s current law gives the path.

• The end points. Each device stops at its own threshold, measured from its own source and its own gate: M1 when $V_C = 2 + 1$1, M2 when $V_X = 0 + 1$1. A series pair does not lose a threshold per device.
• The path. The regions need $V_X$VX​, and $V_X$ comes from KCL. A node with almost no capacitance can’t store charge, so the current in through M1 must equal the current out through M2. With both saturated and equal (the key’s implicit assumption), equal currents mean equal $V_{SG}$VSG​, because a saturated device’s current depends only on its overdrive (Chapter 4, Section 4).

Two PFETs in series

1. Where each stops, because that needs only the gates and the thresholds. M1’s source is the capacitor: it conducts while $V_{SG1} = V_C - 2 > 1$1, so the capacitor can fall only to $V_C = 3\,\mathrm{V}$3V. M2’s source is $V_X$VX​: it conducts while $V_X - 0 > 1$1, so $V_X$ can fall only to 1 V. Each device stops at its own threshold.
2. The start, because the regions are read from the voltages at each moment. The key assumes $V_X = 0$0. Then M1 has $V_{SG1} = 3\,\mathrm{V}$ and $V_{SD1} = 5\,\mathrm{V}$5V: saturated. M2 has $V_{SG2} = 0$0: off.
3. $V_X$ charges at once, because M1’s current has nowhere to go but the small node capacitance at $V_X$VX​. So $V_X$ rises almost instantly, until M2 carries the same current (KCL).
4. Equal currents, to find where $V_X$ settles. With equal devices (the key’s implicit assumption) and both saturated, equal currents need equal $V_{SG}$VSG​: $V_X - 0 = V_C - 2$2, so $V_X = 3\,\mathrm{V}$3V. Then M1 has $V_{SD1} = 2\,\mathrm{V}$2V, exactly its overdrive: on the edge of saturation. M2 has $V_{SD2} = 3\,\mathrm{V}$ against 2 V of overdrive: saturated.
5. The discharge, because the regions must still hold as both voltages fall. As $V_C$ falls, $V_X = V_C - 2$ follows, by the equal-$V_{SG}$ condition of step 4. M1: $V_{SD1} = 2\,\mathrm{V} \ge V_C - 3$3. M2: $V_{SD2} = V_C - 2 > V_C - 3$3. Both stay saturated.
6. The end, because the equal-$V_{SG}$ condition brings both devices to their thresholds at the same moment. Both stop together: $V_C = 3\,\mathrm{V}$3V, $V_X = 1\,\mathrm{V}$1V, both in cut-off.

Check. Two routes agree. Step 1 found the end points from the gate voltages alone, with no currents; steps 3–6 followed the currents and ended at the same 3 V and 1 V. They must agree, because the KCL path can only stop where some device has reached its threshold.

Answer: $V_C(\infty) = 3\,\mathrm{V}$ and $V_X(\infty) = 1\,\mathrm{V}$1V. M1: saturation, the triode/saturation edge, saturation, cut-off. M2: cut-off, saturation, cut-off.

The final voltages don’t depend on the sizes; the path does. added If M2 were weaker than M1, the equal-current $V_X$ would sit higher, above 3 V at the start, and M1 would begin in triode. The end points, 3 V and 1 V, are set by the gate voltages and the thresholds alone. That is the habit the midterms test: “where does it stop?” needs only $V_G \pm |V_T|$ (M5, MT21-1b asks it of an NFET passing a 1).

Remember. In a series chain each device stops at its own threshold, from its own gate. The regions on the way need one more tool: KCL at the node between the devices.

Check yourself In circuit (c), M1's gate is moved from 2 V to 0 V. Where do V_C and V_X end?

M1 now conducts while $V_C - 0 > 1$1, so the capacitor falls to 1 V; M2 stops $V_X$ at 1 V. Both end at 1 V: a PFET with its gate at 0 V passes a low only down to $|V_{Tp}|$∣VTp​∣, and a second one in series, also with its gate at 0 V, adds no further drop (one threshold, not two).

The answer key agrees

Its waveforms show the same path: $V_C$ falls from 5 V to 3 V, while $V_X$ jumps to 3 V and decays to 1 V. It takes M1 and M2 to be equal without saying so (step 4).

HW1-2d: the same with a bipolar transistor

HW1-2d (p4) discharges the capacitor through an NFET whose source drives the base of an NPN transistor. It is out of scope: no lecture before the midterm cutoff teaches a BJT’s regions or its $V_{BE,on}$VBE,on​; Lecture 3 only contrasts the bipolar device with the MOSFET’s symmetry (Chapter 3, Section 6).

3. HW1-3: subthreshold current at zero gate voltage

HW1-3, p5: the key’s expression (its operator reads as “+”).

HW1-3, p5 (10 points; from the key). A transistor carries $100\,\mu\mathrm{A}$ at $V_{GS} = V_T = 0.5\,\mathrm{V}$0.5V, with a 60 mV/decade subthreshold slope. Find $I_D$ at $V_{GS} = 0$0.

Hint

How far below its threshold is the gate at $V_{GS} = 0$0, and what does the slope say that costs in current?

What it asks. The current of the transistor when it is off, at $V_{GS} = 0$0, given its current at threshold (100 µA at 0.5 V) and its subthreshold slope (60 mV per decade). Nothing else about the device is needed.

The idea. This is the decade count of page M3’s device short-answer section, in its plainest form: one device at one temperature. A MOSFET doesn’t shut off at its threshold. Below $V_T$ its current falls by one decade, a factor of 10, for every $S$ millivolts that the gate is below threshold (Chapter 4, Section 11):

$$I_D = I(V_T)\times10^{(V_{GS} - V_T)/S}\qquad(V_{GS} < V_T).$$

$S$ is the subthreshold slope, here 60 mV/decade. The current at threshold multiplies the exponential: each decade divides it by 10. So the whole answer is a count of decades.

1. Write the law, because the question gives exactly its inputs, the current at threshold and the slope (Chapter 4, Section 11): $I_D = I(V_T)\times10^{(V_{GS} - V_T)/S}$10(VGS​−VT​)/S.
2. Count the decades, because each one divides the current by 10. From 0.5 V down to 0: $500/60 = 8.33$ decades.
3. Turn them into a factor, because the law needs the factor by which the current falls, not the count: $10^{-8.33} = 4.64\times10^{-9}$10−9.
4. Multiply the current at threshold, since the law is a product: $I_D = 100\,\mu\mathrm{A} \times 4.64\times10^{-9} = 4.64\times10^{-13}\,\mathrm{A} = 0.46\,\mathrm{pA}$0.46pA.

Check. The size, from the count alone: 8.33 decades lies between 8 and 9, so the current must lie between $100\,\mu\mathrm{A}/10^8 = 1\,\mathrm{pA}$ and $100\,\mu\mathrm{A}/10^9 = 0.1\,\mathrm{pA}$0.1pA. ✓ And the slope is a sensible one: 60 mV/decade is the ideal room-temperature slope, $(kT/q)\ln 10 = 59.5\,\mathrm{mV}$59.5mV.

Answer: $I_D = 0.46\,\mathrm{pA}$0.46pA.

Remember. The off current is the current at threshold, divided by 10 once for every $S$ millivolts below threshold. It is the same move as M3’s MT17-1c (16.7 decades at 300 K, 12.5 at 400 K) and the leakage step of MT24-2b and MT23-1b (2.22 decades: about 60 nA/µm).

The answer key agrees

Its boxed answer is 0.46 pA. Its written expression joins $100\times10^{-6}$ and $10^{(V_{gs} - 0.5)/0.06}$ with what reads as a “+”; it must be a product (a sum would give 100 µA at $V_{GS} = 0$0), and the boxed 0.46 pA is the product.

4. HW1-4: saturation velocity and width from I–V curves

HW1-4, p5 (20 points; from the key). Figures 1 (NMOS) and 2 (PMOS) show I–V curves of devices $1\,\mu\mathrm{m}$ wide with $t_{ox} = 5.8\,\mathrm{nm}$5.8nm. (a) Are they velocity-saturated? Find the saturation velocity of electrons and of holes. (b) Find the width of an NMOS whose saturated current steps by 1.8 mA for each 0.5 V of $V_{GS}$VGS​.

The two figures are not in the key; its working gives the readings: the NMOS tops step by about 160 µA (its prose says 170 µA) and the PMOS tops by about 80 µA, per 0.5 V of gate voltage. Part (b)‘s wording is reconstructed from the key’s calculation.

HW1-4a: the saturation velocity of electrons and holes

Hint

What does the spacing of the tops tell you about how the current grows with $V_{GS}$VGS​, and which unknowns drop out of the difference between two tops?

What it asks. Two families of curves, NMOS and PMOS, both 1 µm wide with a 5.8 nm oxide. Decide whether they are velocity-saturated, then extract $v_{sat}$ for electrons (the NMOS) and for holes (the PMOS). Only the oxide and the width are given: no $V_T$VT​, no $L$L, no mobility. That decides the method: it can use only the spacing of the tops.

The idea. This is the spacing sign of page H2, Section 2; what is new is turning the spacing into a velocity. Evenly spaced tops mean the saturated current is linear in the overdrive: the fully velocity-saturated limit of Chapter 4, Section 7,

$$I_{DSAT} = C_{ox}Wv_{sat}(V_{GS} - V_T),$$

which holds when $(V_{GS} - V_T)/L \gg \mathcal{E}_{crit}/2$Ecrit​/2, in short channels. It is the channel’s charge per area, $C_{ox}(V_{GS} - V_T)$VT​), times the width, moving at $v_{sat}$vsat​. Take the difference between two tops: $V_T$ cancels and leaves $\Delta I = C_{ox}Wv_{sat}\,\Delta V_{GS}$Cox​Wvsat​ΔVGS​, in which every factor is known except $v_{sat}$vsat​. (The square law would give steps that grow: starting at threshold, equal steps of $V_{GS}$ give currents in the ratio 1 : 4 : 9 : 16, so steps in the ratio 1 : 3 : 5 : 7.)

1. Decide the model first, because the formula depends on it. The key reads the tops as evenly spaced: current linear in the overdrive, not its square. That is the signature of velocity saturation (Chapter 4, Section 7).
2. Take the difference of two tops, because $V_T$ is not given and the difference removes it. In the limit, $I_{DSAT} = C_{ox}Wv_{sat}(V_{GS} - V_T)$VT​), so a step of $\Delta V_{GS}$ adds $\Delta I = C_{ox}Wv_{sat}\,\Delta V_{GS}$Cox​Wvsat​ΔVGS​, whatever $V_T$ is.
3. The oxide capacitance, the one factor still to compute: $C_{ox} = \varepsilon_{ox}/t_{ox} = 3.45\times10^{-13}/5.8\times10^{-7} = 5.95\times10^{-7}\,\mathrm{F/cm^2}$10−7F/cm2.
4. Electrons, from the NMOS steps (160 µA per 0.5 V, a reading from the key’s figures): $v_{sat} = \dfrac{\Delta I}{WC_{ox}\Delta V_{GS}} = \dfrac{160\times10^{-6}}{10^{-4} \times 5.95\times10^{-7} \times 0.5} = 5.38\times10^6\,\mathrm{cm/s}$ (with 170 µA, $5.72\times10^6$106).
5. Holes, from the PMOS steps (80 µA), with the same denominator: $\dfrac{80\times10^{-6}}{2.975\times10^{-11}} = 2.69\times10^6\,\mathrm{cm/s}$106cm/s, half the electrons’ value.

Check. The units: $\mathrm{A}/(\mathrm{cm} \times \mathrm{F/cm^2} \times \mathrm{V}) = \mathrm{A\cdot cm}/(\mathrm{F\cdot V})$A⋅cm/(F⋅V), and a farad times a volt is a coulomb, an ampere a coulomb per second, so the result is in cm/s. ✓ And the ratio: the two devices share $C_{ox}$Cox​, $W$ and $\Delta V_{GS}$ΔVGS​, so half the current per step must mean half the velocity.

Answer: $v_{sat} \approx 5.4\times10^6\,\mathrm{cm/s}$ for electrons and $2.7\times10^6\,\mathrm{cm/s}$ for holes (readings from the key’s figures).

Why these come out below silicon’s $10^7\,\mathrm{cm/s}$107cm/s. added The method assumes the full limit. A partly saturated device’s tops grow by less than $C_{ox}Wv_{sat}\,\Delta V_{GS}$ per step, so the fit returns a smaller, effective $v_{sat}$vsat​. HW1-1a shows it: its top step, 3.5 to 4 V, is about 1.7 mA/V, only half of that device’s limit slope $\beta\,\mathcal{E}_{crit}L = 3.32\,\mathrm{mA/V}$3.32mA/V. Read an extracted $v_{sat}$ as a lower bound.

Remember. With evenly spaced tops, divide the current step by $C_{ox}W\,\Delta V_{GS}$ and you have $v_{sat}$vsat​, without knowing $V_T$VT​. Unless the device is fully saturated, the result is a lower bound.

The answer key agrees

Its prose says 170 µA, but its arithmetic and its boxed answer use 160 µA (170 µA would give $5.72\times10^6\,\mathrm{cm/s}$106cm/s).

HW1-4b: the width

Hint

Which factors in $\Delta I = C_{ox}Wv_{sat}\,\Delta V_{GS}$ are the same as in part (a)?

What it asks. An NMOS on the same process whose tops step by 1.8 mA per 0.5 V, instead of (a)‘s 160 µA. How wide is it?

The idea. The step formula of (a), solved for the width: $W = \Delta I/(C_{ox}v_{sat}\,\Delta V_{GS})$ΔI/(Cox​vsat​ΔVGS​). The same oxide and the same carriers (electrons) give the same $C_{ox}$ and $v_{sat}$ as in (a). In the velocity-saturated limit the current is proportional to the width and doesn’t depend on $L$ (Chapter 4, Section 7), so the width is the only thing that can make the step larger.

1. Solve the step formula for W, because the oxide, the carriers and $\Delta V_{GS}$ are all as in (a): $W = \dfrac{\Delta I}{C_{ox}v_{sat}\,\Delta V_{GS}}$Cox​vsat​ΔVGS​ΔI​.
2. Put in (a)‘s values, with its rounded $v_{sat}$vsat​: $W = \dfrac{1.8\times10^{-3}}{5.95\times10^{-7} \times 5.4\times10^6 \times 0.5} = 1.12\times10^{-3}\,\mathrm{cm} = 11.2\,\mu\mathrm{m}$11.2μm.

Check. A second route needs no constants. The current per step scales with $W$W, so $W = (1.8\,\mathrm{mA}/0.16\,\mathrm{mA}) \times 1\,\mu\mathrm{m} = 11.25\,\mu\mathrm{m}$11.25μm, the same to the rounding of $v_{sat}$ (10.6 µm with the 170 µA reading).

Answer: $W \approx 11\,\mu\mathrm{m}$11μm.

Remember. In the velocity-saturated limit the current per volt of overdrive is proportional to the width alone, so a width is a ratio of current steps times a known width.

The answer key differs

It writes "$= 0.001\,\mathrm{cm} = 10\,\mu\mathrm{m}$". The quotient is $1.12\times10^{-3}$ cm; rounding it to one digit makes the width 11% small.

5. HW1-5: scaling with a field factor

HW1-5, p6: the key’s first line, depletion width.

HW1-5, pp6–7 (20 points; from the key). Dimensions scale by $1/k$1/k, voltages by $\alpha/k$ and doping by $\alpha k$αk, so fields grow by $\alpha$α. How do the depletion width, capacitance, inversion charge, drift velocity, current, delay, power, power-delay product, circuit density and power density scale, for a long-channel and for a velocity-saturated device?

Hint

Write each quantity as a product of ones you have already scaled. Which ones need nothing but lengths, voltages and doping?

What it asks. A scaling rule that is not Chapter 4’s: lengths shrink by $1/k$ but voltages only by $\alpha/k$α/k, so every field grows by $\alpha$α, and the doping rises by $\alpha k$αk. Find how ten quantities scale, twice: for a long-channel device and for a velocity-saturated one. The second column is the point of the problem, because the two devices’ carriers respond differently to a larger field.

The idea. Chapter 4, Section 10 does this for constant-field scaling, $\alpha = 1$1. The homework lets the field grow by $\alpha$ added: voltages fall more slowly than lengths, as they did in practice once $V_T$ stopped scaling (Section 11). The method is the lecture’s: write each quantity as a product of quantities already scaled, in order, so that every line uses only the lines above it. The relations are Chapter 4’s:

• the depletion width, $W_d \sim \sqrt{V/N}$ (Chapter 3’s formula; the homework assumes that $V_{bi}$ scales with the other voltages, which Section 11 says it doesn’t in practice);
• a device’s capacitance, $C \sim \varepsilon A/t_{ox}$εA/tox​: its area times $C_{ox}$Cox​;
• the inversion charge per area, $Q_i \sim (\varepsilon/t_{ox})V$(ε/tox​)V;
• the current, $I \sim Q_iWv$Qi​Wv: charge per area, times width, times drift velocity;
• the delay, $CV/I$CV/I: the time the current takes to move the charge $CV$CV;
• the power, $P \sim IV$IV.

Only the drift velocity differs between the two devices. In a long channel $v = \mu\mathcal{E}$ grows with the field; a velocity-saturated carrier already moves at $v_{sat}$vsat​, which doesn’t scale.

Quantity by quantity

1. Depletion width first, because it needs only a voltage and a doping: $W_d \sim \sqrt{V/N} \to \sqrt{(\alpha/k)\cdot 1/(\alpha k)} = 1/k$1/k. The extra doping exactly offsets the extra voltage.
2. Capacitance, because it needs only lengths: $C \sim \varepsilon A/t_{ox} \to (1/k^2)/(1/k) = 1/k$1/k.
3. Inversion charge per area, because the current is built on it: $Q_i \sim (\varepsilon/t_{ox})V \to (\alpha/k)/(1/k) = \alpha$α. The voltage falls more slowly than the oxide thins, so each area of channel holds more charge.
4. Drift velocity, the one line where the devices differ: long-channel $v = \mu\mathcal{E} \to \alpha$α; velocity-saturated $v = v_{sat} \to 1$ (it doesn’t scale).
5. Current, charge per area times width times velocity, $I \sim Q_iWv$Qi​Wv: long-channel $\alpha \cdot (1/k) \cdot \alpha = \alpha^2/k$α2/k; saturated $\alpha \cdot (1/k) = \alpha/k$α/k.
6. Delay, the time to move the charge $CV$ at the current $I$I: long-channel $\dfrac{(1/k)(\alpha/k)}{\alpha^2/k} = \dfrac{1}{\alpha k}$αk1​; saturated $\dfrac{(1/k)(\alpha/k)}{\alpha/k} = \dfrac1k$k1​.
7. Power $IV$IV, current times voltage: long-channel $\alpha^3/k^2$α3/k2; saturated $\alpha^2/k^2$α2/k2.
8. Power × delay, from lines 6 and 7: long-channel $\dfrac{\alpha^3}{k^2}\cdot\dfrac{1}{\alpha k} = \dfrac{\alpha^2}{k^3}$k3α2​; saturated $\dfrac{\alpha^2}{k^2}\cdot\dfrac1k = \dfrac{\alpha^2}{k^3}$k3α2​. The same.
9. Circuit density $1/A$1/A, because each device’s area shrinks as $1/k^2$1/k2: $k^2$ for both. Power density $P/A$P/A, the power per device times the devices per area: long-channel $\alpha^3$α3, saturated $\alpha^2$α2.

Quantity	Long-channel	Velocity-saturated	At $\alpha = 1$ (Chapter 4)
$W_d$Wd​, $C$	$1/k$	$1/k$	$1/\kappa$
$Q_i$ (per area)	$\alpha$	$\alpha$	1
$v_{drift}$	$\alpha$	1	1
current	$\alpha^2/k$	$\alpha/k$	$1/\kappa$
delay	$1/(\alpha k)$	$1/k$	$1/\kappa$
power	$\alpha^3/k^2$	$\alpha^2/k^2$	$1/\kappa^2$
power × delay	$\alpha^2/k^3$	$\alpha^2/k^3$	$1/\kappa^3$
density	$k^2$	$k^2$	$\kappa^2$
power density	$\alpha^3$	$\alpha^2$	1

Check. Two of them. At $\alpha = 1$ both columns must collapse to Chapter 4’s constant-field table, and they do (the last column). And power × delay is the energy of one switching event, $CV^2$ (Chapter 6, Section 6), which scales directly as $(1/k)(\alpha/k)^2 = \alpha^2/k^3$ whatever the carriers do: the same entry as step 8, for both devices. ✓

Answers: as in the table.

What it means. added At $\alpha = 1$ both columns collapse to Chapter 4’s table: at constant field $\mu\mathcal{E}$ doesn’t change either, so velocity saturation makes no difference. Raise the field and they part. A long-channel device gets faster by the extra $1/\alpha$1/α; a velocity-saturated one does not (its carriers are already at $v_{sat}$vsat​), yet its power density still grows as $\alpha^2$α2. For example, $k = 1.4$ and $\alpha = 1.2$1.2: the delay falls to 0.595 (long) or 0.714 (saturated), and the power density rises 1.73 or 1.44 times. More field buys heat, not speed, which is why the supply had to keep falling.

Remember. Scale a quantity by writing it as a product of ones already scaled, in the lecture’s order. The field factor reaches the delay only through the drift velocity, so velocity saturation decides whether more field buys speed.

The answer key agrees

Formulas this homework uses

• Square law $I_{DSAT} = \tfrac12\mu C_{ox}\tfrac{W}{L}(V_{GS} - V_T)^2$VT​)2, flat past $V_{DSAT} = V_{GS} - V_T$VT​. Velocity-saturated $I_{DSAT} = C_{ox}Wv_{sat}(V_{GS} - V_T)\tfrac{s - 1}{s + 1}$VT​)s+1s−1​, $s = \sqrt{1 + 2(V_{GS} - V_T)/(\mathcal{E}_{crit}L)}$1+2(VGS​−VT​)/(Ecrit​L)​, $V_{DSAT} = 2(V_{GS} - V_T)/(1 + s)$s); the limit $C_{ox}Wv_{sat}(V_{GS} - V_T)$ (Chapter 4, Sections 4–7).
• Doubling test: doubling the overdrive multiplies $I_{DSAT}$ by 4 (square law) down to 2 (fully saturated).
• Junction: $V_{bi} = \tfrac{kT}{q}\ln\tfrac{N_AN_D}{n_i^2}$qkT​lnni2​NA​ND​​, $W = \sqrt{2\kappa_s\varepsilon_0(V_{bi} + V_R)/(qN)}$2κs​ε0​(Vbi​+VR​)/(qN)​, $N = N_AN_D/(N_A + N_D)$ND​), $C_j = \kappa_s\varepsilon_0/W$ (Chapter 3, Sections 2–5).
• Where a device stops: an NFET when $V_{GS} = V_T$ (it passes $V_G - V_T$ at most), a PFET when $V_{SG} = |V_T|$ (it passes $V_G + |V_T|$ at least) (Chapter 10, Section 5).
• Subthreshold: $I = I(V_T)\times10^{(V_{GS} - V_T)/S}$10(VGS​−VT​)/S, $S = 60\,\mathrm{mV/decade}$ ideal at 300 K (Chapter 4, Section 11).
• Scaling: $W_d \sim \sqrt{V/N}$V/N​, $C \sim \varepsilon A/t_{ox}$εA/tox​, $Q_i \sim (\varepsilon/t_{ox})V$(ε/tox​)V, $I \sim Q_iWv$Qi​Wv, delay $\sim CV/I$CV/I, $P \sim IV$ (Chapter 4, Section 10).

What this means for the midterm

Device short answers (MT17-1b–c, MT21-2; see M3, Section 9).

• Subthreshold decades (HW1-3) is in three of the four past midterms: MT17-1c directly, and inside the chain’s leakage in MT24-2b and MT23-1b. Trap: nA, not pA; and at another temperature the slope scales with $T$T. About 2 minutes.
• Junctions and wells (HW1-1b): MT17-1b’s grounded well is the same picture, a $p^+$ diffusion in an n well, asked the other way round: forward bias instead of reverse. Trap: name both junctions in the well. About 3 minutes.

Pass-transistor levels (every midterm since 2021; see M5).

• “Where does it stop?” (HW1-2) is the core of MT21-1b and MT23-2c: an NFET stops a high at $V_G - V_T$VT​, a PFET stops a low at $V_G + |V_T|$∣VT​∣. Trap: one threshold per series device (wrong), unless a degraded node drives a gate (MT23-2c’s second drop). About 1–2 minutes per level.

Not asked by any past midterm. The I–V models (HW1-1a, HW1-4) and scaling (HW1-5) appear in the finals (FN10-6a–b compares the two models’ supply sensitivity) and in midterm short answers only as reasoning: “linear, not square” and “$v_{sat}$vsat​ doesn’t scale”. Know the doubling test and the two delay columns of the scaling table.

What the key gets wrong

Re-solving every part found these disagreements; all are recorded in this page’s review/decisions.md.

Part	The key	Here
HW1-1a	velocity-saturated current “only goes up linearly” with the overdrive	that is the full limit; its own curves grow 2.9× when the overdrive doubles, and reach 35% of the limit
HW1-1b	$C_{max} = 25.89\,\mathrm{fF}$ (width rounded to 120 nm)	124 nm, so $C_{max} = 25.0\,\mathrm{fF}$25.0fF; $C_{min} = 10.6\,\mathrm{fF}$ (the key’s 10.7 is rounding)
HW1-3	the expression joins the two factors with “+”	a product; the boxed 0.46 pA is right
HW1-4a	“170 µA” in the prose	its arithmetic uses 160 µA; the boxed $5.4\times10^6\,\mathrm{cm/s}$ is right
HW1-4b	$0.001\,\mathrm{cm} = 10\,\mu\mathrm{m}$	$1.12\times10^{-3}\,\mathrm{cm} = 11\,\mu\mathrm{m}$

Every other part (HW1-2a–c, HW1-5) agrees with its key after re-solving. HW1-2d is out of scope.