M4. Path sizing: the exam way

This is the exam way of M4: each part as you would write it on the paper, with what to recognize, the lines to write, the trap to watch and the answer. Every part keeps the anchor it has on M4, so the switch at the top of the page takes you to the same part’s full solution. The method is the path-sizing card of the playbook. So far this page covers MT23-5; MT21-5 and MT17-5 follow in the retrofit of M4.

The clock. The midterms gave 75 minutes for 150 points, 30 s a point, so a 10-point part has about 5 minutes. The past finals gave 180 minutes for 200–250 points, about 0.7–0.9 min a point, so a 10-point part there has 7–9 minutes.

1. MT23-5: a 25 fF side load (40 points)

MT23-5, p11. Consider the critical path shown below through a set of complementary static CMOS gates. In this technology, the nFET and pFET have the same drive strength and the circuit is sized for equal rising and falling delays. We are working in a technology in which the gate capacitance per unit width is 1 fF/µm. Assume that the FO1 delay is $\tau_{inv} = 50$ psec. A minimum width device 1.0 µm. Please ignore source-drain diffusion capacitances and overlap capacitances; that is, worry only about the gate input capacitances of the devices. Let $C_{load} = 1$ pF.

MT23-5’s critical path (p11, redrawn): inverter $W_1$W1​, AOI22 $W_2$W2​, NAND2 with PFETs $W_3$ and series NFETs $2W_3$2W3​, inverter $W_4$W4​, then $C_{load}$Cload​.

Reading the circuit

Write this table once; every part reads from it. Equal strengths: a balanced inverter is W/W, input $2W$2W. Two devices in series act like one of half the width.

Stage	Gate	Normalized input	One input	$g$
1	inverter W₁/W₁	$2W_1$	$2W_1$	1
2	AOI22, all W₂ (stacks of two)	$W_2$	$2W_2$	2
3	NAND2, NFETs 2W₃, PFETs W₃	$2W_3$	$3W_3$	3/2
4	inverter W₄/W₄	$2W_4$	$2W_4$	1

Load: $1\,\mathrm{pF}/(1\,\mathrm{fF/\mu m}) = 1000\,\mu$m of gate.

Part (a): the delay as drawn (10 points)

MT23-5a. Estimate the delay of the path from A to E, which is the same for a falling (rising) input at A propagating to a rising (falling) output at E. Let $W_1 = 10\,\mu$m, $W_2 = 1.0\,\mu$m, $W_3 = 1.0\,\mu$m, and $W_4 = 1.0\,\mu$m. (10 points)

Hint

Each stage’s gain is the next stage’s input (or the load) over its own normalized inverter’s input. The stage table under Reading the circuit lists both for every gate.

Recognize. Path sizing, move (a): the delay as drawn. About 5 minutes.

On the paper.

1. Delay $= \tau_{inv}\sum$ gains; gain = load ÷ normalized input.
2. $f_4 = 1000/(2 \cdot 1) = 500$
3. $f_3 = 2W_4/2W_3 = 2/2 = 1$
4. $f_2 = 3W_3/W_2 = 3/1 = 3$
5. $f_1 = 2W_2/2W_1 = 2/20 = 0.1$
6. $\sum = 504.1$504.1; $504.1 \times 50\,\mathrm{ps} = 25.2$ ns

Watch out. The AOI22’s gain divides by its normalized input $W_2$W2​, not its own input $2W_2$2W2​; the latter gives $h = 1.5$ and halves its delay.

Answer: $504.1\,\tau_{inv} \approx 25.2$ ns. The last stage’s gain of 500 is almost all of it.

Full solution

Part (b): equal-gain sizing (10 points)

MT23-5b. Assume that $W_1$ is fixed at 1.0 µm but you are free to tune $W_2$W2​, $W_3$W3​, and $W_4$W4​. Find approximate values of $W_2$W2​, $W_3$W3​, and $W_4$ to minimize delay and estimate the new delay of your resized network. (10 points)

Hint

Write the four gains with $W_2$W2​, $W_3$ and $W_4$ as unknowns and multiply them. What is left?

Recognize. Path sizing, move (b): one gate fixed, nothing branching, “minimize delay”: equal gains. About 5 minutes.

On the paper.

1. No branch, so $F = \dfrac{2W_2}{2W_1}\cdot\dfrac{3W_3}{W_2}\cdot\dfrac{2W_4}{2W_3}\cdot\dfrac{1000}{2W_4} = \dfrac{1500}{W_1} = 1500$
2. Equal gains: $f = 1500^{1/4}$15001/4: $\sqrt{1500} = 38.73$38.73, $\sqrt{38.73} = 6.223$
3. Back from the load: $1000/(2W_4) = f \Rightarrow W_4 = 80.3\,\mu$m
4. $2W_4/2W_3 = f \Rightarrow W_3 = 12.9\,\mu$m
5. $3W_3/W_2 = f \Rightarrow W_2 = 6.22\,\mu$m
6. Check: $f_1 = W_2/W_1 = 6.22 = f$ ✓
7. Delay $= 4f\,\tau_{inv} = 24.89 \times 50\,\mathrm{ps} = 1245$ ps

Watch out. The answer is in picoseconds: 1245 ps is 1.24 ns (the key writes “1244.7 ns”). Size from the load back; the first stage only checks.

Answer: $W_2 = 6.22\,\mu$m, $W_3 = 12.9\,\mu$m, $W_4 = 80.3\,\mu$m; delay $24.9\,\tau_{inv} \approx 1.24$ ns, down from 25.2 ns.

Full solution

Part (c): the side load (10 points)

MT23-5c, p13. Now assume that the circuit is modified as shown below. What is the delay of the circuit now from A to E using your sizing from (b)? (10 points)

MT23-5c’s path (p13, redrawn): 25 fF from node C, the AOI22’s output, to ground.

Hint

Which stage’s output is the node the capacitor hangs on? Only that stage’s load changes.

Recognize. Path sizing, move (c): a side load at fixed sizes. About 5 minutes.

On the paper.

1. 25 fF hangs on node C, the AOI’s output: stage 2. $25\,\mathrm{fF} = 25\,\mu$m of gate
2. $f_2 = (3W_3 + 25)/W_2 = (38.73 + 25)/6.223 = 10.24$
3. $f_1 = f_3 = f_4 = 6.223$ (loads and sizes unchanged)
4. Delay $= (3 \times 6.223 + 10.24)\,\tau_{inv} = 28.91 \times 50\,\mathrm{ps} = 1446$ ps

Watch out. Read the node from the figure: the capacitor is on C, not on D (the key puts it on D and gets 1.29 ns).

Answer: $28.9\,\tau_{inv} \approx 1.45$ ns.

Full solution

Part (d): retuning (10 points)

MT23-5d, p14. How might this new circuit be resized to reduce the delay calculated in (c), again keeping $W_1$ fixed? Perform this retuning and calculate the new delay. You do not have to achieve a “minimum” delay here; just demonstrate how you would retune the circuit to improve the delay. (10 points)

The 25 fF on node C. Original figure ↑

Hint

Nothing branches between stages 1 and 2. If only $W_2$ changes, what happens to the product of their two gains?

Recognize. Path sizing, move (d): retune around a branch. About 5 minutes for lines 1–4, which answer the question; lines 5–8 only if time is left (the minimum isn’t required).

On the paper.

1. Branch on C: $F$ now depends on $W_3$W3​, so don’t reuse $F^{1/4}$
2. Only $W_2$ moves: $f_1f_2 = W_2 \cdot 63.73/W_2 = 63.73$63.73, fixed, so make them equal
3. $f_1 = f_2 = \sqrt{63.73} = 7.98$7.98, so $W_2 = 7.98\,\mu$m
4. Delay $= 2(7.98) + 2(6.223) = 28.41\,\tau_{inv} = 1.42$ ns
5. If time: split at C; balance each side: $D(W_3) = 2\sqrt{3W_3 + 25} + 2\sqrt{500/W_3}$
6. If time: $W_3 = 16$16: $2\sqrt{73} + 2\sqrt{31.25} = 17.09 + 11.18 = 28.27$
7. If time: $W_2 = \sqrt{73} = 8.54$8.54; $f_3 = f_4 = \sqrt{31.25} = 5.59$5.59, so $W_4 = 500/5.59 = 89.4\,\mu$m
8. If time: delay $= 28.27\,\tau_{inv} \approx 1.41$ ns

Watch out. Recomputing $F$ and taking $\sqrt[4]{F}$ treats $F$ as fixed; on node C it gives $28.98\,\tau_{inv}$28.98τinv​, slower than not retuning.

Answer: first $W_2 = 8.0\,\mu$m (1.42 ns); then $W_2 = 8.5$8.5, $W_3 = 16$16, $W_4 = 89\,\mu$m, which gives $28.3\,\tau_{inv} \approx 1.41$ ns. That is the minimum to within 0.01%. The best gains are not equal: the two stages before the branch share one value (8.54), the two after it a smaller one (5.59).

Full solution

2. MT21-5: an input limit and a 500 fF branch (35 points)

The exam way of MT21-5 comes with the retrofit of M4. Until then, work it from the full solution and the path-sizing card.

3. MT17-5: unequal strengths and a branch inverter (40 points)

The exam way of MT17-5 comes with the retrofit of M4. Until then, work it from the full solution and the path-sizing card.