PS5: Problem Set 5 (latches and clocking)
This term’s Problem Set 5 (due November 4, 2026), with no points and no official key: the guide re-solves every part. Work through it in order: each part gives its question in short and links to its full solution and its exam way.
8 parts: all solved in the guide, each with an exam way.
PS5-Q1
PS5-Q1a
One latch in a 7 ns loop, high 5 ns and low 5 ns: is it a valid FSM? If not, how could it be fixed?
PS5-Q1b
A – latch pair around 12 ns of logic, with a 10 ns cycle.
PS5-Q1c
Two flip-flops with the primed clocks 1.5 ns late, 1 ns of forward logic and 11 ns back.
PS5-Q1d
Latches on , , , with 2 ns, 11 ns and 4 ns of logic.
PS5-Q1e
Four latches with 6, 5, 6 and 4 ns of logic: a 21 ns loop over two cycles.
PS5-Q2
Design a two-bit wrap-around counter (00 to 11, then 00) with a synchronous reset, for the fastest clock possible.
The guide solves the logic and the reset; the search for the highest clock frequency in Spectre is simulation work and is left out.
PS5-Q3
PS5-Q3a
Draw a static master–slave flip-flop with scan inputs SI and SE, from its function table.
PS5-Q3b
Chained through SI, the flip-flops form a scan chain: how does that help testing, and what is the test procedure?