FT1. Stuck-at faults, scan, reliability and minimum energy: the exam way

This is the exam way of FT1: each part as you would write it on the paper, with what to recognize, the lines to write, the trap to watch and the answer. Every part keeps the anchor it has on FT1, so the switch at the top of the page takes you to the same part’s full solution. The methods are four cards of the playbook: stuck-at faults and scan for FN10-3, FN17-4, FN19-4 and PS5-Q3b; the scan flip-flop for PS5-Q3a; clock latency and reliability for FN17-1d and FN17-1e; and the subthreshold supply for FN10-2c and FN17-10c. FT1 sets each method out in full in its approach sections (scan, short answers, the supply). FT1’s seven harder variations stay on FT1 only, at the end of each family: stuck-at faults and scan, latency and reliability and the lowest supply and minimum energy. Work them there, against the budgets their titles give.

The clock. The past finals gave 180 minutes. FN10 had 200 points, 0.9 min a point, so FN10-3’s 10 points and FN10-2c’s 10 have about 9 minutes each. FN17 and FN19 had 250, 0.72 min a point: FN17-4’s two 10-point parts have about 7 minutes each, FN19-4’s 20 points about 14, the 5-point short answers FN17-1d and FN17-1e about 4 each, and FN17-10c’s 8 points (overwritten on the scan) about 6. PS5 is a problem set and gives no points; each of its parts gets the budget of a final part with the same work at 0.9 min a point: about 9 minutes for Q3a’s drawing (as a 10-point part) and 7 for Q3b’s two short answers (as 8 points). (The past midterms gave 75 minutes for 150 points, 0.5 min a point: a final part has more time, and more steps.)

Conventions. Fault values are written good/faulty: “0/1” is 0 in the good circuit and 1 in the faulty one; ST0 and ST1 are stuck at 0 and at 1. Patterns list the inputs in the order the part names them. A chain runs scan_in → $F_1$ → … → $F_n$ → scan_out, so scan_in carries $q_n$ first and scan_out gives $D_n$ first; L, C and U name the load, capture and unload edges. Subthreshold numbers use the papers’ $S$ = 80 mV/decade and $I_{off}$ = 10 nA, with $kT/q$ = 26 mV; $u = V\ln 10/S$Vln10/S.

FN10-3: a stuck-at-1 test through reconvergent fan-out (10 points)

FN10-3, p5. Determine a test pattern to detect a stuck-at-one fault at node X in the following network and propagate it to the output Z. Is this pattern unique? (10 points)

FN10-3’s network (Final 2010, p5, redrawn). The question calls the output Z; the figure labels it Y, and this page writes Y. $P$P, $Q$ (the outer ANDs’ outputs) and $N_1$N1​, $N_2$ (the NORs’ outputs) are this guide’s names.

The pattern and whether it is unique (10 points)

FN10-3, p5. Determine a test pattern to detect a stuck-at-one fault at node X in the following network and propagate it to the output Z. Is this pattern unique? (10 points)

Hint

With X stuck at 1, what do both NORs output in the faulty circuit, whatever the other inputs are? What must the good circuit’s Y be, then?

Recognize. Stuck-at faults and scan: “a stuck-at-one fault at node X”, “propagate it to the output”, “is this pattern unique?”. $X$ fans out to two NORs that meet again at a NAND: a reconvergence. About 9 minutes: write the faulty output first, and the condition on both branches follows from it.

On the paper.

1. $P = AB$AB, $X = CD$CD, $Q = EF$EF; $N_1 = \overline{P + X}$P+X​, $N_2 = \overline{X + Q}$X+Q​; $Y = \overline{N_1N_2}$
2. Faulty: $X = 1$ controls both NORs: $N_1 = N_2 = 0$0, so $Y = 1$ for every pattern
3. So the good $Y$ must be 0: $N_1 = N_2 = 1$1, both branches open
4. Control: good $X = 0$0, so $CD \ne 11$11; $X$ = 0/1
5. $N_1 = 1$ needs $P = AB = 0$0; $N_2 = 1$ needs $Q = EF = 0$
6. Pattern $ABCDEF$ = 000000: $N_1$ = 1/0, $N_2$ = 1/0, $Y$ = 0/1 ✓
7. Unique? Each pair $AB$AB, $CD$CD, $EF$ is 00, 01 or 10: $3 \times 3 \times 3 = 27$ of $2^6 = 64$
8. Not unique; both branches must be sensitized

What to write on the figure (FT1’s values): (a) 000000 opens both branches and is detected; (b) 110000 opens one, and $Y$ = 1/1. Original figure ↗

Watch out. The single-path recipe fails here. Opening one branch (110000: $Q = 0$0, but $P = 1$ holds $N_1$ at 0) gives $Y$ = 1/1, because a steady 0 into the NAND is its controlling value. “Unique?” asks for a count, not a yes.

Answer: for example $ABCDEF$ = 000000 (any pattern with $AB \ne 11$11, $CD \ne 11$ and $EF \ne 11$11): the good $Y$ is 0, the faulty $Y$ is 1. Not unique: 27 of the 64 patterns detect it. Both branches from $X$ must be sensitized: the faulty $Y$ is 1 for every pattern, so the good $Y$ must be 0, and that needs both NORs at 1.

Full solution

FN17-4: a stuck-at-0 fault behind a three-flip-flop scan chain (20 points)

FN17-4, p9. Consider the circuit shown below.

FN17-4’s scan chain (Final 2017, p9, redrawn): scan_in → $F_1$ ($W_1$W1​) → $F_2$ ($W_2$W2​) → $F_3$ ($W_3$W3​) → scan_out, on one clk and one scan_enable. The labels $F_1$–$F_3$ are this guide’s. The block’s outputs $Y_1$Y1​, $Y_2$Y2​, $Y_3$ return to the D inputs; $Z_1$Z1​, $Z_2$ are primary outputs and $X_1$ a primary input.

The block inside (FN17-4, p9, redrawn). $A$ is the paper’s name; $O$ ($= Z_2 = Y_3$=Y3​), the OR’s output, is this guide’s.

Part (a): the pattern and the order (10 points)

FN17-4a, p9. Determine an appropriate test pattern that achieves controllability and observability for a stuck-at-zero fault at node A. What value must be scanned into the flip-flops? In what order? (10 points)

Hint

Node A feeds two gates. Which of them can carry a change in A when A is 1, and what does the OR’s output do to the other?

Recognize. Stuck-at faults and scan: “controllability and observability”, “a stuck-at-zero fault at node A”, “what value must be scanned into the flip-flops? In what order?”. About 7 minutes: control first, because here it picks the path; then reverse the load for scan_in.

On the paper.

1. $Z_1 = \overline{W_1W_2}$W1​W2​​, $A = W_2W_3$W2​W3​, $O = W_1 + W_2 + W_3$ $(= Z_2 = Y_3)$
2. $Y_1 = \overline{Z_1X_1A}$Z1​X1​A​, $Y_2 = \overline{A + O}$
3. Control: good $A = 1$1, so $W_2 = W_3 = 1$1; $A$ = 1/0
4. Then $O = 1$1, controlling for the NOR: $Y_2$ = 0/0, blocked
5. Observe at $Y_1$Y1​: $Z_1 = 1$ needs $W_1 = 0$0; $X_1 = 1$ (primary input, held by the tester)
6. $Y_1 = \overline{1\cdot1\cdot A}$ = 0/1 ✓
7. Pattern $X_1 = 1$1, $W_1W_2W_3 = 011$011: every input forced, the only one of 16
8. The first bit in ends in $F_3$F3​: scan_in carries $W_3, W_2, W_1$ = 1, 1, 0 (SE = 1, three edges)

What to write on the logic (FT1’s values): $A$ = 1/0 reaches $Y_1$Y1​; $O = 1$ blocks the NOR. Original figure ↗

Watch out. $Y_2$ looks like the short way out, but the control condition $W_2 = 1$ makes the NOR’s other input 1. Shifting in $W_1, W_2, W_3$ in that order loads them reversed. $X_1$ is applied, not scanned.

Answer: scan $W_1W_2W_3 = 011$ into the flip-flops and hold the primary input $X_1 = 1$1. In time order scan_in carries 1, 1, 0 ($W_3$W3​ first, $W_1$ last). The fault is observed at $Y_1$ (the NOR to $Y_2$ is blocked by $O = 1$1); it is the only pattern that works.

Full solution

Part (b): what comes out, good and bad (10 points)

FN17-4b, p9. After the scanned pattern of (a) is clocked once, what values will be scanned out of the registers for the “bad” circuit? What would be expected values for the “good” circuit? (10 points)

Hint

After the capture edge, which flip-flop’s value is already on scan_out, and which comes next?

Recognize. Stuck-at faults and scan: “clocked once”, “scanned out of the registers”, the “bad” and the “good” circuit. About 7 minutes: evaluate the logic twice, then reverse for scan_out.

On the paper.

1. “Clocked once”: one capture edge, SE = 0: $F_1, F_2, F_3 \leftarrow Y_1, Y_2, Y_3$
2. Good, at $X_1 = 1$1, 011: $Z_1 = 1$1, $A = 1$1, $O = 1$1: $Y_1 = 0$0, $Y_2 = 0$0, $Y_3 = 1$
3. Bad, $A = 0$0: $Y_1 = \overline{1\cdot1\cdot0} = 1$1, $Y_2 = \overline{0 + 1} = 0$0, $Y_3 = 1$
4. Registers $(Y_1, Y_2, Y_3)$(Y1​,Y2​,Y3​): good (0, 0, 1), bad (1, 0, 1)
5. scan_out is $F_3$‘s Q: $Y_3$ first, then $Y_2$Y2​, then $Y_1$
6. scan_out: good 1, 0, 0; bad 1, 0, 1: the third bit out differs
7. $Z_1 = Z_2 = 1$ in both circuits: only the chain sees the fault

What to draw if there is time (FT1’s waveforms): the bit after U2, $Y_1$Y1​, tells the circuits apart. Original figure ↗

Watch out. $(Y_1, Y_2, Y_3)$ is the register view; on scan_out the same bits come in reverse order. Label which one you give, or give both: the key gives only the registers.

Answer: after one capture edge the registers hold good $(Y_1, Y_2, Y_3) = (0, 0, 1)$ and bad $(1, 0, 1)$(1,0,1). Scanned out, $Y_3$ first, the good circuit gives 1, 0, 0 and the bad circuit 1, 0, 1: the third bit out, $Y_1$Y1​, reveals the fault.

Full solution

FN19-4: scan waveforms for a stuck-at-1 fault (20 points)

FN19-4, p9. Sketch the waveforms for scan_enable, clock, scan_in, and scan_out for a test sequence to scan in a test pattern, clock the system once, and scan out the resulting pattern such that a stuck-at-one fault at node X could be detected. Show where this would be detected in your waveform. (20 points)

FN19-4’s circuit (Final 2019, p9, redrawn). The flip-flops are numbered in chain order, $F_1$–$F_4$ down the left, $F_5$ at the bottom right, $F_6$ at the top right (scan_out); $P = q_1q_2$ is this guide’s name, $X = q_3q_4$ the paper’s. The left column’s D inputs come from logic outside the figure.

The waveforms and where the fault shows (20 points)

FN19-4, p9. Sketch the waveforms for scan_enable, clock, scan_in, and scan_out for a test sequence to scan in a test pattern, clock the system once, and scan out the resulting pattern such that a stuck-at-one fault at node X could be detected. Show where this would be detected in your waveform. (20 points)

Hint

X feeds only the NOR into F5. What must the NOR’s other input be, and how many edges after the capture does F5’s value reach scan_out?

Recognize. Stuck-at faults and scan: “sketch the waveforms for scan_enable, clock, scan_in, and scan_out”, “clock the system once”, “show where this would be detected”. About 14 minutes: 4 for the chain order and the pattern, 10 for the drawing.

On the paper.

1. Chain (follow Q to SI): scan_in → $F_1$ … $F_4$ → $F_5$ (bottom right) → $F_6$ → scan_out
2. $P = q_1q_2$q1​q2​, $X = q_3q_4$q3​q4​; $D_6 = \overline P$P, $D_5 = \overline{P + X}$
3. Control: good $X = 0$0, so $q_3q_4 \ne 11$11; $X$ = 0/1
4. Observe at $D_5$ ($D_6$D6​ never sees $X$X): $P = 0$0, so $q_1q_2 \ne 11$11; $D_5$ = 1/0
5. Load $q_1 \ldots q_6$ = 101000 (36 of the 64 loads work; 000000 is the simplest)
6. scan_in, $q_6$ first: 0, 0, 0, 1, 0, 1 on L1–L6, SE = 1
7. SE falls after L6, before C; one capture edge C; SE rises again before U1
8. After C: scan_out $= D_6 = 1$ in both circuits
9. After U1: scan_out $= D_5$D5​: 1 good, 0 faulty, marked “detected”
10. U2–U5: $F_4 \ldots F_1$‘s captures (unknown, from logic off the figure); U6 ends the unload: 6 + 1 + 6 = 13 edges

What to draw (FT1’s waveforms): SE low across exactly one edge; the fault shows in the second bit out. Original figure ↗

Watch out. The fault shows in the second bit out, not the first: $F_6$ carries $\overline P$P, which $X$ cannot change. Number the flip-flops in chain order before you count, and change SE between edges, never on one.

Answer: load, for example, $q_1 \ldots q_6$ = 101000 (any load with $q_1q_2 \ne 11$ and $q_3q_4 \ne 11$11): SE high for six edges with scan_in 0, 0, 0, 1, 0, 1; SE low for one capture edge; SE high to shift out. scan_out shows $D_6 = 1$ in both circuits after the capture, then $D_5$ after the first unload edge, 1 good and 0 faulty: the fault is detected at the second bit out.

Full solution

PS5-Q3: the scan flip-flop and the scan test

PS5-Q3, p3. To improve the testability of a digital integrated circuit (that is, to improve the ability to detect and isolate manufacturing faults), it is a common practice in flop-based designs to modify the basic master-slave flip-flop (with inputs D, for data, CLK, for clock, and Q, for output) described in class to include two additional inputs, SI (for scan in) and SE (for scan enable). The function table for this “testability-enhanced” flip-flop is shown below:

D	SI	SE	CLK	Q[n+1]
1	X	0	rising edge	1
0	X	0	rising edge	0
X	X	X	falling edge	Q[n]
X	1	1	rising edge	1
X	0	1	rising edge	0

PS5-Q3 prints no figure. This is the table’s cell at gate level (Chapter 22 §4, Lecture21 @ 33:30): a 2:1 multiplexer on SE (input 0 is D, input 1 is SI) in front of a rising-edge flip-flop. X in the table means “don’t care”.

Part (a): the static scan flip-flop at the switch level

PS5-Q3a, p3. Draw the schematic for a static flip-flop enhanced in this way.

Hint

Which block selects between D and SI, and which edge must the master latch close on for the table’s rising-edge rows?

Recognize. The scan flip-flop: a function table with SI and SE, “draw the schematic for a static flip-flop”. About 9 minutes, as a 10-point drawing (PS5 gives no points): the mux, the master, the slave, the complements.

On the paper.

1. The table: $Q^+ = \overline{SE}\cdot D + SE\cdot SI$ at each rising edge; a falling edge holds
2. Mux: two transmission gates into node $m$m; D’s has its NFET on $\overline{SE}$SE, PFET on SE; SI’s the mirror
3. Rising edge: master transparent while CLK = 0, slave while CLK = 1
4. Master: input gate (NFET $\overline{CLK}$CLK, PFET CLK), forward inverter; feedback inverter and gate (NFET CLK, PFET $\overline{CLK}$CLK)
5. Slave: the same with the clocks swapped; its forward inverter drives Q
6. Static: each latch closes its feedback loop while it holds
7. Two inversions from $m$ to Q: Q $= m$ ✓
8. Two inverters make $\overline{SE}$ and $\overline{CLK}$
9. Count: $2\times2 + 2\times8 + 2\times2 = 24$ transistors
10. Row 3: CLK falls, the slave closes and holds, Q unchanged ✓

What to draw (FT1’s cell): the mux in a dashed box, then the master and slave latches, each with its feedback gate. Original figure ↗

Watch out. Chapter 13’s drawing puts the master on CLK (transparent while CLK = 1): that cell captures at the falling edge, against the table. A latch without its feedback loop is dynamic, not static.

Answer: the circuit drawn above: a multiplexer of two transmission gates (D passes while SE = 0, SI while SE = 1) into a static positive-edge master–slave flip-flop (master transparent while CLK = 0, slave while CLK = 1, each latch with switched feedback), with inverters for $\overline{SE}$ and $\overline{CLK}$CLK: 24 transistors.

Full solution

Part (b): why scan helps, and the test procedure

PS5-Q3b, p3. With this type of flip-flop design it is possible to reconfigure all the flip-flops in the machine as a long shift register (called a scan chain), in which the output of each flip-flop is connected to the SI input of another. How might this improve our ability to test a chip? What would be the test procedure?

Hint

Without the chain, how would a tester put a chosen value into a flip-flop deep inside the chip, and how would it read one out?

Recognize. Stuck-at faults and scan: “how might this improve our ability to test a chip?”, “what would be the test procedure?”. Two short answers in about 7 minutes, as 8 points: the course’s two words, then the phases with SE’s value in each.

On the paper.

1. SE = 1: the flip-flops form one shift register, scan_in → … → scan_out
2. Controllability: any state is shifted in, in $n$ edges
3. Observability: one capture edge, then every captured D is shifted out
4. So only combinational logic is left: stuck-at patterns, generated automatically
5. (i) Test the chain: shift a known sequence (0101…) through; it emerges $n$ edges later
6. (ii) SE = 1: shift the pattern in, $n$ edges, the last flip-flop’s bit first
7. (iii) SE = 0: apply the primary inputs, one capture edge
8. (iv) SE = 1: shift the response out, $n$ edges, comparing with the good response; load the next pattern meanwhile
9. (v) Any mismatch fails the chip; its position names the flip-flop whose logic holds the fault
10. Cost: $p(n + 1) + n$ edges; e.g. $n$ = 1,000, $p$ = 500: 501,500 edges

Watch out. Answer both questions: the benefit in the course’s two words, controllability and observability, and the procedure with SE in each phase. Test the chain itself first; running programs on the chip (functional testing) is not the answer, since its coverage of defects is unknown.

Answer: the chain makes every flip-flop controllable (any state shifted in) and observable (every captured value shifted out), so the chip is tested as combinational logic with stuck-at patterns. Procedure: test the chain itself; then for each pattern, shift it in with SE = 1, capture once with SE = 0 and the primary inputs applied, and shift the response out with SE = 1 (loading the next pattern) and compare it with the good circuit’s.

Full solution

FN17-1d: why low clock latency (5 points)

FN17-1d, p3. Why is reducing the latency in a clock distribution desirable? Explain. (5 points)

FN17-1d prints no figure. This is how latency turns variation into skew and jitter (Chapter 23 §6, added; after Lecture22 @ 21:57): (a) every leaf’s clock comes $t_L$ after the root’s, and one buffer on B’s branch sees a lower supply; (b) a static difference delays clk_B by the same $\delta$ every cycle (skew), a varying supply moves its edge within a band (jitter).

The answer (5 points)

FN17-1d, p3. Why is reducing the latency in a clock distribution desirable? Explain. (5 points)

Hint

If every leaf received the clock exactly t_L after the root, would the size of t_L matter? What makes two leaves’ delays differ?

Recognize. Clock latency and reliability, the latency short answer: “why is reducing the latency … desirable? Explain.” About 4 minutes: three sentences, and a number if time is left.

On the paper.

1. An equal latency cancels: launch and capture are both $t_L$ late
2. But $t_L$ is buffers and wires whose delays vary with PVT, each by a fraction $\epsilon$
3. The arrival error is about $\epsilon\,t_L$ϵtL​: proportional to the latency
4. Static differences between branches → skew; transient ones (supply noise) → jitter
5. $t_{skew},\ t_{jitter} \approx |S_V|\,(\Delta V_{DD}/V_{DD})\,t_L$∣SV​∣(ΔVDD​/VDD​)tL​, $S_V = -V_T/(V_{DD} - V_T)$
6. Both come off the cycle, $t_{clk\to Q} + t_{logic} + t_{setup} + t_{skew} + t_{jitter} \le T$T, and off the hold margin
7. e.g. 0.9 V, $V_T$ = 0.35 V: $|S_V|$ = 0.636; a 6 % difference gives 30.5 ps in 800 ps, 11.5 ps in 300 ps

Watch out. “Latency adds delay to every path” earns nothing: it cancels from both ends of the path. The marks are for the mechanism: PVT variation acts on the latency, in proportion, as skew and jitter.

Answer: because latency turns PVT variation into skew and jitter. Each buffer’s delay changes by a fraction under process, supply and temperature variation, so the arrival-time error is that fraction of the latency: static differences become skew, transient ones (supply noise) jitter, both in proportion to the latency and both taken off the cycle time and the hold margin. (For example, a 6 % supply difference gives 30.5 ps of skew in an 800 ps network, 11.5 ps in a 300 ps one.)

Full solution

FN17-1e: infant mortality and burn-in (5 points)

FN17-1e, p3. The process by which chips that fail early in their lifetime is sometimes referred to as “infant mortality.” Name one mechanism that produces infant mortality and how burn-in testing helps to identify chips that will fail early in their lifetime based on this mechanism. (5 points)

FN17-1e prints no figure. This is a latent defect (Chapter 22 §10, redrawn from Lecture21 @ 51:47): a wire of width $w$ necked by a particle to $w_{neck}$wneck​. The current $I$ crowds into the neck, where its density is $w/w_{neck}$ times higher.

The answer (5 points)

FN17-1e, p3. Name one mechanism that produces infant mortality and how burn-in testing helps to identify chips that will fail early in their lifetime based on this mechanism. (5 points)

Hint

A die whose wire is narrowed but not cut passes every logic test. What happens in that narrow spot when current flows for weeks, and what speeds it up?

Recognize. Clock latency and reliability, the reliability short answer: “infant mortality”, “name one mechanism”, “how burn-in testing helps to identify”. About 4 minutes: the defect, the mechanism, what speeds it up, the test after.

On the paper.

1. Latent defect: a particle necks a wire in lithography; it still conducts, so the die passes the test
2. The current crowds into the neck: $J = I/(wt)$I/(wt), $J_{neck}/J = w/w_{neck}$ (e.g. $0.8/0.2 = 4$4)
3. Electromigration (a DC current drags metal atoms along) opens the neck early in life
4. It is accelerated by temperature and by current density
5. Burn-in: run hot (about 85 °C) at about 20 % over nominal $V_{DD}$VDD​: the necks fail in hours
6. Test again after burn-in, at nominal; the failures are discarded, and what ships starts on the bathtub’s flat bottom

What to sketch if asked (Chapter 22 §11): burn-in spends the infant-mortality region before $t_{ship}$tship​. Original figure ↗

Watch out. Oxide breakdown (TDDB), hot carriers (HCI) and NBTI are wear-out, the bathtub’s rising end; burn-in does not screen them. Burn-in stresses the chips; the test afterwards is what identifies them.

Answer: electromigration through a necked wire: a particle narrows a wire, which still conducts and passes the test, but the current density in the neck is several times the design value, and electromigration opens it early in life. Electromigration is accelerated by temperature and current, so burn-in (about 85 °C and about 20 % over the nominal supply) makes these wires fail in the factory; the test after burn-in catches them.

Full solution

FN10-2c: the lowest working supply (10 points)

FN10-2, p3. Consider an inverter operating with a supply voltage of $V_{DD}$ with logic signals that swing between ground and $V_{DD}$VDD​. (assume $V_T > 0.2$ V; a handwritten addition on the paper.) (a) Let $V_{DD}$ = 0.2 V. Assume that the $I_{off}$ of each transistor is 10 nA. (For the nFET, $I_{off}$ is defined by $V_{GS}$ = 0.0 V and $V_{DS} = V_{DD}$VDD​. For the pFET, $I_{off}$ is defined by $V_{SG}$ = 0.0 V and $V_{SD} = V_{DD}$VDD​.) If the subthreshold slope is 80 mV/decade, what is the $I_{on}/I_{off}$ ratio for each transistor? (For the nFET, $I_{on}$ is defined by $V_{GS} = V_{DD}$ and $V_{DS} = V_{DD}$VDD​. For the pFET, $I_{on}$ is defined by $V_{SG} = V_{DD}$ and $V_{SD} = V_{DD}$VDD​.) (10 points)

FN10-2’s inverter (Final 2010, p3, redrawn), with part (c)‘s operating point added: input $0.9V_{DD}$ (from an identical stage), output $0.1V_{DD}$0.1VDD​; the off PFET leaks $I_P$IP​, the on NFET, with only $0.1V_{DD}$ across it, sinks $I_N$IN​. Parts (a)–(b) are solved on FN2.

Part (c): the lowest supply for a 10–90 % swing (10 points)

FN10-2c, p4. Imagine that we continue to scale down $V_{DD}$VDD​. Find the lowest value of $V_{DD}$ at which the inverter will operate with an output swing of at least $0.1V_{DD}$ to $0.9V_{DD}$0.9VDD​. What is the $I_{on}/I_{off}$ ratio for each transistor at this value of $V_{DD}$VDD​? (10 points)

Hint

With the output low, which device carries current in, which carries it out, and what are each one’s gate and drain voltages if the input comes from an identical inverter?

Recognize. The subthreshold supply, its functional limit: “continue to scale down $V_{DD}$VDD​”, “the lowest value of $V_{DD}$ … output swing of at least $0.1V_{DD}$ to $0.9V_{DD}$0.9VDD​”, “$I_{on}/I_{off}$Ion​/Ioff​ … at this value”. About 9 minutes: the balance in four lines, the search in two, the ratio in one.

On the paper.

1. Output low at $0.1V_{DD}$0.1VDD​; input from an identical stage, $0.9V_{DD}$
2. NFET, $V_{GS} = 0.9V_{DD}$0.9VDD​, $V_{DS} = 0.1V_{DD}$0.1VDD​: $I_N = I_{off}10^{0.9V_{DD}/S}(1 - e^{-0.1V_{DD}/(kT/q)})$
3. PFET, $V_{SG} = 0.1V_{DD}$0.1VDD​, $V_{SD} = 0.9V_{DD}$ (drain factor ≈ 1): $I_P = I_{off}10^{0.1V_{DD}/S}$
4. $I_N = I_P$IP​, $I_{off}$ cancels: $10^{-0.8V_{DD}/S} = 1 - e^{-0.1V_{DD}/(kT/q)}$
5. $S$ = 0.08 V, $kT/q$ = 0.026 V: $10^{-10V_{DD}} = 1 - e^{-3.85V_{DD}}$
6. 60 mV: 0.251 > 0.206; 70 mV: 0.200 < 0.236; the crossing lies between
7. Refine: $V_{DD}$ = 65.3 mV (both sides 0.222)
8. Part (a)‘s ratio for each transistor: $I_{on}/I_{off} = 10^{V_{DD}/S} = 10^{65.3/80} = 6.56$ (6.49 at 65 mV)
9. (Keeping the PFET’s drain factor too gives 62.0 mV; a full-rail input, both factors kept, 52.8 mV: say which reading you use)

The balance (FT1’s plot): the two sides of line 4 cross at 65.3 mV. Original figure ↗

Watch out. The key’s $I_{on}/I_{off} = 10^{0.8V_{DD}/S} = 4.47$ is the NFET’s drive at $0.9V_{DD}$ against the PFET’s at $0.1V_{DD}$0.1VDD​, not part (a)‘s ratio; by (a)‘s definition it is $10^{V_{DD}/S} \approx 6.5$6.5. Drop the NFET’s drain factor and the currents never balance.

Answer: $V_{DD} \approx$ 65 mV (65.3 mV, from $10^{-0.8V_{DD}/S} = 1 - e^{-0.1V_{DD}/(kT/q)}$ with the input from an identical stage and the NFET’s drain factor). There $I_{on}/I_{off} = 10^{V_{DD}/S} \approx$ 6.5 for each transistor (6.56; 6.49 at 65 mV).

Full solution

FN17-10c: the supply for minimum energy (about 8 points)

FN17-10, p21–22. Consider a chain of eight identical $10\,\mu m/5\,\mu m$ inverters. The chain is loaded at the end by 30 fF. In this problem, we are going to calculate the supply voltage at which this inverter chain will consume minimum energy. This will be subthreshold operation. Let the gate capacitance per unit width be given by 2 fF/µm. (a) Assume the $I_{off}$ of each transistor is 10 nA. If the subthreshold slope is 80 mV/decade, what is the on-current of the devices of the inverter as a function of $V_{DD}$VDD​? (b) Estimate the delay of the inverter chain (as a function of $V_{DD}$VDD​). (The point values are overwritten on the scan; each appears to be 8.)

FN17-10 prints no figure. This is the chain’s energy model (Chapter 23 §16, added): for FN17-10, $N = N_g = 8$ inverters, every node $C = (10 + 5)$ µm × 2 fF/µm = 30 fF, $I_{off}$ = 10 nA, $S$ = 80 mV/decade. Parts (a)–(b), solved on FN2, give $I_{on} = I_{off}10^{V_{DD}/S}$ and the chain’s 50 % delay $T = 8CV_{DD}/(2I_{on})$8CVDD​/(2Ion​).

Part (c): the switching energy and the supply that minimizes it (about 8 points)

FN17-10c, p22. Estimate the switching energy of the inverter chain as a function of $V_{DD}$VDD​. Include both the dynamic power dissipated and the leakage of all the inverters during the delay time of the chain. What value of $V_{DD}$ minimizes this energy? (Point value overwritten on the scan; it appears to be 8.)

Hint

Write the dynamic energy and the leakage energy each as something times $CV_{DD}^2$CVDD2​. As $V_{DD}$ falls, which factor shrinks and which grows, and which wins?

Recognize. The subthreshold supply, minimum energy: “switching energy … include both the dynamic power dissipated and the leakage … during the delay time of the chain”, “what value of $V_{DD}$ minimizes this energy?”. About 6 minutes: the energy in four lines, the test for a minimum in two, the answer and the key’s number in three.

On the paper.

1. One transition: 4 of the 8 nodes rise, each drawing $CV_{DD}^2$CVDD2​: $E_{dyn} = 4CV_{DD}^2$4CVDD2​, $C$ = 30 fF
2. From (b): $T = 8CV_{DD}/(2I_{on})$8CVDD​/(2Ion​), $I_{on} = I_{off}10^{V_{DD}/S}$
3. Leakage: 8 inverters × $I_{off}V_{DD}T$ $= 32CV_{DD}^2\,10^{-V_{DD}/S}$ ($I_{off}$Ioff​ cancels)
4. $E = 4CV_{DD}^2\big[1 + 8\cdot10^{-V_{DD}/0.08}\big]$ (16 with the full-swing delay $CV_{DD}/I_{on}$CVDD​/Ion​)
5. $u = V_{DD}\ln 10/S$VDD​ln10/S: $E \propto u^2(1 + 8e^{-u})$8e−u), $dE/du = 2ue^{-u}(e^u - 4u + 8)$
6. $e^u - 4u + 8 \ge 6.45$ (at $u = \ln 4$ln4) $> 0$0: no stationary point (with 16: $\ge 7.36$7.36)
7. $E$ falls as $V_{DD}$ falls, so go to the lowest working supply
8. FN10-2c’s 10–90 % criterion, same $S$ and $kT/q$kT/q: $V_{DD} \approx$ 65 mV, $E$ = 1.14 fJ
9. The intended 0.133 V minimizes the charge $4CV_{DD} + 8I_{off}T$ with the key’s full-swing $T = 8CV_{DD}/I_{on}$8CVDD​/Ion​, not the energy

The energy (FT1’s plot): it rises for every $V_{DD}$VDD​, so the minimum sits at the functional limit. Original figure ↗

Watch out. Energy is charge times $V_{DD}$VDD​: write $CV_{DD}^2$ and $I_{off}V_{DD}T$Ioff​VDD​T, not $CV_{DD}$ and $I_{off}T$Ioff​T. The key does the latter, which is how it finds a minimum. In general a minimum exists only if $K = N/(4\alpha) \ge e^3 \approx 20$20; this chain has $K = 4$4.

Answer: $E(V_{DD}) = 4CV_{DD}^2 + 8I_{off}V_{DD}T = 4(30\ \text{fF})V_{DD}^2\big[1 + 8\cdot10^{-V_{DD}/0.08}\big]$ (16 in place of 8 with the full-swing delay). $dE/dV_{DD} > 0$ for every $V_{DD}$VDD​: there is no interior minimum. The energy falls all the way down to the functional limit, so the minimum-energy supply is the lowest working supply, about 65 mV by FN10-2c’s 10–90 % criterion (about 1.1 fJ per transition). The intended answer, 0.133 V, is the minimum of the charge form the key writes, not of the energy.

Full solution