FN19: the 2019 final

The Fall 2019 final (250 points). There is no official key: the guide re-solves every part and notes where the unofficial proposed solutions differ. Work through it in order: each part gives its question in short and links to the page that solves it, and to its exam way where the page has one. The exam ways of F1–F3 come with their rebuild in early December.

24 parts: all solved in the guide, 10 with an exam way.

FN19-1

FN19-1a (10 points)

An inverter with $V_T = 0.32$ V and 90 mV/decade, at $V_{DD} = 1.2$ V: the off-current and $I_{on}/I_{off}$Ion​/Ioff​.

Full solution

FN19-1b (10 points)

$I_{on}/I_{off}$ at $V_{DD} = 0.2$ V.

Full solution

FN19-1c (10 points)

Its delay into 10 fF at 0.2 V.

Full solution

FN19-1d (10 points)

Driven by a 1 GHz square wave at 0.2 V, its average power.

Full solution

FN19-2

FN19-2a (10 points)

Why does a short-channel device’s threshold fall as $V_{DS}$ rises?

Full solution

FN19-2b (10 points)

Why did shorter channels have lower thresholds before halo doping ($V_T$VT​ roll-off)?

Full solution

FN19-2c (10 points)

With halo doping, why do shorter channels give higher thresholds (inverse roll-off)?

Partly beyond the lectures, which name inverse roll-off but not halo doping; F1 marks its added step.

Full solution

FN19-3

FN19-3a (10 points)

A four-bit ripple-carry chain with W = 1 µm: the delay from $C_{in}$ to $C_{out}$Cout​.

Full solution

FN19-3b (10 points)

At 1.2 V and W = 1 µm, the energy of one propagated transition.

Full solution

FN19-3c (9 points)

The W that minimizes the delay, and the energy at that W.

Full solution

FN19-3d (10 points)

Repeat (c) with $C_{load} = 0$0.

Full solution

FN19-4 (20 points)

Sketch scan_enable, clock, scan_in and scan_out for a scan test that detects a stuck-at-1 fault at node X, and show where it is detected.

Full solution · The exam way

FN19-5

FN19-5a (10 points)

Two clock-chopped flip-flops, 200 ps of logic, CLK2 100 ps early: the widest pulse $\Delta$ that still works.

Full solution · The exam way

FN19-5b (12 points)

That chopped clock is driven by a 4 µm/2 µm inverter into 200 fF: sketch it as the latch receives it, and give its height.

Full solution · The exam way

FN19-6

FN19-6a (10 points)

A dynamic PLA with correctly derived clocks: $y_0$ and $y_1$ as functions of the inputs.

Full solution · The exam way

FN19-6b (8 points)

Design a replica AND row, used twice, that generates $\phi_{AND}$ and $\phi_{OR}$ϕOR​.

Full solution · The exam way

FN19-7

FN19-7a (8 points)

A global wire whose capacitance per unit length is 0.04 fF/µm plus 0.15 fF/µm² times its width: why this form?

Full solution · The exam way

FN19-7b (10 points)

The Elmore delay from A to B.

Full solution · The exam way

FN19-7c (8 points)

With an FO1 delay of 50 ps, must resistance be considered in the delay from A to B? Explain.

Full solution · The exam way

FN19-7d (10 points)

Widen the wire from A to X from 0.4 µm to 10 µm: the Elmore delay from A to B now.

Full solution · The exam way

FN19-8

FN19-8a (10 points)

A dynamic gate and two static gates: the A-rising-to-E-rising delay in evaluate with every width 1 µm and no side branch.

Full solution

FN19-8b (15 points)

Keep $W_1 = 1$ µm and resize for minimum delay, with every β ratio between 0.25 and 4.

Full solution

FN19-8c (10 points)

With (b)‘s sizes, the delay with a 200 fF side branch.

Full solution

FN19-9 (10 points)

A pass-transistor latch cannot be written: Y ignores A while clk is high. What went wrong, and how is it fixed?

Full solution · The exam way