MT17: the 2017 midterm

The Fall 2017 midterm (November 1, 2017; 150 points). Work through it in order: each part gives its question in short and links to the page that solves it. The exam ways of M3, M5 and M6 come with their rebuild in early December; until then, use the full solutions and the playbook.

16 parts: all solved in the guide.

MT17-1

MT17-1a (8 points)

What does fanout do to the static DC noise margin of a CMOS gate? Explain.

MT17-1b (8 points)

An inverter’s PFET has its n-well tied to ground, with $V_{DD} = 2.5$ V and $V_{in} = 0$ . Does static DC current flow? Explain.

MT17-1c (8 points)

An NFET carries 10 µA at $V_{GS} = V_T = 1$ V. Find $I_D$ at $V_{GS} = 0$ at 300 K (60 mV/decade), and again at 400 K.

MT17-2 (16 points)

Label three inverter VTCs by their sizes (4/1, 2/1 and 1/1 µm) and explain; which has the largest $NM_H$ ?

MT17-3

MT17-3a (8 points)

With equal-strength devices, an inverter with a 2 µm PFET and a 1 µm NFET drives 50 fF: its rising and falling delays in units of $\tau_{inv}$ .

MT17-3b (8 points)

The same with an 8 µm PFET and a 1 µm NFET.

MT17-3c (8 points)

A dynamic gate’s A-rising-to-Y-falling delay in evaluation (clk = 1, B = 1).

MT17-3d (8 points)

A four-input NAND’s rising and falling delays with B = C = D = 1.

MT17-4

MT17-4a (8 points)

Four 2W/W inverters with no wiring capacitance ( $C_x = 0$ ): the delay from A to B. Does it depend on W? Why?

MT17-4b (10 points)

With wiring capacitance $C_x$ between stages: the delay as a function of W and $C_x$ , and the W that minimizes it.

MT17-4c (10 points)

The dynamic energy of one transition through the chain, as a function of W and $C_x$ .

MT17-4d (10 points)

The W that minimizes energy × delay.

MT17-5

MT17-5a (10 points)

A four-gate path with PFETs half as strong as NFETs: the A-to-E delay with every width 1 µm.

MT17-5b (10 points)

Keep $W_1 = 1$ µm and size $W_2$ – $W_4$ for minimum delay; give the new delay.

MT17-5c (10 points)

A branch inverter is added: the delay with the sizes of (b).

MT17-5d (10 points)

Retune the modified circuit, $W_1$ still fixed, and give the new delay.