FS1. Flip-flop and latch timing: the exam way

This is the exam way of FS1: each part as you would write it on the paper, with what to recognize, the lines to write, the trap to watch and the answer. Every part keeps the anchor it has on FS1, so the switch at the top of the page takes you to the same part’s full solution. The methods are two cards of the playbook: flip-flop timing for FN17-5, FN12-7b and FN10-6c–d, and latch loops for PS5-Q1. FS1’s five harder variations stay on FS1; work them there, against the budgets their titles give.

The clock. The past finals gave 180 minutes for 200–250 points. FN17 had 250 points, about 0.72 min a point, so a 10-point part has about 7 minutes; FN10 and FN12 had 200, 0.9 min a point, so a 15-point part has about 14 minutes. PS5 is a problem set and has no points: each of its parts gets the budget of a final part with the same amount of work (5 to 12 points) at 0.9 min a point.

Two conventions run through every line below: latches are transparent high, and skew is signed, $\delta$ = (capture edge) − (launch edge), so $\delta > 0$ is a late capture clock.

FN17-5: four latches, two flip-flops, 50 ps of skew (40 points)

FN17-5, p11. Consider the path through the two flip-flops shown below. Assume that the $\phi_1'$ and $\phi_2'$ clocks are skewed to arrive 50 psec earlier than the corresponding $\phi_1$ and $\phi_2$ clocks. Let each latch be characterized by $t_{setup} = 5$ psec, $t_{clk-q} = 10$ psec, and $t_{d-q} = 10$ psec. Let the cycle time of the clock be 500 psec.

FN17-5’s path (p11, redrawn): latches on φ1 and φ2, the logic, latches on φ1′ and φ2′. Read in pairs, it is two master–slave flip-flops.

Reading the figure

Write this once. The question draws no clocks; the key’s sketch confirms $\phi_2 = \overline{\phi_1}$ and the primes the same waveforms 50 ps early. With φ1 rising at 0 in a 500 ps cycle:

Edge	Time (ps)	Role
φ2 rises (first pair’s slave opens)	250	launch; Q moves at 260
φ1′ falls (second pair’s master closes)	200, then 700	capture: this cycle’s, then the next

So $\delta = -50$ ps. No hold time is given: $t_{hold} = 0$0.

Part (a): does it work with no logic? (10 points)

FN17-5a, p11. If $t_{logic} = 0$ psec, will this circuit function correctly? Explain. (10 points)

Hint

With no logic at all, which of the two constraints is in danger, and in which direction does an early capture clock push it?

Recognize. Flip-flop timing, moves 1–3: read the pairs, sign the skew, check hold first. About 7 minutes.

On the paper.

1. Pairs: (φ1, φ2) launches as φ2 opens; (φ1′, φ2′) captures as φ1′ closes
2. Primes early: $\delta = -50$ ps; $t_{hold} = 0$ (not given)
3. Hold: $t_{clk\to Q} + t_{logic} \ge \delta + t_{hold}$
4. $10 + 0 \ge -50 + 0$ ✓, margin 60 ps
5. In time: Q moves at 260 ps; φ1′ shut at 200 ps
6. Setup at $t_{logic} = 0$0: $260 \le 700 - 5$ ✓

Watch out. “Earlier” makes $\delta$ negative, and an early capture clock only helps hold. Writing $+50$ as if skew always hurt hold gives a failure (by 40 ps) that belongs to the late case.

Answer: yes. The receiving master closes 50 ps before the new data is launched: no hold (early-mode) problem, 60 ps of margin, and the long path at $t_{logic} = 0$ is easily met.

Full solution

Part (b): the largest logic delay (10 points)

FN17-5b, p11. What is the largest value of $t_{logic}$ for which the circuit will work? Explain. (10 points)

Hint

Which edge must the data beat, and how far after the launch does that edge come when the capture clock is 50 ps early?

Recognize. Flip-flop timing, move 4: “largest $t_{logic}$tlogic​” is the long path. About 7 minutes.

On the paper.

1. Long path: $t_{clk\to Q} + t_{logic} + t_{setup} \le T_{cycle} + \delta$
2. $t_{logic} \le 500 - 50 - 10 - 5 = 435$ ps
3. In time: start $250 + 10 = 260$260; deadline $700 - 5 = 695$695; $695 - 260 = 435$ ✓
4. $t_{d-q}$ unused: the slave is shut while the master’s output moves

Watch out. Two tempting wrong numbers: adding $t_{d-q}$ (425 ps), and $+50$ for the early clock (535 ps). An early capture edge comes sooner, so it can only take time away.

Answer: $t_{logic} \le 435$ ps, 50 ps less than with no skew (485 ps).

Full solution

Part (c): repairing the clocks (10 points)

FN17-5c, p12. If the circuit is not functional in (a), how can the $\phi_1$ and $\phi_2$ clocks be modified such that the circuit will function correctly. (10 points)

Hint

Is the condition “if the circuit is not functional in (a)” met?

Recognize. Flip-flop timing, move 5 (repairs), but conditional on (a). About 7 minutes; the answer itself is short.

On the paper.

1. Condition: (a) works, hold margin 60 ps
2. So no change to φ1 and φ2 is needed
3. Had it failed (late primes): open a window, φ1 falling before φ2 rising
4. $t_{overlap} \ge \delta + t_{hold} - t_{clk\to Q} - t_{logic}$tlogic​; the long path loses $t_{overlap}$

Watch out. Read the condition literally. Do not “fix” the 50 ps by delaying the primed clocks: the circuit works, and the question asks about φ1 and φ2.

Answer: the circuit in (a) works, so no modification of φ1 and φ2 is required.

Full solution

Part (d): the largest logic delay now (10 points)

FN17-5d, p12. What is the largest value of $t_{logic}$ now for which the circuit will work? Explain. (10 points)

Hint

“Now” means after part (c)‘s change. What did part (c) change?

Recognize. Flip-flop timing, move 4 after move 5: the long path after the repair. About 7 minutes; the answer itself is short.

On the paper.

1. (c) changed nothing: $t_{overlap} = 0$0, $\delta = -50$ ps
2. $t_{logic} \le T_{cycle} + \delta - t_{clk\to Q} - t_{setup} - t_{overlap}$
3. $= 500 - 50 - 10 - 5 - 0 = 435$ ps

Watch out. Subtract a window only if (c) opened one. With a window it would be $435 - t_{overlap}$toverlap​.

Answer: 435 ps, the same as (b).

Full solution

FN12-7b: two clock generators, 1.5 ns apart (15 points)

FN12-7, p8. Consider the “local clock generator” circuit shown below, used to generate two clock phases locally from a single-wire global clock. The delay blocks (labelled with $\Delta_1$ and $\Delta_2$Δ2​) could be implemented with an even number of inverters (for example).

FN12-7’s local clock generator (p8, redrawn): $\phi_1 = \text{NOR}(\phi, \Delta_1(\phi_2))$NOR(ϕ,Δ1​(ϕ2​)), $\phi_2 = \text{NOR}(\overline\phi, \Delta_2(\phi_1))$NOR(ϕ​,Δ2​(ϕ1​)).

Part (b): adjusting Δ1 and Δ2 (15 points)

FN12-7b, p9. Consider two latches driven by two different clock generators as shown below: Let CLK1 and CLK2 each have 10nsec periods, but let there be skew between CLK1 and CLK2 such that CLK2 arrives 1.5nsec later than CLK1. Ignoring latch overhead and skew introduced by the clock generators and assuming that the combinational logic represented a fixed delay of 0.5nsec, how must $\Delta_1$ and $\Delta_2$ in the clock generators be adjusted (from zero) to ensure correct functionality? Please assume that both clock generators must be adjusted in the same way and carefully explain your answer. (15 points)

On the paper, “latches” is crossed out by hand and replaced by “flip-flops”.

FN12-7b’s system (p9, redrawn): in each flip-flop the first latch (the master) is on φ2, the second (the slave) on φ1; 0.5 ns of logic between them.

Hint

Which phase drives each pair’s master, and so which edge captures and which launches? Then: which of the two delays sits between them?

Recognize. Flip-flop timing, move 5: a late capture clock, a short path, and a repair by a local non-overlap window. About 14 minutes.

On the paper.

1. NOR: φ falls → φ2 falls at once, φ1 rises $\Delta_1$ later
2. φ rises → φ1 falls at once, φ2 rises $\Delta_2$ later
3. p9: master on φ2, slave on φ1
4. Capture: φ2 falls = CLK falling; launch: φ1 rises = CLK1 falling $+ \Delta_1$
5. $\delta = +1.5$ ns, $t_{logic} = 0.5$ ns, overheads 0
6. As drawn: data at $5 + 0.5 = 5.5$ ns, CG2’s master open until 6.5 ns ✗
7. Hold: $\Delta_1 + 0.5 \ge 1.5$1.5, so $\Delta_1 \ge 1.0$ ns
8. $\Delta_2$ only delays the master’s opening: leave 0
9. Ceiling: $\Delta_1 < T_{cycle}/2 = 5$ ns (or φ1 never rises)

Watch out. Find the master’s phase on p9 first. Chapter 14’s board flip-flop has its master on φ1, whose slave opens $\Delta_2$ after the master closes, so its knob is $\Delta_2$Δ2​; here the master is on φ2, so the knob is $\Delta_1$Δ1​.

Answer: raise $\Delta_1$ to at least 1.0 ns (and below 5 ns) in both generators; leave $\Delta_2 = 0$0. The launch then waits until the 0.5 ns path can no longer beat CLK2’s 1.5 ns late capture.

Full solution

FN10-6c–d: jitter from a noisy supply (15 points)

FN10-6, p9. One of the issues in using inverters as delay elements (or in distributing clocks) is that they have a high sensitivity to power-supply variations. Let’s try to calculate this (back-of-the-envelope).

Part (a), solved on FN1, gives the sensitivity $\frac{V_{DD}}{t_{delay}}\frac{\partial t_{delay}}{\partial V_{DD}} = -0.25$ for a velocity-saturated inverter at $V_{DD} = 2.5$ V, $|V_T| = 0.5$ V.

FN10-6c–d’s setting, drawn from the words (the paper prints no figure): a 2 ns inverter tree on a 2.0–2.5 V supply, and two flip-flops on different leaves.

Part (c): the jitter (8 points)

FN10-6c, p10. Assume that I am distributing a clock through a fan-out tree of inverters, where the delay from root to leaf is $2nsec$2nsec. If my power supply is varying between 2.5 V and 2.0 V (power supply noise), what jitter can I expect on the clock? Use the sensitivity you calculated in (a). (8 points)

Hint

If every inverter in the tree slows by the same fraction, by how much does the root-to-leaf delay change?

Recognize. Flip-flop timing, move 6: jitter from a sensitivity and a latency. About 7 minutes.

On the paper.

1. $S = -V_T/(V_{DD} - V_T) = -0.5/2.0 = -0.25$ (part a)
2. $\Delta V_{DD}/V_{DD} = (2.0 - 2.5)/2.5 = -0.2$
3. $\Delta t/t \approx S\,\Delta V_{DD}/V_{DD} = (-0.25)(-0.2) = +0.05$
4. Whole tree slows 5%: $\Delta t \approx 0.05 \times 2\,\mathrm{ns} = 100$ ps

Watch out. Scale the whole 2 ns latency, not one inverter. Use (a)‘s $-0.25$−0.25; the square-law $-1.5$ of part (b) would give 600 ps. The first-order answer is low: the exact model gives 133 ps.

Answer: about 100 ps of jitter.

Full solution

Part (d): a failure the clock cannot fix (7 points)

FN10-6d, p10. Assume that I have a flop-based design with $t_{clk-q} = 100psec$ and $t_{hold} = 50psec$50psec. Could this jitter result in functional failure of the design, functional failure that could not be eliminated by slowing down the clock? If functional failure is possible, what steps would I have to take as a designer to avoid it (assuming that I cannot change the jitter characteristics of the clock)? (7 points)

Hint

Which of the two timing checks has no clock period in it, and what does 100 ps of jitter look like to a pair of flip-flops on different leaves?

Recognize. Flip-flop timing, moves 3 and 6: “cannot be eliminated by slowing down the clock” is the short path, and jitter enters it as skew. About 6 minutes.

On the paper.

1. Jitter as skew: the capture edge up to $\delta = +100$ ps late
2. Hold: $t_{clk\to Q} + t_{logic} \ge \delta + t_{hold}$
3. $100 + t_{logic} \ge 100 + 50$50, so $t_{logic} \ge 50$ ps
4. Back-to-back flip-flops ($t_{logic} = 0$tlogic​=0): $100 \ge 150$ ✗
5. No $T_{cycle}$ in it: a slower clock cannot help
6. Fix: pad every short path to ≥ 50 ps (fast corner)

Watch out. Jitter’s long-path effect (a shorter cycle) is the one a slower clock fixes. The question asks about the other check.

Answer: yes. Hold needs $t_{logic} \ge 50$ ps, so back-to-back flip-flops fail, at any clock speed. Pad every short path to at least 50 ps.

Full solution

PS5-Q1: five latch loops

PS5-Q1, p1–p2. In each of the following examples, indicate if the circuit is functional (i. e., it is a valid FSM). If the circuit is not functional, indicate how the circuit, delays, or clocks could be modified to ensure functionality. Try to explore more than one possibility. Even if the circuit is functional, indicate any issues with the design that you might see. “Primed” clocks indicate clock skew with respect to the “unprimed” clocks; you cannot change this skew time. All of the latches are active high. For simplicity, you may assume that the setup and hold times to the closing edge of the latch are zero. You may also assume that the latch adds no delay.

PS5-Q1’s clocks (p2, redrawn): φ1 and φ2 complementary, 5 ns high and 5 ns low; φ1′ and φ2′ the same, 1.5 ns late. Parts (d) and (e) use the same clocks.

The windows

Write them once, with φ1 rising at 0 in each 10 ns cycle: φ1 open on [0, 5), φ2 on [5, 10), φ1′ on [1.5, 6.5), φ2′ on [6.5, 11.5). Setup, hold and the latches’ delays are zero.

Part (a): one latch in a 7 ns loop

PS5-Q1a, p1. (a) [One latch on φ1, 5 nsec high and 5 nsec low, fed back to itself through comb logic, delay = 7nsec.]

PS5-Q1a (p1, redrawn): one φ1 latch fed back through 7 ns.

Hint

While the latch is open, the loop is just logic. Can a change made when it opens come all the way round before it closes?

Recognize. Latch loops: a single latch fed back on itself, checked on both sides. About 5 minutes.

On the paper.

1. One latch: a one-cycle loop, open 5 ns of every 10
2. Race: leaves at 0, back at 7; latch shut at 5 ✓ (2 ns)
3. Rule 2: $7 \le 10$ ✓; waits 3 ns, leaves again at 10
4. One state change per cycle: functional
5. Needs the shortest path ≥ 5 ns; at 50% duty, $7 \le T_{cycle} \le 14$ ns
6. 3 ns of every cycle is dead time

Watch out. The loop has a lower bound as well as an upper one: it must be slower than the open time. A faster logic corner, a longer high phase or a much slower 50% clock breaks it.

Answer: functional: $5 < 7 \le 10$ ns, 2 ns of race margin. Issues: it relies on a minimum delay of 5 ns (at 50% duty, $7 \le T_{cycle} \le 14$ ns), and 3 ns a cycle is dead time; a pulse or a flip-flop is safer.

Full solution

Part (b): a φ1–φ2 pair in a 12 ns loop

PS5-Q1b, p1. (b) [φ1 and φ2, each 5 nsec high and 5 nsec low; a latch on φ1, then a latch on φ2, fed back through comb logic, delay = 12 nsec.]

PS5-Q1b (p1, redrawn): a φ1 latch, a φ2 latch, and 12 ns back.

Hint

How many cycles does a loop through one φ1 latch and one φ2 latch hold?

Recognize. Latch loops, rule 2: a flip-flop fed back on itself. About 5 minutes.

On the paper.

1. φ1 then φ2 directly = a flip-flop: one cycle in the loop
2. Rule 2: $12 > 10$ ✗
3. Walk: leaves φ2 at 5, reaches φ1 at 17; φ1 shut at 15 (−2 ns)
4. Not functional
5. Fix 1: $T_{cycle} \ge 12$ ns (83.3 MHz)
6. Fix 2: logic ≤ 10 ns
7. Moving logic between the latches: still 12 ns in one cycle ✗

Watch out. No borrowing in a one-cycle loop: there is no second cycle to borrow from, and no launch point rescues a loop that fails rule 2.

Answer: not functional (12 ns of logic in a one-cycle, 10 ns loop). Fixes: $T_{cycle} \ge 12$ ns, or logic ≤ 10 ns.

Full solution

Part (c): two flip-flops, 1 ns forward and 11 ns back

PS5-Q1c, p2. (c) [Latches φ1, φ2, comb logic delay = 1nsec, latches φ1′, φ2′, and comb logic delay = 11 nsec back to the first latch; φ1′ and φ2′ 1.5 nsec late.]

PS5-Q1c (p2, redrawn): flip-flop A (φ1, φ2), 1 ns, flip-flop B (φ1′, φ2′), 11 ns back.

Hint

Read the latches in pairs. What does the late primed pair do to the short 1 ns path, and to the long 11 ns one?

Recognize. Latch loops, read as two flip-flops: the flip-flop timing checks, one per direction. About 11 minutes.

On the paper.

1. Rule 2: four latches, two cycles: $12 \le 20$ ✓
2. A → B, hold, $\delta = +1.5$+1.5: $1 \ge 1.5$ ✗ (data at 6, φ1′ open until 6.5)
3. B → A, setup, $\delta = -1.5$−1.5: $11 \le 10 - 1.5 = 8.5$ ✗ ($16.5 + 11 = 27.5 > 25$16.5+25)
4. Not functional, for two reasons
5. Fix 1: pad the 1 ns path to ≥ 1.5 ns and $T_{cycle} \ge 11 + 1.5 = 12.5$ ns
6. Fix 2: pad, and the return logic ≤ 8.5 ns
7. Fix 3: a 0.5 ns non-overlap window, $T_{cycle} \ge 11 + 1.5 + 0.5 = 13$ ns
8. Fix 4, at 10 ns: pad to 2 ns, move φ2′ 5 ns (at least 2.5 ns) into the 11 ns block

Watch out. A slower clock does not cure the race: with 50% phases φ1′ still closes 0.5 ns after the data arrives, at any period. The race needs padding or a window.

Answer: not functional: a hold race A → B (0.5 ns too fast) and a long path B → A (11 > 8.5 ns). Pad the 1 ns path to ≥ 1.5 ns and run at $T_{cycle} \ge 12.5$ ns or speed the return to ≤ 8.5 ns; or a 0.5 ns window with $T_{cycle} \ge 13$ ns; or, at 10 ns, pad to 2 ns and move φ2′ 5 ns into the 11 ns block.

Full solution

Part (d): 2 ns, 11 ns and 4 ns

PS5-Q1d, p2. (d) [Latches φ1, φ2, comb logic delay = 2 nsec, latch φ1′, comb logic delay = 11 nsec, latch φ2′, and comb logic delay = 4 nsec back to the first latch.]

PS5-Q1d (top) and Q1e (bottom) (p2, redrawn), both on part (c)‘s clocks.

Hint

When can the data leave the φ1′ latch at the earliest, and when does φ2′ close?

Recognize. Latch loops, move 5: rule 2 holds, but a wait restarts the clock at φ1′. About 8 minutes.

On the paper.

1. Rule 2: $2 + 11 + 4 = 17 \le 20$ ✓
2. Race into φ1′: $5 + 2 = 7 > 6.5$ ✓ (0.5 ns)
3. Data waits at φ1′ until it opens at 11.5
4. $11.5 + 11 = 22.5 >$ φ2′‘s close at 21.5 ✗ (1 ns): not functional
5. Chain from 11.5: to φ2′, block ≤ 10; to φ1 (closes 25), block + 4 ≤ 13.5
6. Fix 1: block ≤ 9.5 ns
7. Fix 2: move φ1′ ≥ 1.5 ns into the block (4.5–6.5 ns: 3 ns margin)
8. Fix 3: $T + 1.5 + 11 \le 2T + 1.5$ and $T + 16.5 \le 2.5T$2.5T: $T_{cycle} \ge 11$ ns

Watch out. A 10 ns block meets φ2′ exactly but reaches φ1 at 25.5 ns, after it closes. Check every closing edge after the wait, not only the next one.

Answer: not functional: from φ1′‘s opening (11.5 ns) the 11 ns block reaches φ2′ 1 ns after it closes. Fixes: the block ≤ 9.5 ns; or move φ1′ at least 1.5 ns into it; or $T_{cycle} \ge 11$ ns. Issue: the 2 ns path has only 0.5 ns of hold margin.

Full solution

Part (e): a 21 ns loop in two cycles

PS5-Q1e, p2. (e) [Latch φ1, comb logic delay = 6 nsec, latch φ2, delay = 5 nsec, latch φ1′, delay = 6 nsec, latch φ2′, and delay = 4 nsec back to the first latch.]

PS5-Q1e (the lower loop): the last two latches are on the primed clocks. Original figure ↑

Hint

Add the four blocks. Then ask what happens to the departure time from φ1 lap after lap.

Recognize. Latch loops, rule 2 first: every block is short, so only the sum shows the failure. About 8 minutes.

On the paper.

1. Rule 2: $6 + 5 + 6 + 4 = 21 > 20$ ✗
2. Lap 1: φ2 at 6, φ1′ at 11 (waits to 11.5), φ2′ 17.5, φ1 21.5: all met
3. Then every lap takes 21 ns: φ1 left 1.5, 2.5, 3.5, 4.5 ns into its window
4. φ2’s margin: 4, 2.5, 1.5, 0.5, −0.5 ns
5. Lap 5: φ2 reached at 90.5, shut at 90 ✗: not functional
6. Fix 1: $2T_{cycle} \ge 21$21: $T_{cycle} \ge 10.5$ ns (95.2 MHz)
7. Fix 2: cut ≥ 1 ns of logic anywhere in the loop

Watch out. One good lap proves nothing. If you only walk lap 1, you call it functional.

Answer: not functional: 21 ns of logic in a two-cycle (20 ns) loop; each lap ends 1 ns later, and lap 5 misses φ2 (90.5 against 90 ns). Fixes: $T_{cycle} \ge 10.5$ ns, or at least 1 ns less logic.

Full solution